arch/arm/mach-omap2/timer-gp.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer-gp.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38
  39 #include <asm/mach/time.h>
  40 #include <plat/dmtimer.h>
  41 #include <asm/localtimer.h>
  42 #include <asm/sched_clock.h>
  43 #include <plat/common.h>
  44 #include <plat/omap_hwmod.h>
  45
  46 #include "timer-gp.h"
  47
  48 /* Parent clocks, eventually these will come from the clock framework */
  49
  50 #define OMAP2_MPU_SOURCE        "sys_ck"
  51 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
  52 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
  53 #define OMAP2_32K_SOURCE        "func_32k_ck"
  54 #define OMAP3_32K_SOURCE        "omap_32k_fck"
  55 #define OMAP4_32K_SOURCE        "sys_32k_ck"
  56
  57 #ifdef CONFIG_OMAP_32K_TIMER
  58 #define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
  59 #define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
  60 #define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
  61 #define OMAP3_SECURE_TIMER      12
  62 #else
  63 #define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
  64 #define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
  65 #define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
  66 #define OMAP3_SECURE_TIMER      1
  67 #endif
  68
  69 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
  70 #define MAX_GPTIMER_ID          12
  71
  72 u32 sys_timer_reserved;
  73
  74 /* Clockevent code */
  75
  76 static struct omap_dm_timer clkev;
  77 static struct clock_event_device clockevent_gpt;
  78 static u8 __initdata gptimer_id = 1;
  79 static u8 __initdata inited;
  80
  81 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  82 {
  83         struct clock_event_device *evt = &clockevent_gpt;
  84
  85         __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
  86
  87         evt->event_handler(evt);
  88         return IRQ_HANDLED;
  89 }
  90
  91 static struct irqaction omap2_gp_timer_irq = {
  92         .name           = "gp timer",
  93         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  94         .handler        = omap2_gp_timer_interrupt,
  95 };
  96
  97 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  98                                          struct clock_event_device *evt)
  99 {
 100         __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
 101                                                 0xffffffff - cycles, 1);
 102
 103         return 0;
 104 }
 105
 106 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 107                                     struct clock_event_device *evt)
 108 {
 109         u32 period;
 110
 111         __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
 112
 113         switch (mode) {
 114         case CLOCK_EVT_MODE_PERIODIC:
 115                 period = clkev.rate / HZ;
 116                 period -= 1;
 117                 /* Looks like we need to first set the load value separately */
 118                 __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
 119                                         0xffffffff - period, 1);
 120                 __omap_dm_timer_load_start(clkev.io_base,
 121                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 122                                                 0xffffffff - period, 1);
 123                 break;
 124         case CLOCK_EVT_MODE_ONESHOT:
 125                 break;
 126         case CLOCK_EVT_MODE_UNUSED:
 127         case CLOCK_EVT_MODE_SHUTDOWN:
 128         case CLOCK_EVT_MODE_RESUME:
 129                 break;
 130         }
 131 }
 132
 133 static struct clock_event_device clockevent_gpt = {
 134         .name           = "gp timer",
 135         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 136         .shift          = 32,
 137         .set_next_event = omap2_gp_timer_set_next_event,
 138         .set_mode       = omap2_gp_timer_set_mode,
 139 };
 140
 141 /**
 142  * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
 143  * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
 144  *
 145  * Define the GPTIMER that the system should use for the tick timer.
 146  * Meant to be called from board-*.c files in the event that GPTIMER1, the
 147  * default, is unsuitable.  Returns -EINVAL on error or 0 on success.
 148  */
 149 int __init omap2_gp_clockevent_set_gptimer(u8 id)
 150 {
 151         if (id < 1 || id > MAX_GPTIMER_ID)
 152                 return -EINVAL;
 153
 154         BUG_ON(inited);
 155
 156         gptimer_id = id;
 157
 158         return 0;
 159 }
 160
 161 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 162                                                 int gptimer_id,
 163                                                 const char *fck_source)
 164 {
 165         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 166         struct omap_hwmod *oh;
 167         size_t size;
 168         int res = 0;
 169
 170         sprintf(name, "timer%d", gptimer_id);
 171         omap_hwmod_setup_one(name);
 172         oh = omap_hwmod_lookup(name);
 173         if (!oh)
 174                 return -ENODEV;
 175
 176         timer->irq = oh->mpu_irqs[0].irq;
 177         timer->phys_base = oh->slaves[0]->addr->pa_start;
 178         size = oh->slaves[0]->addr->pa_end - timer->phys_base;
 179
 180         /* Static mapping, never released */
 181         timer->io_base = ioremap(timer->phys_base, size);
 182         if (!timer->io_base)
 183                 return -ENXIO;
 184
 185         /* After the dmtimer is using hwmod these clocks won't be needed */
 186         sprintf(name, "gpt%d_fck", gptimer_id);
 187         timer->fclk = clk_get(NULL, name);
 188         if (IS_ERR(timer->fclk))
 189                 return -ENODEV;
 190
 191         sprintf(name, "gpt%d_ick", gptimer_id);
 192         timer->iclk = clk_get(NULL, name);
 193         if (IS_ERR(timer->iclk)) {
 194                 clk_put(timer->fclk);
 195                 return -ENODEV;
 196         }
 197
 198         omap_hwmod_enable(oh);
 199
 200         sys_timer_reserved |= (1 << (gptimer_id - 1));
 201
 202         if (gptimer_id != 12) {
 203                 struct clk *src;
 204
 205                 src = clk_get(NULL, fck_source);
 206                 if (IS_ERR(src)) {
 207                         res = -EINVAL;
 208                 } else {
 209                         res = __omap_dm_timer_set_source(timer->fclk, src);
 210                         if (IS_ERR_VALUE(res))
 211                                 pr_warning("%s: timer%i cannot set source\n",
 212                                                 __func__, gptimer_id);
 213                         clk_put(src);
 214                 }
 215         }
 216         __omap_dm_timer_reset(timer->io_base, 1, 1);
 217         timer->posted = 1;
 218
 219         timer->rate = clk_get_rate(timer->fclk);
 220
 221         timer->reserved = 1;
 222
 223         return res;
 224 }
 225
 226 static void __init omap2_gp_clockevent_init(int gptimer_id,
 227                                                 const char *fck_source)
 228 {
 229         int res;
 230
 231         inited = 1;
 232
 233         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
 234         BUG_ON(res);
 235
 236         omap2_gp_timer_irq.dev_id = (void *)&clkev;
 237         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 238
 239         __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
 240
 241         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
 242                                      clockevent_gpt.shift);
 243         clockevent_gpt.max_delta_ns =
 244                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 245         clockevent_gpt.min_delta_ns =
 246                 clockevent_delta2ns(3, &clockevent_gpt);
 247                 /* Timer internal resynch latency. */
 248
 249         clockevent_gpt.cpumask = cpumask_of(0);
 250         clockevents_register_device(&clockevent_gpt);
 251
 252         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
 253                 gptimer_id, clkev.rate);
 254 }
 255
 256 /* Clocksource code */
 257
 258 #ifdef CONFIG_OMAP_32K_TIMER
 259 /*
 260  * When 32k-timer is enabled, don't use GPTimer for clocksource
 261  * instead, just leave default clocksource which uses the 32k
 262  * sync counter.  See clocksource setup in plat-omap/counter_32k.c
 263  */
 264
 265 static void __init omap2_gp_clocksource_init(void)
 266 {
 267         omap_init_clocksource_32k();
 268 }
 269
 270 #else
 271 /*
 272  * clocksource
 273  */
 274 static DEFINE_CLOCK_DATA(cd);
 275 static struct omap_dm_timer *gpt_clocksource;
 276 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 277 {
 278         return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
 279 }
 280
 281 static struct clocksource clocksource_gpt = {
 282         .name           = "gp timer",
 283         .rating         = 300,
 284         .read           = clocksource_read_cycles,
 285         .mask           = CLOCKSOURCE_MASK(32),
 286         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 287 };
 288
 289 static void notrace dmtimer_update_sched_clock(void)
 290 {
 291         u32 cyc;
 292
 293         cyc = omap_dm_timer_read_counter(gpt_clocksource);
 294
 295         update_sched_clock(&cd, cyc, (u32)~0);
 296 }
 297
 298 /* Setup free-running counter for clocksource */
 299 static void __init omap2_gp_clocksource_init(void)
 300 {
 301         static struct omap_dm_timer *gpt;
 302         u32 tick_rate;
 303         static char err1[] __initdata = KERN_ERR
 304                 "%s: failed to request dm-timer\n";
 305         static char err2[] __initdata = KERN_ERR
 306                 "%s: can't register clocksource!\n";
 307
 308         gpt = omap_dm_timer_request();
 309         if (!gpt)
 310                 printk(err1, clocksource_gpt.name);
 311         gpt_clocksource = gpt;
 312
 313         omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
 314         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
 315
 316         omap_dm_timer_set_load_start(gpt, 1, 0);
 317
 318         init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
 319
 320         if (clocksource_register_hz(&clocksource_gpt, tick_rate))
 321                 printk(err2, clocksource_gpt.name);
 322 }
 323 #endif
 324
 325 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src)                  \
 326 static void __init omap##name##_timer_init(void)                        \
 327 {                                                                       \
 328         omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
 329         omap2_gp_clocksource_init();                                    \
 330 }
 331
 332 #define OMAP_SYS_TIMER(name)                                            \
 333 struct sys_timer omap##name##_timer = {                                 \
 334         .init   = omap##name##_timer_init,                              \
 335 };
 336
 337 #ifdef CONFIG_ARCH_OMAP2
 338 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE)
 339 OMAP_SYS_TIMER(2)
 340 #endif
 341
 342 #ifdef CONFIG_ARCH_OMAP3
 343 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE)
 344 OMAP_SYS_TIMER(3)
 345 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE)
 346 OMAP_SYS_TIMER(3_secure)
 347 #endif
 348
 349 #ifdef CONFIG_ARCH_OMAP4
 350 static void __init omap4_timer_init(void)
 351 {
 352 #ifdef CONFIG_LOCAL_TIMERS
 353         twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
 354         BUG_ON(!twd_base);
 355 #endif
 356         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
 357         omap2_gp_clocksource_init();
 358 }
 359 OMAP_SYS_TIMER(4)
 360 #endif