4 * Karthik Dasu <karthik-dp@ti.com>
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/linkage.h>
27 #include <asm/assembler.h>
38 * Registers access definitions
40 #define SDRC_SCRATCHPAD_SEM_OFFS 0xc
41 #define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\
42 (SDRC_SCRATCHPAD_SEM_OFFS)
43 #define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
45 #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
46 #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
47 #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
48 #define SRAM_BASE_P OMAP3_SRAM_PA
49 #define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
50 #define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
51 OMAP36XX_CONTROL_MEM_RTA_CTRL)
53 /* Move this as correct place is available */
54 #define SCRATCHPAD_MEM_OFFS 0x310
55 #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
56 OMAP343X_CONTROL_MEM_WKUP +\
58 #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
59 #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
60 #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
61 #define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
62 #define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
63 #define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
64 #define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
65 #define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
66 #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
67 #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
70 * This file needs be built unconditionally as ARM to interoperate correctly
71 * with non-Thumb-2-capable firmware.
81 * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
82 * This function sets up a flag that will allow for this toggling to take
83 * place on 3630. Hopefully some version in the future may not need this.
85 ENTRY(enable_omap3630_toggle_l2_on_restore)
86 stmfd sp!, {lr} @ save registers on stack
87 /* Setup so that we will disable and enable l2 */
89 adrl r2, l2dis_3630 @ may be too distant for plain adr
91 ldmfd sp!, {pc} @ restore regs and return
92 ENDPROC(enable_omap3630_toggle_l2_on_restore)
95 /* Function to call rom code to save secure ram context */
97 ENTRY(save_secure_ram_context)
98 stmfd sp!, {r4 - r11, lr} @ save registers on stack
99 adr r3, api_params @ r3 points to parameters
100 str r0, [r3,#0x4] @ r0 has sdram address
103 ldr r12, sram_phy_addr_mask
105 mov r0, #25 @ set service ID for PPA
106 mov r12, r0 @ copy secure service ID in r12
107 mov r1, #0 @ set task id for ROM code in r1
108 mov r2, #4 @ set some flags in r2, r6
110 dsb @ data write barrier
111 dmb @ data memory barrier
112 smc #1 @ call SMI monitor (smi #1)
117 ldmfd sp!, {r4 - r11, pc}
124 .word 0x4, 0x0, 0x0, 0x1, 0x1
125 ENDPROC(save_secure_ram_context)
126 ENTRY(save_secure_ram_context_sz)
127 .word . - save_secure_ram_context
130 * ======================
131 * == Idle entry point ==
132 * ======================
136 * Forces OMAP into idle state
138 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
139 * and executes the WFI instruction. Calling WFI effectively changes the
140 * power domains states to the desired target power states.
144 * - only the minimum set of functions gets copied to internal SRAM at boot
145 * and after wake-up from OFF mode, cf. omap_push_sram_idle. The function
146 * pointers in SDRAM or SRAM are called depending on the desired low power
148 * - when the OMAP wakes up it continues at different execution points
149 * depending on the low power mode (non-OFF vs OFF modes),
150 * cf. 'Resume path for xxx mode' comments.
153 ENTRY(omap34xx_cpu_suspend)
154 stmfd sp!, {r4 - r11, lr} @ save registers on stack
157 * r0 contains information about saving context:
158 * 0 - No context lost
159 * 1 - Only L1 and logic lost
160 * 2 - Only L2 lost (Even L1 is retained we clean it along with L2)
161 * 3 - Both L1 and L2 lost and logic lost
165 * For OFF mode: save context and jump to WFI in SDRAM (omap3_do_wfi)
166 * For non-OFF modes: jump to the WFI code in SRAM (omap3_do_wfi_sram)
168 ldr r4, omap3_do_wfi_sram_addr
170 cmp r0, #0x0 @ If no context save required,
171 bxeq r5 @ jump to the WFI code in SRAM
174 /* Otherwise fall through to the save context code */
177 * jump out to kernel flush routine
178 * - reuse that code is better
179 * - it executes in a cached space so is faster than refetch per-block
180 * - should be faster and will change with kernel
181 * - 'might' have to copy address, load and jump to it
182 * Flush all data from the L1 data cache before disabling
190 * Clear the SCTLR.C bit to prevent further data cache
191 * allocation. Clearing SCTLR.C would make all the data accesses
192 * strongly ordered and would not hit the cache.
194 mrc p15, 0, r0, c1, c0, 0
195 bic r0, r0, #(1 << 2) @ Disable the C bit
196 mcr p15, 0, r0, c1, c0, 0
200 * Invalidate L1 data cache. Even though only invalidate is
201 * necessary exported flush API is used here. Doing clean
202 * on already clean cache would be almost NOP.
207 ENDPROC(omap34xx_cpu_suspend)
208 omap3_do_wfi_sram_addr:
209 .word omap3_do_wfi_sram
211 .word v7_flush_dcache_all
213 /* ===================================
214 * == WFI instruction => Enter idle ==
215 * ===================================
220 * Includes the resume path for non-OFF modes
222 * This code gets copied to internal SRAM and is accessible
223 * from both SDRAM and SRAM:
224 * - executed from SRAM for non-off modes (omap3_do_wfi_sram),
225 * - executed from SDRAM for OFF mode (omap3_do_wfi).
229 ldr r4, sdrc_power @ read the SDRC_POWER register
230 ldr r5, [r4] @ read the contents of SDRC_POWER
231 orr r5, r5, #0x40 @ enable self refresh on idle req
232 str r5, [r4] @ write back to SDRC_POWER register
234 /* Data memory barrier and Data sync barrier */
239 * ===================================
240 * == WFI instruction => Enter idle ==
241 * ===================================
243 wfi @ wait for interrupt
246 * ===================================
247 * == Resume path for non-OFF modes ==
248 * ===================================
262 * This function implements the erratum ID i581 WA:
263 * SDRC state restore before accessing the SDRAM
265 * Only used at return from non-OFF mode. For OFF
266 * mode the ROM code configures the SDRC and
267 * the DPLL before calling the restore code directly
271 /* Make sure SDRC accesses are ok */
274 /* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
275 ldr r4, cm_idlest_ckgen
281 ldr r4, cm_idlest1_core
286 /* allow DLL powerdown upon hw idle req */
293 /* Is dll in lock mode? */
294 ldr r4, sdrc_dlla_ctrl
297 bne exit_nonoff_modes @ Return if locked
298 /* wait till dll locks */
300 ldr r4, sdrc_dlla_status
301 /* Wait 20uS for lock */
310 b exit_nonoff_modes @ Return when locked
312 /* disable/reenable DLL if not locked */
314 ldr r4, sdrc_dlla_ctrl
317 bic r6, #(1<<3) @ disable dll
320 orr r6, r6, #(1<<3) @ enable dll
323 b wait_dll_lock_timed
326 /* Re-enable C-bit if needed */
327 mrc p15, 0, r0, c1, c0, 0
328 tst r0, #(1 << 2) @ Check C bit enabled?
329 orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
330 mcreq p15, 0, r0, c1, c0, 0
334 * ===================================
335 * == Exit point from non-OFF modes ==
336 * ===================================
338 ldmfd sp!, {r4 - r11, pc} @ restore regs and return
339 ENDPROC(omap3_do_wfi)
343 .word CM_IDLEST1_CORE_V
345 .word CM_IDLEST_CKGEN_V
347 .word SDRC_DLLA_STATUS_V
349 .word SDRC_DLLA_CTRL_V
350 ENTRY(omap3_do_wfi_sz)
351 .word . - omap3_do_wfi
355 * ==============================
356 * == Resume path for OFF mode ==
357 * ==============================
361 * The restore_* functions are called by the ROM code
362 * when back from WFI in OFF mode.
363 * Cf. the get_*restore_pointer functions.
365 * restore_es3: applies to 34xx >= ES3.0
366 * restore_3630: applies to 36xx
367 * restore: common code for 3xxx
369 * Note: when back from CORE and MPU OFF mode we are running
370 * from SDRAM, without MMU, without the caches and prediction.
371 * Also the SRAM content has been cleared.
373 ENTRY(omap3_restore_es3)
374 ldr r5, pm_prepwstst_core_p
377 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
378 bne omap3_restore @ Fall through to OMAP3 common code
381 ldr r2, es3_sdrc_fix_sz
384 ldmia r0!, {r3} @ val = *src
385 stmia r1!, {r3} @ *dst = val
386 subs r2, r2, #0x1 @ num_words--
390 b omap3_restore @ Fall through to OMAP3 common code
391 ENDPROC(omap3_restore_es3)
393 ENTRY(omap3_restore_3630)
394 ldr r1, pm_prepwstst_core_p
397 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
398 bne omap3_restore @ Fall through to OMAP3 common code
399 /* Disable RTA before giving control */
400 ldr r1, control_mem_rta
401 mov r2, #OMAP36XX_RTA_DISABLE
403 ENDPROC(omap3_restore_3630)
405 /* Fall through to common code for the remaining logic */
409 * Read the pwstctrl register to check the reason for mpu reset.
410 * This tells us what was lost.
412 ldr r1, pm_pwstctrl_mpu
415 cmp r2, #0x0 @ Check if target power state was OFF or RET
419 cmp r0, #0x1 @ should we disable L2 on 3630?
421 mrc p15, 0, r0, c1, c0, 1
422 bic r0, r0, #2 @ disable L2 cache
423 mcr p15, 0, r0, c1, c0, 1
430 adr r0, l2_inv_api_params_offset
432 add r3, r3, r0 @ r3 points to dummy parameters
433 mov r0, #40 @ set service ID for PPA
434 mov r12, r0 @ copy secure Service ID in r12
435 mov r1, #0 @ set task id for ROM code in r1
436 mov r2, #4 @ set some flags in r2, r6
438 dsb @ data write barrier
439 dmb @ data memory barrier
440 smc #1 @ call SMI monitor (smi #1)
441 /* Write to Aux control register to set some bits */
442 mov r0, #42 @ set service ID for PPA
443 mov r12, r0 @ copy secure Service ID in r12
444 mov r1, #0 @ set task id for ROM code in r1
445 mov r2, #4 @ set some flags in r2, r6
447 ldr r4, scratchpad_base
448 ldr r3, [r4, #0xBC] @ r3 points to parameters
449 dsb @ data write barrier
450 dmb @ data memory barrier
451 smc #1 @ call SMI monitor (smi #1)
453 #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
454 /* Restore L2 aux control register */
455 @ set service ID for PPA
456 mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
457 mov r12, r0 @ copy service ID in r12
458 mov r1, #0 @ set task ID for ROM code in r1
459 mov r2, #4 @ set some flags in r2, r6
461 ldr r4, scratchpad_base
463 adds r3, r3, #8 @ r3 points to parameters
464 dsb @ data write barrier
465 dmb @ data memory barrier
466 smc #1 @ call SMI monitor (smi #1)
471 l2_inv_api_params_offset:
472 .long l2_inv_api_params - .
474 /* Execute smi to invalidate L2 cache */
475 mov r12, #0x1 @ set up to invalidate L2
476 smc #0 @ Call SMI monitor (smieq)
477 /* Write to Aux control register to set some bits */
478 ldr r4, scratchpad_base
482 smc #0 @ Call SMI monitor (smieq)
483 ldr r4, scratchpad_base
487 smc #0 @ Call SMI monitor (smieq)
490 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
492 mrc p15, 0, r1, c1, c0, 1
493 orr r1, r1, #2 @ re-enable L2 cache
494 mcr p15, 0, r1, c1, c0, 1
497 /* Now branch to the common CPU resume function */
499 ENDPROC(omap3_restore)
507 .word PM_PREPWSTST_CORE_P
509 .word PM_PWSTCTRL_MPU_P
511 .word SCRATCHPAD_BASE_P
513 .word SRAM_BASE_P + 0x8000
517 .word CONTROL_MEM_RTA_CTRL
530 * This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0
531 * Copied to and run from SRAM in order to reconfigure the SDRC parameters.
536 ldr r4, sdrc_syscfg @ get config addr
537 ldr r5, [r4] @ get value
538 tst r5, #0x100 @ is part access blocked
540 biceq r5, r5, #0x100 @ clear bit if set
541 str r5, [r4] @ write back change
542 ldr r4, sdrc_mr_0 @ get config addr
543 ldr r5, [r4] @ get value
544 str r5, [r4] @ write back change
545 ldr r4, sdrc_emr2_0 @ get config addr
546 ldr r5, [r4] @ get value
547 str r5, [r4] @ write back change
548 ldr r4, sdrc_manual_0 @ get config addr
549 mov r5, #0x2 @ autorefresh command
550 str r5, [r4] @ kick off refreshes
551 ldr r4, sdrc_mr_1 @ get config addr
552 ldr r5, [r4] @ get value
553 str r5, [r4] @ write back change
554 ldr r4, sdrc_emr2_1 @ get config addr
555 ldr r5, [r4] @ get value
556 str r5, [r4] @ write back change
557 ldr r4, sdrc_manual_1 @ get config addr
558 mov r5, #0x2 @ autorefresh command
559 str r5, [r4] @ kick off refreshes
567 .word SDRC_SYSCONFIG_P
573 .word SDRC_MANUAL_0_P
579 .word SDRC_MANUAL_1_P
580 ENDPROC(es3_sdrc_fix)
581 ENTRY(es3_sdrc_fix_sz)
582 .word . - es3_sdrc_fix