2 * OMAP4 Power Management Routines
4 * Copyright (C) 2010-2011 Texas Instruments, Inc.
5 * Rajendra Nayak <rnayak@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <linux/suspend.h>
15 #include <linux/module.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/slab.h>
21 #include "clockdomain.h"
22 #include "powerdomain.h"
26 struct powerdomain *pwrdm;
30 u32 saved_logic_state;
32 struct list_head node;
35 static LIST_HEAD(pwrst_list);
38 static int omap4_pm_suspend(void)
40 struct power_state *pwrst;
42 u32 cpu_id = smp_processor_id();
44 /* Save current powerdomain state */
45 list_for_each_entry(pwrst, &pwrst_list, node) {
46 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
47 pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
50 /* Set targeted power domain states by suspend */
51 list_for_each_entry(pwrst, &pwrst_list, node) {
52 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
53 pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
57 * For MPUSS to hit power domain retention(CSWR or OSWR),
58 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
59 * since CPU power domain CSWR is not supported by hardware
60 * Only master CPU follows suspend path. All other CPUs follow
61 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
62 * domain CSWR is not supported by hardware.
63 * More details can be found in OMAP4430 TRM section 4.3.4.2.
65 omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
67 /* Restore next powerdomain state */
68 list_for_each_entry(pwrst, &pwrst_list, node) {
69 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
70 if (state > pwrst->next_state) {
71 pr_info("Powerdomain (%s) didn't enter "
73 pwrst->pwrdm->name, pwrst->next_state);
76 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
77 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
80 pr_crit("Could not enter target state in pm_suspend\n");
82 pr_info("Successfully put all powerdomains to target state\n");
86 #endif /* CONFIG_SUSPEND */
88 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
90 struct power_state *pwrst;
96 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
97 * through hotplug path and CPU0 explicitly programmed
98 * further down in the code path
100 if (!strncmp(pwrdm->name, "cpu", 3))
104 * FIXME: Remove this check when core retention is supported
105 * Only MPUSS power domain is added in the list.
107 if (strcmp(pwrdm->name, "mpu_pwrdm"))
110 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
114 pwrst->pwrdm = pwrdm;
115 pwrst->next_state = PWRDM_POWER_RET;
116 list_add(&pwrst->node, &pwrst_list);
118 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
122 * omap_default_idle - OMAP4 default ilde routine.'
124 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
125 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
126 * by secondary CPU with CONFIG_CPUIDLE.
128 static void omap_default_idle(void)
138 * omap4_pm_init - Init routine for OMAP4 PM
140 * Initializes all powerdomain and clockdomain target states
141 * and all PRCM settings.
143 static int __init omap4_pm_init(void)
146 struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
147 struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
149 if (!cpu_is_omap44xx())
152 if (omap_rev() == OMAP4430_REV_ES1_0) {
153 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
157 pr_err("Power Management for TI OMAP4.\n");
159 ret = pwrdm_for_each(pwrdms_setup, NULL);
161 pr_err("Failed to setup powerdomains\n");
166 * The dynamic dependency between MPUSS -> MEMIF and
167 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
168 * expected. The hardware recommendation is to enable static
169 * dependencies for these to avoid system lock ups or random crashes.
171 mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
172 emif_clkdm = clkdm_lookup("l3_emif_clkdm");
173 l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
174 l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
175 l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
176 ducati_clkdm = clkdm_lookup("ducati_clkdm");
177 if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
178 (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
181 ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
182 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
183 ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
184 ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
185 ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
186 ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
188 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
189 "wakeup dependency\n");
193 ret = omap4_mpuss_init();
195 pr_err("Failed to initialise OMAP4 MPUSS\n");
199 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
201 #ifdef CONFIG_SUSPEND
202 omap_pm_suspend = omap4_pm_suspend;
205 /* Overwrite the default cpu_do_idle() */
206 arm_pm_idle = omap_default_idle;
213 late_initcall(omap4_pm_init);