2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <trace/events/power.h>
33 #include <asm/suspend.h>
35 #include <plat/sram.h>
36 #include "clockdomain.h"
37 #include "powerdomain.h"
38 #include <plat/sdrc.h>
39 #include <plat/prcm.h>
40 #include <plat/gpmc.h>
44 #include "cm2xxx_3xxx.h"
45 #include "cm-regbits-34xx.h"
46 #include "prm-regbits-34xx.h"
48 #include "prm2xxx_3xxx.h"
54 static suspend_state_t suspend_state = PM_SUSPEND_ON;
57 /* pm34xx errata defined in pm.h */
61 struct powerdomain *pwrdm;
66 struct list_head node;
69 static LIST_HEAD(pwrst_list);
71 static int (*_omap_save_secure_sram)(u32 *addr);
72 void (*omap3_do_wfi_sram)(void);
74 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
75 static struct powerdomain *core_pwrdm, *per_pwrdm;
76 static struct powerdomain *cam_pwrdm;
78 static inline void omap3_per_save_context(void)
80 omap_gpio_save_context();
83 static inline void omap3_per_restore_context(void)
85 omap_gpio_restore_context();
88 static void omap3_enable_io_chain(void)
92 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
94 /* Do a readback to assure write has been done */
95 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
97 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
98 OMAP3430_ST_IO_CHAIN_MASK)) {
100 if (timeout > 1000) {
101 pr_err("Wake up daisy chain activation failed.\n");
104 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
109 static void omap3_disable_io_chain(void)
111 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
115 static void omap3_core_save_context(void)
117 omap3_ctrl_save_padconf();
120 * Force write last pad into memory, as this can fail in some
121 * cases according to errata 1.157, 1.185
123 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
124 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
126 /* Save the Interrupt controller context */
127 omap_intc_save_context();
128 /* Save the GPMC context */
129 omap3_gpmc_save_context();
130 /* Save the system control module context, padconf already save above*/
131 omap3_control_save_context();
132 omap_dma_global_context_save();
135 static void omap3_core_restore_context(void)
137 /* Restore the control module context, padconf restored by h/w */
138 omap3_control_restore_context();
139 /* Restore the GPMC context */
140 omap3_gpmc_restore_context();
141 /* Restore the interrupt controller context */
142 omap_intc_restore_context();
143 omap_dma_global_context_restore();
147 * FIXME: This function should be called before entering off-mode after
148 * OMAP3 secure services have been accessed. Currently it is only called
149 * once during boot sequence, but this works as we are not using secure
152 static void omap3_save_secure_ram_context(void)
155 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
157 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
159 * MPU next state must be set to POWER_ON temporarily,
160 * otherwise the WFI executed inside the ROM code
161 * will hang the system.
163 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
164 ret = _omap_save_secure_sram((u32 *)
165 __pa(omap3_secure_ram_storage));
166 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
167 /* Following is for error tracking, it should not happen */
169 printk(KERN_ERR "save_secure_sram() returns %08x\n",
178 * PRCM Interrupt Handler Helper Function
180 * The purpose of this function is to clear any wake-up events latched
181 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
182 * may occur whilst attempting to clear a PM_WKST_x register and thus
183 * set another bit in this register. A while loop is used to ensure
184 * that any peripheral wake-up events occurring while attempting to
185 * clear the PM_WKST_x are detected and cleared.
187 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
189 u32 wkst, fclk, iclk, clken;
190 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
191 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
192 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
193 u16 grpsel_off = (regs == 3) ?
194 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
197 wkst = omap2_prm_read_mod_reg(module, wkst_off);
198 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
199 wkst &= ~ignore_bits;
201 iclk = omap2_cm_read_mod_reg(module, iclk_off);
202 fclk = omap2_cm_read_mod_reg(module, fclk_off);
205 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
207 * For USBHOST, we don't know whether HOST1 or
208 * HOST2 woke us up, so enable both f-clocks
210 if (module == OMAP3430ES2_USBHOST_MOD)
211 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
212 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
213 omap2_prm_write_mod_reg(wkst, module, wkst_off);
214 wkst = omap2_prm_read_mod_reg(module, wkst_off);
215 wkst &= ~ignore_bits;
218 omap2_cm_write_mod_reg(iclk, module, iclk_off);
219 omap2_cm_write_mod_reg(fclk, module, fclk_off);
225 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
229 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
230 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
232 return c ? IRQ_HANDLED : IRQ_NONE;
235 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
240 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
241 * these are handled in a separate handler to avoid acking
242 * IO events before parsing in mux code
244 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
245 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
246 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
247 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
248 if (omap_rev() > OMAP3430_REV_ES1_0) {
249 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
250 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
253 return c ? IRQ_HANDLED : IRQ_NONE;
256 static void omap34xx_save_context(u32 *save)
260 /* Read Auxiliary Control Register */
261 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
265 /* Read L2 AUX ctrl register */
266 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
271 static int omap34xx_do_sram_idle(unsigned long save_state)
273 omap34xx_cpu_suspend(save_state);
277 void omap_sram_idle(void)
279 /* Variable to tell what needs to be saved and restored
280 * in omap_sram_idle*/
281 /* save_state = 0 => Nothing to save and restored */
282 /* save_state = 1 => Only L1 and logic lost */
283 /* save_state = 2 => Only L2 lost */
284 /* save_state = 3 => L1, L2 and logic lost */
286 int mpu_next_state = PWRDM_POWER_ON;
287 int per_next_state = PWRDM_POWER_ON;
288 int core_next_state = PWRDM_POWER_ON;
290 int core_prev_state, per_prev_state;
293 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
294 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
295 pwrdm_clear_all_prev_pwrst(core_pwrdm);
296 pwrdm_clear_all_prev_pwrst(per_pwrdm);
298 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
299 switch (mpu_next_state) {
301 case PWRDM_POWER_RET:
302 /* No need to save context */
305 case PWRDM_POWER_OFF:
310 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
315 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
316 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
318 /* Enable IO-PAD and IO-CHAIN wakeups */
319 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
320 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
321 if (omap3_has_io_wakeup() &&
322 (per_next_state < PWRDM_POWER_ON ||
323 core_next_state < PWRDM_POWER_ON)) {
324 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
325 if (omap3_has_io_chain_ctrl())
326 omap3_enable_io_chain();
329 pwrdm_pre_transition();
332 if (per_next_state < PWRDM_POWER_ON) {
333 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
334 omap2_gpio_prepare_for_idle(per_going_off);
335 if (per_next_state == PWRDM_POWER_OFF)
336 omap3_per_save_context();
340 if (core_next_state < PWRDM_POWER_ON) {
341 if (core_next_state == PWRDM_POWER_OFF) {
342 omap3_core_save_context();
343 omap3_cm_save_context();
347 omap3_intc_prepare_idle();
350 * On EMU/HS devices ROM code restores a SRDC value
351 * from scratchpad which has automatic self refresh on timeout
352 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
353 * Hence store/restore the SDRC_POWER register here.
355 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
356 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
357 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
358 core_next_state == PWRDM_POWER_OFF)
359 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
362 * omap3_arm_context is the location where some ARM context
363 * get saved. The rest is placed on the stack, and restored
364 * from there before resuming.
367 omap34xx_save_context(omap3_arm_context);
368 if (save_state == 1 || save_state == 3)
369 cpu_suspend(save_state, omap34xx_do_sram_idle);
371 omap34xx_do_sram_idle(save_state);
373 /* Restore normal SDRC POWER settings */
374 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
375 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
376 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
377 core_next_state == PWRDM_POWER_OFF)
378 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
381 if (core_next_state < PWRDM_POWER_ON) {
382 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
383 if (core_prev_state == PWRDM_POWER_OFF) {
384 omap3_core_restore_context();
385 omap3_cm_restore_context();
386 omap3_sram_restore_context();
387 omap2_sms_restore_context();
389 if (core_next_state == PWRDM_POWER_OFF)
390 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
392 OMAP3_PRM_VOLTCTRL_OFFSET);
394 omap3_intc_resume_idle();
396 pwrdm_post_transition();
399 if (per_next_state < PWRDM_POWER_ON) {
400 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
401 omap2_gpio_resume_after_idle();
402 if (per_prev_state == PWRDM_POWER_OFF)
403 omap3_per_restore_context();
406 /* Disable IO-PAD and IO-CHAIN wakeup */
407 if (omap3_has_io_wakeup() &&
408 (per_next_state < PWRDM_POWER_ON ||
409 core_next_state < PWRDM_POWER_ON)) {
410 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
412 if (omap3_has_io_chain_ctrl())
413 omap3_disable_io_chain();
416 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
419 static void omap3_pm_idle(void)
423 if (omap_irq_pending())
426 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
427 trace_cpu_idle(1, smp_processor_id());
431 trace_power_end(smp_processor_id());
432 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
438 #ifdef CONFIG_SUSPEND
439 static int omap3_pm_suspend(void)
441 struct power_state *pwrst;
444 /* Read current next_pwrsts */
445 list_for_each_entry(pwrst, &pwrst_list, node)
446 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
447 /* Set ones wanted by suspend */
448 list_for_each_entry(pwrst, &pwrst_list, node) {
449 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
451 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
455 omap3_intc_suspend();
460 /* Restore next_pwrsts */
461 list_for_each_entry(pwrst, &pwrst_list, node) {
462 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
463 if (state > pwrst->next_state) {
464 printk(KERN_INFO "Powerdomain (%s) didn't enter "
466 pwrst->pwrdm->name, pwrst->next_state);
469 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
472 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
474 printk(KERN_INFO "Successfully put all powerdomains "
475 "to target state\n");
480 static int omap3_pm_enter(suspend_state_t unused)
484 switch (suspend_state) {
485 case PM_SUSPEND_STANDBY:
487 ret = omap3_pm_suspend();
496 /* Hooks to enable / disable UART interrupts during suspend */
497 static int omap3_pm_begin(suspend_state_t state)
500 suspend_state = state;
501 omap_prcm_irq_prepare();
505 static void omap3_pm_end(void)
507 suspend_state = PM_SUSPEND_ON;
512 static void omap3_pm_finish(void)
514 omap_prcm_irq_complete();
517 static const struct platform_suspend_ops omap_pm_ops = {
518 .begin = omap3_pm_begin,
520 .enter = omap3_pm_enter,
521 .finish = omap3_pm_finish,
522 .valid = suspend_valid_only_mem,
524 #endif /* CONFIG_SUSPEND */
528 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
531 * In cases where IVA2 is activated by bootcode, it may prevent
532 * full-chip retention or off-mode because it is not idle. This
533 * function forces the IVA2 into idle state so it can go
534 * into retention/off and thus allow full-chip retention/off.
537 static void __init omap3_iva_idle(void)
539 /* ensure IVA2 clock is disabled */
540 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
542 /* if no clock activity, nothing else to do */
543 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
544 OMAP3430_CLKACTIVITY_IVA2_MASK))
548 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
549 OMAP3430_RST2_IVA2_MASK |
550 OMAP3430_RST3_IVA2_MASK,
551 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
553 /* Enable IVA2 clock */
554 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
555 OMAP3430_IVA2_MOD, CM_FCLKEN);
557 /* Set IVA2 boot mode to 'idle' */
558 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
559 OMAP343X_CONTROL_IVA2_BOOTMOD);
562 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
564 /* Disable IVA2 clock */
565 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
568 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
569 OMAP3430_RST2_IVA2_MASK |
570 OMAP3430_RST3_IVA2_MASK,
571 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
574 static void __init omap3_d2d_idle(void)
578 /* In a stand alone OMAP3430 where there is not a stacked
579 * modem for the D2D Idle Ack and D2D MStandby must be pulled
580 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
581 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
582 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
583 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
585 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
587 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
589 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
592 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
593 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
594 CORE_MOD, OMAP2_RM_RSTCTRL);
595 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
598 static void __init prcm_setup_regs(void)
600 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
601 OMAP3630_EN_UART4_MASK : 0;
602 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
603 OMAP3630_GRPSEL_UART4_MASK : 0;
605 /* XXX This should be handled by hwmod code or SCM init code */
606 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
609 * Enable control of expternal oscillator through
610 * sys_clkreq. In the long run clock framework should
613 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
614 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
616 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
618 /* setup wakup source */
619 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
620 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
622 /* No need to write EN_IO, that is always enabled */
623 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
624 OMAP3430_GRPSEL_GPT1_MASK |
625 OMAP3430_GRPSEL_GPT12_MASK,
626 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
628 /* Enable PM_WKEN to support DSS LPR */
629 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
630 OMAP3430_DSS_MOD, PM_WKEN);
632 /* Enable wakeups in PER */
633 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
634 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
635 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
636 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
637 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
638 OMAP3430_EN_MCBSP4_MASK,
639 OMAP3430_PER_MOD, PM_WKEN);
640 /* and allow them to wake up MPU */
641 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
642 OMAP3430_GRPSEL_GPIO2_MASK |
643 OMAP3430_GRPSEL_GPIO3_MASK |
644 OMAP3430_GRPSEL_GPIO4_MASK |
645 OMAP3430_GRPSEL_GPIO5_MASK |
646 OMAP3430_GRPSEL_GPIO6_MASK |
647 OMAP3430_GRPSEL_UART3_MASK |
648 OMAP3430_GRPSEL_MCBSP2_MASK |
649 OMAP3430_GRPSEL_MCBSP3_MASK |
650 OMAP3430_GRPSEL_MCBSP4_MASK,
651 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
653 /* Don't attach IVA interrupts */
654 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
655 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
656 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
657 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
659 /* Clear any pending 'reset' flags */
660 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
661 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
662 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
663 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
664 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
665 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
666 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
668 /* Clear any pending PRCM interrupts */
669 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
675 void omap3_pm_off_mode_enable(int enable)
677 struct power_state *pwrst;
681 state = PWRDM_POWER_OFF;
683 state = PWRDM_POWER_RET;
685 list_for_each_entry(pwrst, &pwrst_list, node) {
686 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
687 pwrst->pwrdm == core_pwrdm &&
688 state == PWRDM_POWER_OFF) {
689 pwrst->next_state = PWRDM_POWER_RET;
690 pr_warn("%s: Core OFF disabled due to errata i583\n",
693 pwrst->next_state = state;
695 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
699 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
701 struct power_state *pwrst;
703 list_for_each_entry(pwrst, &pwrst_list, node) {
704 if (pwrst->pwrdm == pwrdm)
705 return pwrst->next_state;
710 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
712 struct power_state *pwrst;
714 list_for_each_entry(pwrst, &pwrst_list, node) {
715 if (pwrst->pwrdm == pwrdm) {
716 pwrst->next_state = state;
723 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
725 struct power_state *pwrst;
730 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
733 pwrst->pwrdm = pwrdm;
734 pwrst->next_state = PWRDM_POWER_RET;
735 list_add(&pwrst->node, &pwrst_list);
737 if (pwrdm_has_hdwr_sar(pwrdm))
738 pwrdm_enable_hdwr_sar(pwrdm);
740 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
744 * Enable hw supervised mode for all clockdomains if it's
745 * supported. Initiate sleep transition for other clockdomains, if
748 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
750 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
751 clkdm_allow_idle(clkdm);
752 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
753 atomic_read(&clkdm->usecount) == 0)
759 * Push functions to SRAM
761 * The minimum set of functions is pushed to SRAM for execution:
762 * - omap3_do_wfi for erratum i581 WA,
763 * - save_secure_ram_context for security extensions.
765 void omap_push_sram_idle(void)
767 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
769 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
770 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
771 save_secure_ram_context_sz);
774 static void __init pm_errata_configure(void)
776 if (cpu_is_omap3630()) {
777 pm34xx_errata |= PM_RTA_ERRATUM_i608;
778 /* Enable the l2 cache toggling in sleep logic */
779 enable_omap3630_toggle_l2_on_restore();
780 if (omap_rev() < OMAP3630_REV_ES1_2)
781 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
785 static int __init omap3_pm_init(void)
787 struct power_state *pwrst, *tmp;
788 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
791 if (!cpu_is_omap34xx())
794 if (!omap3_has_io_chain_ctrl())
795 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
797 pm_errata_configure();
799 /* XXX prcm_setup_regs needs to be before enabling hw
800 * supervised mode for powerdomains */
803 ret = request_irq(omap_prcm_event_to_irq("wkup"),
804 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
807 pr_err("pm: Failed to request pm_wkup irq\n");
811 /* IO interrupt is shared with mux code */
812 ret = request_irq(omap_prcm_event_to_irq("io"),
813 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
817 pr_err("pm: Failed to request pm_io irq\n");
821 ret = pwrdm_for_each(pwrdms_setup, NULL);
823 printk(KERN_ERR "Failed to setup powerdomains\n");
827 (void) clkdm_for_each(clkdms_setup, NULL);
829 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
830 if (mpu_pwrdm == NULL) {
831 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
835 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
836 per_pwrdm = pwrdm_lookup("per_pwrdm");
837 core_pwrdm = pwrdm_lookup("core_pwrdm");
838 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
840 neon_clkdm = clkdm_lookup("neon_clkdm");
841 mpu_clkdm = clkdm_lookup("mpu_clkdm");
842 per_clkdm = clkdm_lookup("per_clkdm");
843 core_clkdm = clkdm_lookup("core_clkdm");
845 #ifdef CONFIG_SUSPEND
846 suspend_set_ops(&omap_pm_ops);
847 #endif /* CONFIG_SUSPEND */
849 arm_pm_idle = omap3_pm_idle;
853 * RTA is disabled during initialization as per erratum i608
854 * it is safer to disable RTA by the bootloader, but we would like
855 * to be doubly sure here and prevent any mishaps.
857 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
858 omap3630_ctrl_disable_rta();
860 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
861 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
862 omap3_secure_ram_storage =
863 kmalloc(0x803F, GFP_KERNEL);
864 if (!omap3_secure_ram_storage)
865 printk(KERN_ERR "Memory allocation failed when"
866 "allocating for secure sram context\n");
871 omap_dma_global_context_save();
872 omap3_save_secure_ram_context();
873 omap_dma_global_context_restore();
879 omap3_save_scratchpad_contents();
883 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
884 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
885 list_del(&pwrst->node);
891 late_initcall(omap3_pm_init);