2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <trace/events/power.h>
33 #include <asm/suspend.h>
35 #include <plat/sram.h>
36 #include "clockdomain.h"
37 #include "powerdomain.h"
38 #include <plat/sdrc.h>
39 #include <plat/prcm.h>
40 #include <plat/gpmc.h>
44 #include "cm2xxx_3xxx.h"
45 #include "cm-regbits-34xx.h"
46 #include "prm-regbits-34xx.h"
48 #include "prm2xxx_3xxx.h"
53 /* pm34xx errata defined in pm.h */
57 struct powerdomain *pwrdm;
62 struct list_head node;
65 static LIST_HEAD(pwrst_list);
67 static int (*_omap_save_secure_sram)(u32 *addr);
68 void (*omap3_do_wfi_sram)(void);
70 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
71 static struct powerdomain *core_pwrdm, *per_pwrdm;
72 static struct powerdomain *cam_pwrdm;
74 static void omap3_enable_io_chain(void)
78 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
80 /* Do a readback to assure write has been done */
81 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
83 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
84 OMAP3430_ST_IO_CHAIN_MASK)) {
87 pr_err("Wake up daisy chain activation failed.\n");
90 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
95 static void omap3_disable_io_chain(void)
97 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
101 static void omap3_core_save_context(void)
103 omap3_ctrl_save_padconf();
106 * Force write last pad into memory, as this can fail in some
107 * cases according to errata 1.157, 1.185
109 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
110 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
112 /* Save the Interrupt controller context */
113 omap_intc_save_context();
114 /* Save the GPMC context */
115 omap3_gpmc_save_context();
116 /* Save the system control module context, padconf already save above*/
117 omap3_control_save_context();
118 omap_dma_global_context_save();
121 static void omap3_core_restore_context(void)
123 /* Restore the control module context, padconf restored by h/w */
124 omap3_control_restore_context();
125 /* Restore the GPMC context */
126 omap3_gpmc_restore_context();
127 /* Restore the interrupt controller context */
128 omap_intc_restore_context();
129 omap_dma_global_context_restore();
133 * FIXME: This function should be called before entering off-mode after
134 * OMAP3 secure services have been accessed. Currently it is only called
135 * once during boot sequence, but this works as we are not using secure
138 static void omap3_save_secure_ram_context(void)
141 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
143 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
145 * MPU next state must be set to POWER_ON temporarily,
146 * otherwise the WFI executed inside the ROM code
147 * will hang the system.
149 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
150 ret = _omap_save_secure_sram((u32 *)
151 __pa(omap3_secure_ram_storage));
152 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
153 /* Following is for error tracking, it should not happen */
155 printk(KERN_ERR "save_secure_sram() returns %08x\n",
164 * PRCM Interrupt Handler Helper Function
166 * The purpose of this function is to clear any wake-up events latched
167 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
168 * may occur whilst attempting to clear a PM_WKST_x register and thus
169 * set another bit in this register. A while loop is used to ensure
170 * that any peripheral wake-up events occurring while attempting to
171 * clear the PM_WKST_x are detected and cleared.
173 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
175 u32 wkst, fclk, iclk, clken;
176 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
177 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
178 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
179 u16 grpsel_off = (regs == 3) ?
180 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
183 wkst = omap2_prm_read_mod_reg(module, wkst_off);
184 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
185 wkst &= ~ignore_bits;
187 iclk = omap2_cm_read_mod_reg(module, iclk_off);
188 fclk = omap2_cm_read_mod_reg(module, fclk_off);
191 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
193 * For USBHOST, we don't know whether HOST1 or
194 * HOST2 woke us up, so enable both f-clocks
196 if (module == OMAP3430ES2_USBHOST_MOD)
197 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
198 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
199 omap2_prm_write_mod_reg(wkst, module, wkst_off);
200 wkst = omap2_prm_read_mod_reg(module, wkst_off);
201 wkst &= ~ignore_bits;
204 omap2_cm_write_mod_reg(iclk, module, iclk_off);
205 omap2_cm_write_mod_reg(fclk, module, fclk_off);
211 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
215 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
216 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
218 return c ? IRQ_HANDLED : IRQ_NONE;
221 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
226 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
227 * these are handled in a separate handler to avoid acking
228 * IO events before parsing in mux code
230 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
231 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
232 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
233 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
234 if (omap_rev() > OMAP3430_REV_ES1_0) {
235 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
236 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
239 return c ? IRQ_HANDLED : IRQ_NONE;
242 static void omap34xx_save_context(u32 *save)
246 /* Read Auxiliary Control Register */
247 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
251 /* Read L2 AUX ctrl register */
252 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
257 static int omap34xx_do_sram_idle(unsigned long save_state)
259 omap34xx_cpu_suspend(save_state);
263 void omap_sram_idle(void)
265 /* Variable to tell what needs to be saved and restored
266 * in omap_sram_idle*/
267 /* save_state = 0 => Nothing to save and restored */
268 /* save_state = 1 => Only L1 and logic lost */
269 /* save_state = 2 => Only L2 lost */
270 /* save_state = 3 => L1, L2 and logic lost */
272 int mpu_next_state = PWRDM_POWER_ON;
273 int per_next_state = PWRDM_POWER_ON;
274 int core_next_state = PWRDM_POWER_ON;
276 int core_prev_state, per_prev_state;
279 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
280 switch (mpu_next_state) {
282 case PWRDM_POWER_RET:
283 /* No need to save context */
286 case PWRDM_POWER_OFF:
291 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
296 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
297 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
299 /* Enable IO-PAD and IO-CHAIN wakeups */
300 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
301 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
302 if (omap3_has_io_wakeup() &&
303 (per_next_state < PWRDM_POWER_ON ||
304 core_next_state < PWRDM_POWER_ON)) {
305 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
306 if (omap3_has_io_chain_ctrl())
307 omap3_enable_io_chain();
310 pwrdm_pre_transition();
313 if (per_next_state < PWRDM_POWER_ON) {
314 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
315 omap2_gpio_prepare_for_idle(per_going_off);
319 if (core_next_state < PWRDM_POWER_ON) {
320 if (core_next_state == PWRDM_POWER_OFF) {
321 omap3_core_save_context();
322 omap3_cm_save_context();
326 omap3_intc_prepare_idle();
329 * On EMU/HS devices ROM code restores a SRDC value
330 * from scratchpad which has automatic self refresh on timeout
331 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
332 * Hence store/restore the SDRC_POWER register here.
334 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
335 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
336 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
337 core_next_state == PWRDM_POWER_OFF)
338 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
341 * omap3_arm_context is the location where some ARM context
342 * get saved. The rest is placed on the stack, and restored
343 * from there before resuming.
346 omap34xx_save_context(omap3_arm_context);
347 if (save_state == 1 || save_state == 3)
348 cpu_suspend(save_state, omap34xx_do_sram_idle);
350 omap34xx_do_sram_idle(save_state);
352 /* Restore normal SDRC POWER settings */
353 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
354 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
355 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
356 core_next_state == PWRDM_POWER_OFF)
357 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
360 if (core_next_state < PWRDM_POWER_ON) {
361 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
362 if (core_prev_state == PWRDM_POWER_OFF) {
363 omap3_core_restore_context();
364 omap3_cm_restore_context();
365 omap3_sram_restore_context();
366 omap2_sms_restore_context();
368 if (core_next_state == PWRDM_POWER_OFF)
369 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
371 OMAP3_PRM_VOLTCTRL_OFFSET);
373 omap3_intc_resume_idle();
375 pwrdm_post_transition();
378 if (per_next_state < PWRDM_POWER_ON) {
379 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
380 omap2_gpio_resume_after_idle();
383 /* Disable IO-PAD and IO-CHAIN wakeup */
384 if (omap3_has_io_wakeup() &&
385 (per_next_state < PWRDM_POWER_ON ||
386 core_next_state < PWRDM_POWER_ON)) {
387 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
389 if (omap3_has_io_chain_ctrl())
390 omap3_disable_io_chain();
393 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
396 static void omap3_pm_idle(void)
400 if (omap_irq_pending())
403 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
404 trace_cpu_idle(1, smp_processor_id());
408 trace_power_end(smp_processor_id());
409 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
415 #ifdef CONFIG_SUSPEND
416 static int omap3_pm_suspend(void)
418 struct power_state *pwrst;
421 /* Read current next_pwrsts */
422 list_for_each_entry(pwrst, &pwrst_list, node)
423 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
424 /* Set ones wanted by suspend */
425 list_for_each_entry(pwrst, &pwrst_list, node) {
426 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
428 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
432 omap3_intc_suspend();
437 /* Restore next_pwrsts */
438 list_for_each_entry(pwrst, &pwrst_list, node) {
439 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
440 if (state > pwrst->next_state) {
441 printk(KERN_INFO "Powerdomain (%s) didn't enter "
443 pwrst->pwrdm->name, pwrst->next_state);
446 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
449 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
451 printk(KERN_INFO "Successfully put all powerdomains "
452 "to target state\n");
457 #endif /* CONFIG_SUSPEND */
461 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
464 * In cases where IVA2 is activated by bootcode, it may prevent
465 * full-chip retention or off-mode because it is not idle. This
466 * function forces the IVA2 into idle state so it can go
467 * into retention/off and thus allow full-chip retention/off.
470 static void __init omap3_iva_idle(void)
472 /* ensure IVA2 clock is disabled */
473 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
475 /* if no clock activity, nothing else to do */
476 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
477 OMAP3430_CLKACTIVITY_IVA2_MASK))
481 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
482 OMAP3430_RST2_IVA2_MASK |
483 OMAP3430_RST3_IVA2_MASK,
484 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
486 /* Enable IVA2 clock */
487 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
488 OMAP3430_IVA2_MOD, CM_FCLKEN);
490 /* Set IVA2 boot mode to 'idle' */
491 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
492 OMAP343X_CONTROL_IVA2_BOOTMOD);
495 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
497 /* Disable IVA2 clock */
498 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
501 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
502 OMAP3430_RST2_IVA2_MASK |
503 OMAP3430_RST3_IVA2_MASK,
504 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
507 static void __init omap3_d2d_idle(void)
511 /* In a stand alone OMAP3430 where there is not a stacked
512 * modem for the D2D Idle Ack and D2D MStandby must be pulled
513 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
514 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
515 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
516 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
518 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
520 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
522 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
525 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
526 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
527 CORE_MOD, OMAP2_RM_RSTCTRL);
528 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
531 static void __init prcm_setup_regs(void)
533 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
534 OMAP3630_EN_UART4_MASK : 0;
535 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
536 OMAP3630_GRPSEL_UART4_MASK : 0;
538 /* XXX This should be handled by hwmod code or SCM init code */
539 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
542 * Enable control of expternal oscillator through
543 * sys_clkreq. In the long run clock framework should
546 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
547 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
549 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
551 /* setup wakup source */
552 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
553 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
555 /* No need to write EN_IO, that is always enabled */
556 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
557 OMAP3430_GRPSEL_GPT1_MASK |
558 OMAP3430_GRPSEL_GPT12_MASK,
559 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
561 /* Enable PM_WKEN to support DSS LPR */
562 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
563 OMAP3430_DSS_MOD, PM_WKEN);
565 /* Enable wakeups in PER */
566 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
567 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
568 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
569 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
570 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
571 OMAP3430_EN_MCBSP4_MASK,
572 OMAP3430_PER_MOD, PM_WKEN);
573 /* and allow them to wake up MPU */
574 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
575 OMAP3430_GRPSEL_GPIO2_MASK |
576 OMAP3430_GRPSEL_GPIO3_MASK |
577 OMAP3430_GRPSEL_GPIO4_MASK |
578 OMAP3430_GRPSEL_GPIO5_MASK |
579 OMAP3430_GRPSEL_GPIO6_MASK |
580 OMAP3430_GRPSEL_UART3_MASK |
581 OMAP3430_GRPSEL_MCBSP2_MASK |
582 OMAP3430_GRPSEL_MCBSP3_MASK |
583 OMAP3430_GRPSEL_MCBSP4_MASK,
584 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
586 /* Don't attach IVA interrupts */
587 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
588 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
589 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
590 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
592 /* Clear any pending 'reset' flags */
593 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
594 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
595 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
596 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
597 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
598 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
599 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
601 /* Clear any pending PRCM interrupts */
602 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
608 void omap3_pm_off_mode_enable(int enable)
610 struct power_state *pwrst;
614 state = PWRDM_POWER_OFF;
616 state = PWRDM_POWER_RET;
618 list_for_each_entry(pwrst, &pwrst_list, node) {
619 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
620 pwrst->pwrdm == core_pwrdm &&
621 state == PWRDM_POWER_OFF) {
622 pwrst->next_state = PWRDM_POWER_RET;
623 pr_warn("%s: Core OFF disabled due to errata i583\n",
626 pwrst->next_state = state;
628 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
632 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
634 struct power_state *pwrst;
636 list_for_each_entry(pwrst, &pwrst_list, node) {
637 if (pwrst->pwrdm == pwrdm)
638 return pwrst->next_state;
643 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
645 struct power_state *pwrst;
647 list_for_each_entry(pwrst, &pwrst_list, node) {
648 if (pwrst->pwrdm == pwrdm) {
649 pwrst->next_state = state;
656 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
658 struct power_state *pwrst;
663 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
666 pwrst->pwrdm = pwrdm;
667 pwrst->next_state = PWRDM_POWER_RET;
668 list_add(&pwrst->node, &pwrst_list);
670 if (pwrdm_has_hdwr_sar(pwrdm))
671 pwrdm_enable_hdwr_sar(pwrdm);
673 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
677 * Push functions to SRAM
679 * The minimum set of functions is pushed to SRAM for execution:
680 * - omap3_do_wfi for erratum i581 WA,
681 * - save_secure_ram_context for security extensions.
683 void omap_push_sram_idle(void)
685 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
687 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
688 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
689 save_secure_ram_context_sz);
692 static void __init pm_errata_configure(void)
694 if (cpu_is_omap3630()) {
695 pm34xx_errata |= PM_RTA_ERRATUM_i608;
696 /* Enable the l2 cache toggling in sleep logic */
697 enable_omap3630_toggle_l2_on_restore();
698 if (omap_rev() < OMAP3630_REV_ES1_2)
699 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
703 static int __init omap3_pm_init(void)
705 struct power_state *pwrst, *tmp;
706 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
709 if (!cpu_is_omap34xx())
712 if (!omap3_has_io_chain_ctrl())
713 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
715 pm_errata_configure();
717 /* XXX prcm_setup_regs needs to be before enabling hw
718 * supervised mode for powerdomains */
721 ret = request_irq(omap_prcm_event_to_irq("wkup"),
722 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
725 pr_err("pm: Failed to request pm_wkup irq\n");
729 /* IO interrupt is shared with mux code */
730 ret = request_irq(omap_prcm_event_to_irq("io"),
731 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
735 pr_err("pm: Failed to request pm_io irq\n");
739 ret = pwrdm_for_each(pwrdms_setup, NULL);
741 printk(KERN_ERR "Failed to setup powerdomains\n");
745 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
747 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
748 if (mpu_pwrdm == NULL) {
749 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
753 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
754 per_pwrdm = pwrdm_lookup("per_pwrdm");
755 core_pwrdm = pwrdm_lookup("core_pwrdm");
756 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
758 neon_clkdm = clkdm_lookup("neon_clkdm");
759 mpu_clkdm = clkdm_lookup("mpu_clkdm");
760 per_clkdm = clkdm_lookup("per_clkdm");
761 core_clkdm = clkdm_lookup("core_clkdm");
763 #ifdef CONFIG_SUSPEND
764 omap_pm_suspend = omap3_pm_suspend;
767 arm_pm_idle = omap3_pm_idle;
771 * RTA is disabled during initialization as per erratum i608
772 * it is safer to disable RTA by the bootloader, but we would like
773 * to be doubly sure here and prevent any mishaps.
775 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
776 omap3630_ctrl_disable_rta();
778 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
779 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
780 omap3_secure_ram_storage =
781 kmalloc(0x803F, GFP_KERNEL);
782 if (!omap3_secure_ram_storage)
783 printk(KERN_ERR "Memory allocation failed when"
784 "allocating for secure sram context\n");
789 omap_dma_global_context_save();
790 omap3_save_secure_ram_context();
791 omap_dma_global_context_restore();
797 omap3_save_scratchpad_contents();
801 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
802 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
803 list_del(&pwrst->node);
809 late_initcall(omap3_pm_init);