2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <linux/omap-dma.h>
32 #include <linux/platform_data/gpio-omap.h>
34 #include <trace/events/power.h>
36 #include <asm/fncpy.h>
37 #include <asm/suspend.h>
38 #include <asm/system_misc.h>
40 #include "clockdomain.h"
41 #include "powerdomain.h"
45 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
54 /* pm34xx errata defined in pm.h */
58 struct powerdomain *pwrdm;
63 struct list_head node;
66 static LIST_HEAD(pwrst_list);
68 static int (*_omap_save_secure_sram)(u32 *addr);
69 void (*omap3_do_wfi_sram)(void);
71 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
72 static struct powerdomain *core_pwrdm, *per_pwrdm;
74 static void omap3_core_save_context(void)
76 omap3_ctrl_save_padconf();
79 * Force write last pad into memory, as this can fail in some
80 * cases according to errata 1.157, 1.185
82 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
83 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
85 /* Save the Interrupt controller context */
86 omap_intc_save_context();
87 /* Save the GPMC context */
88 omap3_gpmc_save_context();
89 /* Save the system control module context, padconf already save above*/
90 omap3_control_save_context();
91 omap_dma_global_context_save();
94 static void omap3_core_restore_context(void)
96 /* Restore the control module context, padconf restored by h/w */
97 omap3_control_restore_context();
98 /* Restore the GPMC context */
99 omap3_gpmc_restore_context();
100 /* Restore the interrupt controller context */
101 omap_intc_restore_context();
102 omap_dma_global_context_restore();
106 * FIXME: This function should be called before entering off-mode after
107 * OMAP3 secure services have been accessed. Currently it is only called
108 * once during boot sequence, but this works as we are not using secure
111 static void omap3_save_secure_ram_context(void)
114 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
116 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
118 * MPU next state must be set to POWER_ON temporarily,
119 * otherwise the WFI executed inside the ROM code
120 * will hang the system.
122 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
123 ret = _omap_save_secure_sram((u32 *)(unsigned long)
124 __pa(omap3_secure_ram_storage));
125 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
126 /* Following is for error tracking, it should not happen */
128 pr_err("save_secure_sram() returns %08x\n", ret);
136 * PRCM Interrupt Handler Helper Function
138 * The purpose of this function is to clear any wake-up events latched
139 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
140 * may occur whilst attempting to clear a PM_WKST_x register and thus
141 * set another bit in this register. A while loop is used to ensure
142 * that any peripheral wake-up events occurring while attempting to
143 * clear the PM_WKST_x are detected and cleared.
145 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
147 u32 wkst, fclk, iclk, clken;
148 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
149 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
150 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
151 u16 grpsel_off = (regs == 3) ?
152 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
155 wkst = omap2_prm_read_mod_reg(module, wkst_off);
156 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
157 wkst &= ~ignore_bits;
159 iclk = omap2_cm_read_mod_reg(module, iclk_off);
160 fclk = omap2_cm_read_mod_reg(module, fclk_off);
163 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
165 * For USBHOST, we don't know whether HOST1 or
166 * HOST2 woke us up, so enable both f-clocks
168 if (module == OMAP3430ES2_USBHOST_MOD)
169 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
170 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
171 omap2_prm_write_mod_reg(wkst, module, wkst_off);
172 wkst = omap2_prm_read_mod_reg(module, wkst_off);
173 wkst &= ~ignore_bits;
176 omap2_cm_write_mod_reg(iclk, module, iclk_off);
177 omap2_cm_write_mod_reg(fclk, module, fclk_off);
183 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
187 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
188 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
190 return c ? IRQ_HANDLED : IRQ_NONE;
193 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
198 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
199 * these are handled in a separate handler to avoid acking
200 * IO events before parsing in mux code
202 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
203 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
204 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
205 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
206 if (omap_rev() > OMAP3430_REV_ES1_0) {
207 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
208 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
211 return c ? IRQ_HANDLED : IRQ_NONE;
214 static void omap34xx_save_context(u32 *save)
218 /* Read Auxiliary Control Register */
219 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
223 /* Read L2 AUX ctrl register */
224 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
229 static int omap34xx_do_sram_idle(unsigned long save_state)
231 omap34xx_cpu_suspend(save_state);
235 void omap_sram_idle(void)
237 /* Variable to tell what needs to be saved and restored
238 * in omap_sram_idle*/
239 /* save_state = 0 => Nothing to save and restored */
240 /* save_state = 1 => Only L1 and logic lost */
241 /* save_state = 2 => Only L2 lost */
242 /* save_state = 3 => L1, L2 and logic lost */
244 int mpu_next_state = PWRDM_POWER_ON;
245 int per_next_state = PWRDM_POWER_ON;
246 int core_next_state = PWRDM_POWER_ON;
251 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
252 switch (mpu_next_state) {
254 case PWRDM_POWER_RET:
255 /* No need to save context */
258 case PWRDM_POWER_OFF:
263 pr_err("Invalid mpu state in sram_idle\n");
268 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
269 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
271 /* Enable IO-PAD and IO-CHAIN wakeups */
272 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
273 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
275 pwrdm_pre_transition(NULL);
278 if (per_next_state < PWRDM_POWER_ON) {
279 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
280 omap2_gpio_prepare_for_idle(per_going_off);
284 if (core_next_state < PWRDM_POWER_ON) {
285 if (core_next_state == PWRDM_POWER_OFF) {
286 omap3_core_save_context();
287 omap3_cm_save_context();
291 omap3_intc_prepare_idle();
294 * On EMU/HS devices ROM code restores a SRDC value
295 * from scratchpad which has automatic self refresh on timeout
296 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
297 * Hence store/restore the SDRC_POWER register here.
299 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
300 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
301 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
302 core_next_state == PWRDM_POWER_OFF)
303 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
306 * omap3_arm_context is the location where some ARM context
307 * get saved. The rest is placed on the stack, and restored
308 * from there before resuming.
311 omap34xx_save_context(omap3_arm_context);
312 if (save_state == 1 || save_state == 3)
313 cpu_suspend(save_state, omap34xx_do_sram_idle);
315 omap34xx_do_sram_idle(save_state);
317 /* Restore normal SDRC POWER settings */
318 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
319 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
320 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
321 core_next_state == PWRDM_POWER_OFF)
322 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
325 if (core_next_state < PWRDM_POWER_ON) {
326 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
327 if (core_prev_state == PWRDM_POWER_OFF) {
328 omap3_core_restore_context();
329 omap3_cm_restore_context();
330 omap3_sram_restore_context();
331 omap2_sms_restore_context();
334 omap3_intc_resume_idle();
336 pwrdm_post_transition(NULL);
339 if (per_next_state < PWRDM_POWER_ON)
340 omap2_gpio_resume_after_idle();
343 static void omap3_pm_idle(void)
345 if (omap_irq_pending())
348 trace_cpu_idle(1, smp_processor_id());
352 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
355 #ifdef CONFIG_SUSPEND
356 static int omap3_pm_suspend(void)
358 struct power_state *pwrst;
361 /* Read current next_pwrsts */
362 list_for_each_entry(pwrst, &pwrst_list, node)
363 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
364 /* Set ones wanted by suspend */
365 list_for_each_entry(pwrst, &pwrst_list, node) {
366 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
368 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
372 omap3_intc_suspend();
377 /* Restore next_pwrsts */
378 list_for_each_entry(pwrst, &pwrst_list, node) {
379 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
380 if (state > pwrst->next_state) {
381 pr_info("Powerdomain (%s) didn't enter target state %d\n",
382 pwrst->pwrdm->name, pwrst->next_state);
385 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
388 pr_err("Could not enter target state in pm_suspend\n");
390 pr_info("Successfully put all powerdomains to target state\n");
395 #endif /* CONFIG_SUSPEND */
399 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
402 * In cases where IVA2 is activated by bootcode, it may prevent
403 * full-chip retention or off-mode because it is not idle. This
404 * function forces the IVA2 into idle state so it can go
405 * into retention/off and thus allow full-chip retention/off.
408 static void __init omap3_iva_idle(void)
410 /* ensure IVA2 clock is disabled */
411 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
413 /* if no clock activity, nothing else to do */
414 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
415 OMAP3430_CLKACTIVITY_IVA2_MASK))
419 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
420 OMAP3430_RST2_IVA2_MASK |
421 OMAP3430_RST3_IVA2_MASK,
422 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
424 /* Enable IVA2 clock */
425 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
426 OMAP3430_IVA2_MOD, CM_FCLKEN);
428 /* Set IVA2 boot mode to 'idle' */
429 omap3_ctrl_set_iva_bootmode_idle();
432 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
434 /* Disable IVA2 clock */
435 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
438 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
439 OMAP3430_RST2_IVA2_MASK |
440 OMAP3430_RST3_IVA2_MASK,
441 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
444 static void __init omap3_d2d_idle(void)
448 /* In a stand alone OMAP3430 where there is not a stacked
449 * modem for the D2D Idle Ack and D2D MStandby must be pulled
450 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
451 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
452 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
453 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
455 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
457 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
459 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
462 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
463 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
464 CORE_MOD, OMAP2_RM_RSTCTRL);
465 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
468 static void __init prcm_setup_regs(void)
470 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
471 OMAP3630_EN_UART4_MASK : 0;
472 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
473 OMAP3630_GRPSEL_UART4_MASK : 0;
475 /* XXX This should be handled by hwmod code or SCM init code */
476 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
479 * Enable control of expternal oscillator through
480 * sys_clkreq. In the long run clock framework should
483 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
484 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
486 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
488 /* setup wakup source */
489 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
490 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
492 /* No need to write EN_IO, that is always enabled */
493 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
494 OMAP3430_GRPSEL_GPT1_MASK |
495 OMAP3430_GRPSEL_GPT12_MASK,
496 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
498 /* Enable PM_WKEN to support DSS LPR */
499 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
500 OMAP3430_DSS_MOD, PM_WKEN);
502 /* Enable wakeups in PER */
503 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
504 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
505 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
506 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
507 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
508 OMAP3430_EN_MCBSP4_MASK,
509 OMAP3430_PER_MOD, PM_WKEN);
510 /* and allow them to wake up MPU */
511 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
512 OMAP3430_GRPSEL_GPIO2_MASK |
513 OMAP3430_GRPSEL_GPIO3_MASK |
514 OMAP3430_GRPSEL_GPIO4_MASK |
515 OMAP3430_GRPSEL_GPIO5_MASK |
516 OMAP3430_GRPSEL_GPIO6_MASK |
517 OMAP3430_GRPSEL_UART3_MASK |
518 OMAP3430_GRPSEL_MCBSP2_MASK |
519 OMAP3430_GRPSEL_MCBSP3_MASK |
520 OMAP3430_GRPSEL_MCBSP4_MASK,
521 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
523 /* Don't attach IVA interrupts */
524 if (omap3_has_iva()) {
525 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
526 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
527 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
528 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
529 OMAP3430_PM_IVAGRPSEL);
532 /* Clear any pending 'reset' flags */
533 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
534 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
535 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
536 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
537 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
538 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
539 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
541 /* Clear any pending PRCM interrupts */
542 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
545 * We need to idle iva2_pwrdm even on am3703 with no iva2.
552 void omap3_pm_off_mode_enable(int enable)
554 struct power_state *pwrst;
558 state = PWRDM_POWER_OFF;
560 state = PWRDM_POWER_RET;
562 list_for_each_entry(pwrst, &pwrst_list, node) {
563 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
564 pwrst->pwrdm == core_pwrdm &&
565 state == PWRDM_POWER_OFF) {
566 pwrst->next_state = PWRDM_POWER_RET;
567 pr_warn("%s: Core OFF disabled due to errata i583\n",
570 pwrst->next_state = state;
572 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
576 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
578 struct power_state *pwrst;
580 list_for_each_entry(pwrst, &pwrst_list, node) {
581 if (pwrst->pwrdm == pwrdm)
582 return pwrst->next_state;
587 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
589 struct power_state *pwrst;
591 list_for_each_entry(pwrst, &pwrst_list, node) {
592 if (pwrst->pwrdm == pwrdm) {
593 pwrst->next_state = state;
600 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
602 struct power_state *pwrst;
607 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
610 pwrst->pwrdm = pwrdm;
611 pwrst->next_state = PWRDM_POWER_RET;
612 list_add(&pwrst->node, &pwrst_list);
614 if (pwrdm_has_hdwr_sar(pwrdm))
615 pwrdm_enable_hdwr_sar(pwrdm);
617 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
621 * Push functions to SRAM
623 * The minimum set of functions is pushed to SRAM for execution:
624 * - omap3_do_wfi for erratum i581 WA,
625 * - save_secure_ram_context for security extensions.
627 void omap_push_sram_idle(void)
629 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
631 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
632 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
633 save_secure_ram_context_sz);
636 static void __init pm_errata_configure(void)
638 if (cpu_is_omap3630()) {
639 pm34xx_errata |= PM_RTA_ERRATUM_i608;
640 /* Enable the l2 cache toggling in sleep logic */
641 enable_omap3630_toggle_l2_on_restore();
642 if (omap_rev() < OMAP3630_REV_ES1_2)
643 pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
644 PM_PER_MEMORIES_ERRATUM_i582);
645 } else if (cpu_is_omap34xx()) {
646 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
650 int __init omap3_pm_init(void)
652 struct power_state *pwrst, *tmp;
653 struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
656 if (!omap3_has_io_chain_ctrl())
657 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
659 pm_errata_configure();
661 /* XXX prcm_setup_regs needs to be before enabling hw
662 * supervised mode for powerdomains */
665 ret = request_irq(omap_prcm_event_to_irq("wkup"),
666 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
669 pr_err("pm: Failed to request pm_wkup irq\n");
673 /* IO interrupt is shared with mux code */
674 ret = request_irq(omap_prcm_event_to_irq("io"),
675 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
677 enable_irq(omap_prcm_event_to_irq("io"));
680 pr_err("pm: Failed to request pm_io irq\n");
684 ret = pwrdm_for_each(pwrdms_setup, NULL);
686 pr_err("Failed to setup powerdomains\n");
690 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
692 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
693 if (mpu_pwrdm == NULL) {
694 pr_err("Failed to get mpu_pwrdm\n");
699 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
700 per_pwrdm = pwrdm_lookup("per_pwrdm");
701 core_pwrdm = pwrdm_lookup("core_pwrdm");
703 neon_clkdm = clkdm_lookup("neon_clkdm");
704 mpu_clkdm = clkdm_lookup("mpu_clkdm");
705 per_clkdm = clkdm_lookup("per_clkdm");
706 wkup_clkdm = clkdm_lookup("wkup_clkdm");
708 #ifdef CONFIG_SUSPEND
709 omap_pm_suspend = omap3_pm_suspend;
712 arm_pm_idle = omap3_pm_idle;
716 * RTA is disabled during initialization as per erratum i608
717 * it is safer to disable RTA by the bootloader, but we would like
718 * to be doubly sure here and prevent any mishaps.
720 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
721 omap3630_ctrl_disable_rta();
724 * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
725 * not correctly reset when the PER powerdomain comes back
726 * from OFF or OSWR when the CORE powerdomain is kept active.
727 * See OMAP36xx Erratum i582 "PER Domain reset issue after
728 * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
729 * complete workaround. The kernel must also prevent the PER
730 * powerdomain from going to OSWR/OFF while the CORE
731 * powerdomain is not going to OSWR/OFF. And if PER last
732 * power state was off while CORE last power state was ON, the
733 * UART3/4 and McBSP2/3 SIDETONE devices need to run a
734 * self-test using their loopback tests; if that fails, those
735 * devices are unusable until the PER/CORE can complete a transition
736 * from ON to OSWR/OFF and then back to ON.
738 * XXX Technically this workaround is only needed if off-mode
739 * or OSWR is enabled.
741 if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
742 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
744 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
745 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
746 omap3_secure_ram_storage =
747 kmalloc(0x803F, GFP_KERNEL);
748 if (!omap3_secure_ram_storage)
749 pr_err("Memory allocation failed when allocating for secure sram context\n");
753 omap_dma_global_context_save();
754 omap3_save_secure_ram_context();
755 omap_dma_global_context_restore();
760 omap3_save_scratchpad_contents();
764 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
765 list_del(&pwrst->node);
768 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
770 free_irq(omap_prcm_event_to_irq("wkup"), NULL);