arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/suspend.h>
  35
  36 #include <plat/sram.h>
  37 #include "clockdomain.h"
  38 #include "powerdomain.h"
  39 #include <plat/serial.h>
  40 #include <plat/sdrc.h>
  41 #include <plat/prcm.h>
  42 #include <plat/gpmc.h>
  43 #include <plat/dma.h>
  44
  45 #include "common.h"
  46 #include "cm2xxx_3xxx.h"
  47 #include "cm-regbits-34xx.h"
  48 #include "prm-regbits-34xx.h"
  49
  50 #include "prm2xxx_3xxx.h"
  51 #include "pm.h"
  52 #include "sdrc.h"
  53 #include "control.h"
  54
  55 #ifdef CONFIG_SUSPEND
  56 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  57 static inline bool is_suspending(void)
  58 {
  59         return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
  60 }
  61 #else
  62 static inline bool is_suspending(void)
  63 {
  64         return false;
  65 }
  66 #endif
  67
  68 /* pm34xx errata defined in pm.h */
  69 u16 pm34xx_errata;
  70
  71 struct power_state {
  72         struct powerdomain *pwrdm;
  73         u32 next_state;
  74 #ifdef CONFIG_SUSPEND
  75         u32 saved_state;
  76 #endif
  77         struct list_head node;
  78 };
  79
  80 static LIST_HEAD(pwrst_list);
  81
  82 static int (*_omap_save_secure_sram)(u32 *addr);
  83 void (*omap3_do_wfi_sram)(void);
  84
  85 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  86 static struct powerdomain *core_pwrdm, *per_pwrdm;
  87 static struct powerdomain *cam_pwrdm;
  88
  89 static inline void omap3_per_save_context(void)
  90 {
  91         omap_gpio_save_context();
  92 }
  93
  94 static inline void omap3_per_restore_context(void)
  95 {
  96         omap_gpio_restore_context();
  97 }
  98
  99 static void omap3_enable_io_chain(void)
 100 {
 101         int timeout = 0;
 102
 103         omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 104                                    PM_WKEN);
 105         /* Do a readback to assure write has been done */
 106         omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 107
 108         while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 109                  OMAP3430_ST_IO_CHAIN_MASK)) {
 110                 timeout++;
 111                 if (timeout > 1000) {
 112                         pr_err("Wake up daisy chain activation failed.\n");
 113                         return;
 114                 }
 115                 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 116                                            WKUP_MOD, PM_WKEN);
 117         }
 118 }
 119
 120 static void omap3_disable_io_chain(void)
 121 {
 122         omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 123                                      PM_WKEN);
 124 }
 125
 126 static void omap3_core_save_context(void)
 127 {
 128         omap3_ctrl_save_padconf();
 129
 130         /*
 131          * Force write last pad into memory, as this can fail in some
 132          * cases according to errata 1.157, 1.185
 133          */
 134         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 135                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 136
 137         /* Save the Interrupt controller context */
 138         omap_intc_save_context();
 139         /* Save the GPMC context */
 140         omap3_gpmc_save_context();
 141         /* Save the system control module context, padconf already save above*/
 142         omap3_control_save_context();
 143         omap_dma_global_context_save();
 144 }
 145
 146 static void omap3_core_restore_context(void)
 147 {
 148         /* Restore the control module context, padconf restored by h/w */
 149         omap3_control_restore_context();
 150         /* Restore the GPMC context */
 151         omap3_gpmc_restore_context();
 152         /* Restore the interrupt controller context */
 153         omap_intc_restore_context();
 154         omap_dma_global_context_restore();
 155 }
 156
 157 /*
 158  * FIXME: This function should be called before entering off-mode after
 159  * OMAP3 secure services have been accessed. Currently it is only called
 160  * once during boot sequence, but this works as we are not using secure
 161  * services.
 162  */
 163 static void omap3_save_secure_ram_context(void)
 164 {
 165         u32 ret;
 166         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 167
 168         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 169                 /*
 170                  * MPU next state must be set to POWER_ON temporarily,
 171                  * otherwise the WFI executed inside the ROM code
 172                  * will hang the system.
 173                  */
 174                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 175                 ret = _omap_save_secure_sram((u32 *)
 176                                 __pa(omap3_secure_ram_storage));
 177                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 178                 /* Following is for error tracking, it should not happen */
 179                 if (ret) {
 180                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 181                                 ret);
 182                         while (1)
 183                                 ;
 184                 }
 185         }
 186 }
 187
 188 /*
 189  * PRCM Interrupt Handler Helper Function
 190  *
 191  * The purpose of this function is to clear any wake-up events latched
 192  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 193  * may occur whilst attempting to clear a PM_WKST_x register and thus
 194  * set another bit in this register. A while loop is used to ensure
 195  * that any peripheral wake-up events occurring while attempting to
 196  * clear the PM_WKST_x are detected and cleared.
 197  */
 198 static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 199 {
 200         u32 wkst, fclk, iclk, clken;
 201         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 202         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 203         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 204         u16 grpsel_off = (regs == 3) ?
 205                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 206         int c = 0;
 207
 208         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 209         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 210         wkst &= ~ignore_bits;
 211         if (wkst) {
 212                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 213                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 214                 while (wkst) {
 215                         clken = wkst;
 216                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 217                         /*
 218                          * For USBHOST, we don't know whether HOST1 or
 219                          * HOST2 woke us up, so enable both f-clocks
 220                          */
 221                         if (module == OMAP3430ES2_USBHOST_MOD)
 222                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 223                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 224                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 225                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 226                         wkst &= ~ignore_bits;
 227                         c++;
 228                 }
 229                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 230                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 231         }
 232
 233         return c;
 234 }
 235
 236 static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 237 {
 238         int c;
 239
 240         c = prcm_clear_mod_irqs(WKUP_MOD, 1,
 241                 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
 242
 243         return c ? IRQ_HANDLED : IRQ_NONE;
 244 }
 245
 246 static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
 247 {
 248         int c;
 249
 250         /*
 251          * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
 252          * these are handled in a separate handler to avoid acking
 253          * IO events before parsing in mux code
 254          */
 255         c = prcm_clear_mod_irqs(WKUP_MOD, 1,
 256                 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
 257         c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
 258         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
 259         if (omap_rev() > OMAP3430_REV_ES1_0) {
 260                 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
 261                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
 262         }
 263
 264         return c ? IRQ_HANDLED : IRQ_NONE;
 265 }
 266
 267 static void omap34xx_save_context(u32 *save)
 268 {
 269         u32 val;
 270
 271         /* Read Auxiliary Control Register */
 272         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 273         *save++ = 1;
 274         *save++ = val;
 275
 276         /* Read L2 AUX ctrl register */
 277         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 278         *save++ = 1;
 279         *save++ = val;
 280 }
 281
 282 static int omap34xx_do_sram_idle(unsigned long save_state)
 283 {
 284         omap34xx_cpu_suspend(save_state);
 285         return 0;
 286 }
 287
 288 void omap_sram_idle(void)
 289 {
 290         /* Variable to tell what needs to be saved and restored
 291          * in omap_sram_idle*/
 292         /* save_state = 0 => Nothing to save and restored */
 293         /* save_state = 1 => Only L1 and logic lost */
 294         /* save_state = 2 => Only L2 lost */
 295         /* save_state = 3 => L1, L2 and logic lost */
 296         int save_state = 0;
 297         int mpu_next_state = PWRDM_POWER_ON;
 298         int per_next_state = PWRDM_POWER_ON;
 299         int core_next_state = PWRDM_POWER_ON;
 300         int per_going_off;
 301         int core_prev_state, per_prev_state;
 302         u32 sdrc_pwr = 0;
 303
 304         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 305         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 306         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 307         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 308
 309         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 310         switch (mpu_next_state) {
 311         case PWRDM_POWER_ON:
 312         case PWRDM_POWER_RET:
 313                 /* No need to save context */
 314                 save_state = 0;
 315                 break;
 316         case PWRDM_POWER_OFF:
 317                 save_state = 3;
 318                 break;
 319         default:
 320                 /* Invalid state */
 321                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 322                 return;
 323         }
 324
 325         /* NEON control */
 326         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 327                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 328
 329         /* Enable IO-PAD and IO-CHAIN wakeups */
 330         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 331         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 332         if (omap3_has_io_wakeup() &&
 333             (per_next_state < PWRDM_POWER_ON ||
 334              core_next_state < PWRDM_POWER_ON)) {
 335                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 336                 if (omap3_has_io_chain_ctrl())
 337                         omap3_enable_io_chain();
 338         }
 339
 340         /* Block console output in case it is on one of the OMAP UARTs */
 341         if (!is_suspending())
 342                 if (per_next_state < PWRDM_POWER_ON ||
 343                     core_next_state < PWRDM_POWER_ON)
 344                         if (!console_trylock())
 345                                 goto console_still_active;
 346
 347         pwrdm_pre_transition();
 348
 349         /* PER */
 350         if (per_next_state < PWRDM_POWER_ON) {
 351                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 352                 omap_uart_prepare_idle(2);
 353                 omap_uart_prepare_idle(3);
 354                 omap2_gpio_prepare_for_idle(per_going_off);
 355                 if (per_next_state == PWRDM_POWER_OFF)
 356                                 omap3_per_save_context();
 357         }
 358
 359         /* CORE */
 360         if (core_next_state < PWRDM_POWER_ON) {
 361                 omap_uart_prepare_idle(0);
 362                 omap_uart_prepare_idle(1);
 363                 if (core_next_state == PWRDM_POWER_OFF) {
 364                         omap3_core_save_context();
 365                         omap3_cm_save_context();
 366                 }
 367         }
 368
 369         omap3_intc_prepare_idle();
 370
 371         /*
 372          * On EMU/HS devices ROM code restores a SRDC value
 373          * from scratchpad which has automatic self refresh on timeout
 374          * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 375          * Hence store/restore the SDRC_POWER register here.
 376          */
 377         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 378             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 379              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 380             core_next_state == PWRDM_POWER_OFF)
 381                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 382
 383         /*
 384          * omap3_arm_context is the location where some ARM context
 385          * get saved. The rest is placed on the stack, and restored
 386          * from there before resuming.
 387          */
 388         if (save_state)
 389                 omap34xx_save_context(omap3_arm_context);
 390         if (save_state == 1 || save_state == 3)
 391                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 392         else
 393                 omap34xx_do_sram_idle(save_state);
 394
 395         /* Restore normal SDRC POWER settings */
 396         if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
 397             (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
 398              omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
 399             core_next_state == PWRDM_POWER_OFF)
 400                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 401
 402         /* CORE */
 403         if (core_next_state < PWRDM_POWER_ON) {
 404                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 405                 if (core_prev_state == PWRDM_POWER_OFF) {
 406                         omap3_core_restore_context();
 407                         omap3_cm_restore_context();
 408                         omap3_sram_restore_context();
 409                         omap2_sms_restore_context();
 410                 }
 411                 omap_uart_resume_idle(0);
 412                 omap_uart_resume_idle(1);
 413                 if (core_next_state == PWRDM_POWER_OFF)
 414                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 415                                                OMAP3430_GR_MOD,
 416                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 417         }
 418         omap3_intc_resume_idle();
 419
 420         pwrdm_post_transition();
 421
 422         /* PER */
 423         if (per_next_state < PWRDM_POWER_ON) {
 424                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 425                 omap2_gpio_resume_after_idle();
 426                 if (per_prev_state == PWRDM_POWER_OFF)
 427                         omap3_per_restore_context();
 428                 omap_uart_resume_idle(2);
 429                 omap_uart_resume_idle(3);
 430         }
 431
 432         if (!is_suspending())
 433                 console_unlock();
 434
 435 console_still_active:
 436         /* Disable IO-PAD and IO-CHAIN wakeup */
 437         if (omap3_has_io_wakeup() &&
 438             (per_next_state < PWRDM_POWER_ON ||
 439              core_next_state < PWRDM_POWER_ON)) {
 440                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 441                                              PM_WKEN);
 442                 if (omap3_has_io_chain_ctrl())
 443                         omap3_disable_io_chain();
 444         }
 445
 446         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 447 }
 448
 449 int omap3_can_sleep(void)
 450 {
 451         if (!omap_uart_can_sleep())
 452                 return 0;
 453         return 1;
 454 }
 455
 456 static void omap3_pm_idle(void)
 457 {
 458         local_irq_disable();
 459         local_fiq_disable();
 460
 461         if (!omap3_can_sleep())
 462                 goto out;
 463
 464         if (omap_irq_pending() || need_resched())
 465                 goto out;
 466
 467         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 468         trace_cpu_idle(1, smp_processor_id());
 469
 470         omap_sram_idle();
 471
 472         trace_power_end(smp_processor_id());
 473         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 474
 475 out:
 476         local_fiq_enable();
 477         local_irq_enable();
 478 }
 479
 480 #ifdef CONFIG_SUSPEND
 481 static int omap3_pm_suspend(void)
 482 {
 483         struct power_state *pwrst;
 484         int state, ret = 0;
 485
 486         /* Read current next_pwrsts */
 487         list_for_each_entry(pwrst, &pwrst_list, node)
 488                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 489         /* Set ones wanted by suspend */
 490         list_for_each_entry(pwrst, &pwrst_list, node) {
 491                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 492                         goto restore;
 493                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 494                         goto restore;
 495         }
 496
 497         omap_uart_prepare_suspend();
 498         omap3_intc_suspend();
 499
 500         omap_sram_idle();
 501
 502 restore:
 503         /* Restore next_pwrsts */
 504         list_for_each_entry(pwrst, &pwrst_list, node) {
 505                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 506                 if (state > pwrst->next_state) {
 507                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 508                                "target state %d\n",
 509                                pwrst->pwrdm->name, pwrst->next_state);
 510                         ret = -1;
 511                 }
 512                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 513         }
 514         if (ret)
 515                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 516         else
 517                 printk(KERN_INFO "Successfully put all powerdomains "
 518                        "to target state\n");
 519
 520         return ret;
 521 }
 522
 523 static int omap3_pm_enter(suspend_state_t unused)
 524 {
 525         int ret = 0;
 526
 527         switch (suspend_state) {
 528         case PM_SUSPEND_STANDBY:
 529         case PM_SUSPEND_MEM:
 530                 ret = omap3_pm_suspend();
 531                 break;
 532         default:
 533                 ret = -EINVAL;
 534         }
 535
 536         return ret;
 537 }
 538
 539 /* Hooks to enable / disable UART interrupts during suspend */
 540 static int omap3_pm_begin(suspend_state_t state)
 541 {
 542         disable_hlt();
 543         suspend_state = state;
 544         omap_uart_enable_irqs(0);
 545         omap_prcm_irq_prepare();
 546         return 0;
 547 }
 548
 549 static void omap3_pm_end(void)
 550 {
 551         suspend_state = PM_SUSPEND_ON;
 552         omap_uart_enable_irqs(1);
 553         enable_hlt();
 554         return;
 555 }
 556
 557 static void omap3_pm_finish(void)
 558 {
 559         omap_prcm_irq_complete();
 560 }
 561
 562 static const struct platform_suspend_ops omap_pm_ops = {
 563         .begin          = omap3_pm_begin,
 564         .end            = omap3_pm_end,
 565         .enter          = omap3_pm_enter,
 566         .finish         = omap3_pm_finish,
 567         .valid          = suspend_valid_only_mem,
 568 };
 569 #endif /* CONFIG_SUSPEND */
 570
 571
 572 /**
 573  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 574  *                   retention
 575  *
 576  * In cases where IVA2 is activated by bootcode, it may prevent
 577  * full-chip retention or off-mode because it is not idle.  This
 578  * function forces the IVA2 into idle state so it can go
 579  * into retention/off and thus allow full-chip retention/off.
 580  *
 581  **/
 582 static void __init omap3_iva_idle(void)
 583 {
 584         /* ensure IVA2 clock is disabled */
 585         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 586
 587         /* if no clock activity, nothing else to do */
 588         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 589               OMAP3430_CLKACTIVITY_IVA2_MASK))
 590                 return;
 591
 592         /* Reset IVA2 */
 593         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 594                           OMAP3430_RST2_IVA2_MASK |
 595                           OMAP3430_RST3_IVA2_MASK,
 596                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 597
 598         /* Enable IVA2 clock */
 599         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 600                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 601
 602         /* Set IVA2 boot mode to 'idle' */
 603         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 604                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 605
 606         /* Un-reset IVA2 */
 607         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 608
 609         /* Disable IVA2 clock */
 610         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 611
 612         /* Reset IVA2 */
 613         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 614                           OMAP3430_RST2_IVA2_MASK |
 615                           OMAP3430_RST3_IVA2_MASK,
 616                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 617 }
 618
 619 static void __init omap3_d2d_idle(void)
 620 {
 621         u16 mask, padconf;
 622
 623         /* In a stand alone OMAP3430 where there is not a stacked
 624          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 625          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 626          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 627         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 628         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 629         padconf |= mask;
 630         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 631
 632         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 633         padconf |= mask;
 634         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 635
 636         /* reset modem */
 637         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 638                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 639                           CORE_MOD, OMAP2_RM_RSTCTRL);
 640         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 641 }
 642
 643 static void __init prcm_setup_regs(void)
 644 {
 645         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 646                                         OMAP3630_EN_UART4_MASK : 0;
 647         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 648                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 649
 650         /* XXX This should be handled by hwmod code or SCM init code */
 651         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 652
 653         /*
 654          * Enable control of expternal oscillator through
 655          * sys_clkreq. In the long run clock framework should
 656          * take care of this.
 657          */
 658         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 659                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 660                              OMAP3430_GR_MOD,
 661                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 662
 663         /* setup wakup source */
 664         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 665                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 666                           WKUP_MOD, PM_WKEN);
 667         /* No need to write EN_IO, that is always enabled */
 668         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 669                           OMAP3430_GRPSEL_GPT1_MASK |
 670                           OMAP3430_GRPSEL_GPT12_MASK,
 671                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 672
 673         /* Enable PM_WKEN to support DSS LPR */
 674         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 675                                 OMAP3430_DSS_MOD, PM_WKEN);
 676
 677         /* Enable wakeups in PER */
 678         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 679                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 680                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 681                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 682                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 683                           OMAP3430_EN_MCBSP4_MASK,
 684                           OMAP3430_PER_MOD, PM_WKEN);
 685         /* and allow them to wake up MPU */
 686         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 687                           OMAP3430_GRPSEL_GPIO2_MASK |
 688                           OMAP3430_GRPSEL_GPIO3_MASK |
 689                           OMAP3430_GRPSEL_GPIO4_MASK |
 690                           OMAP3430_GRPSEL_GPIO5_MASK |
 691                           OMAP3430_GRPSEL_GPIO6_MASK |
 692                           OMAP3430_GRPSEL_UART3_MASK |
 693                           OMAP3430_GRPSEL_MCBSP2_MASK |
 694                           OMAP3430_GRPSEL_MCBSP3_MASK |
 695                           OMAP3430_GRPSEL_MCBSP4_MASK,
 696                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 697
 698         /* Don't attach IVA interrupts */
 699         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 700         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 701         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 702         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 703
 704         /* Clear any pending 'reset' flags */
 705         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 706         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 707         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 708         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 709         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 710         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 711         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 712
 713         /* Clear any pending PRCM interrupts */
 714         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 715
 716         omap3_iva_idle();
 717         omap3_d2d_idle();
 718 }
 719
 720 void omap3_pm_off_mode_enable(int enable)
 721 {
 722         struct power_state *pwrst;
 723         u32 state;
 724
 725         if (enable)
 726                 state = PWRDM_POWER_OFF;
 727         else
 728                 state = PWRDM_POWER_RET;
 729
 730         list_for_each_entry(pwrst, &pwrst_list, node) {
 731                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 732                                 pwrst->pwrdm == core_pwrdm &&
 733                                 state == PWRDM_POWER_OFF) {
 734                         pwrst->next_state = PWRDM_POWER_RET;
 735                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 736                                 __func__);
 737                 } else {
 738                         pwrst->next_state = state;
 739                 }
 740                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 741         }
 742 }
 743
 744 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 745 {
 746         struct power_state *pwrst;
 747
 748         list_for_each_entry(pwrst, &pwrst_list, node) {
 749                 if (pwrst->pwrdm == pwrdm)
 750                         return pwrst->next_state;
 751         }
 752         return -EINVAL;
 753 }
 754
 755 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 756 {
 757         struct power_state *pwrst;
 758
 759         list_for_each_entry(pwrst, &pwrst_list, node) {
 760                 if (pwrst->pwrdm == pwrdm) {
 761                         pwrst->next_state = state;
 762                         return 0;
 763                 }
 764         }
 765         return -EINVAL;
 766 }
 767
 768 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 769 {
 770         struct power_state *pwrst;
 771
 772         if (!pwrdm->pwrsts)
 773                 return 0;
 774
 775         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 776         if (!pwrst)
 777                 return -ENOMEM;
 778         pwrst->pwrdm = pwrdm;
 779         pwrst->next_state = PWRDM_POWER_RET;
 780         list_add(&pwrst->node, &pwrst_list);
 781
 782         if (pwrdm_has_hdwr_sar(pwrdm))
 783                 pwrdm_enable_hdwr_sar(pwrdm);
 784
 785         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 786 }
 787
 788 /*
 789  * Enable hw supervised mode for all clockdomains if it's
 790  * supported. Initiate sleep transition for other clockdomains, if
 791  * they are not used
 792  */
 793 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 794 {
 795         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 796                 clkdm_allow_idle(clkdm);
 797         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 798                  atomic_read(&clkdm->usecount) == 0)
 799                 clkdm_sleep(clkdm);
 800         return 0;
 801 }
 802
 803 /*
 804  * Push functions to SRAM
 805  *
 806  * The minimum set of functions is pushed to SRAM for execution:
 807  * - omap3_do_wfi for erratum i581 WA,
 808  * - save_secure_ram_context for security extensions.
 809  */
 810 void omap_push_sram_idle(void)
 811 {
 812         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 813
 814         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 815                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 816                                 save_secure_ram_context_sz);
 817 }
 818
 819 static void __init pm_errata_configure(void)
 820 {
 821         if (cpu_is_omap3630()) {
 822                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 823                 /* Enable the l2 cache toggling in sleep logic */
 824                 enable_omap3630_toggle_l2_on_restore();
 825                 if (omap_rev() < OMAP3630_REV_ES1_2)
 826                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 827         }
 828 }
 829
 830 static int __init omap3_pm_init(void)
 831 {
 832         struct power_state *pwrst, *tmp;
 833         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 834         int ret;
 835
 836         if (!cpu_is_omap34xx())
 837                 return -ENODEV;
 838
 839         if (!omap3_has_io_chain_ctrl())
 840                 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
 841
 842         pm_errata_configure();
 843
 844         /* XXX prcm_setup_regs needs to be before enabling hw
 845          * supervised mode for powerdomains */
 846         prcm_setup_regs();
 847
 848         ret = request_irq(omap_prcm_event_to_irq("wkup"),
 849                 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
 850
 851         if (ret) {
 852                 pr_err("pm: Failed to request pm_wkup irq\n");
 853                 goto err1;
 854         }
 855
 856         /* IO interrupt is shared with mux code */
 857         ret = request_irq(omap_prcm_event_to_irq("io"),
 858                 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
 859                 omap3_pm_init);
 860
 861         if (ret) {
 862                 pr_err("pm: Failed to request pm_io irq\n");
 863                 goto err1;
 864         }
 865
 866         ret = pwrdm_for_each(pwrdms_setup, NULL);
 867         if (ret) {
 868                 printk(KERN_ERR "Failed to setup powerdomains\n");
 869                 goto err2;
 870         }
 871
 872         (void) clkdm_for_each(clkdms_setup, NULL);
 873
 874         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 875         if (mpu_pwrdm == NULL) {
 876                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 877                 goto err2;
 878         }
 879
 880         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 881         per_pwrdm = pwrdm_lookup("per_pwrdm");
 882         core_pwrdm = pwrdm_lookup("core_pwrdm");
 883         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 884
 885         neon_clkdm = clkdm_lookup("neon_clkdm");
 886         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 887         per_clkdm = clkdm_lookup("per_clkdm");
 888         core_clkdm = clkdm_lookup("core_clkdm");
 889
 890 #ifdef CONFIG_SUSPEND
 891         suspend_set_ops(&omap_pm_ops);
 892 #endif /* CONFIG_SUSPEND */
 893
 894         pm_idle = omap3_pm_idle;
 895         omap3_idle_init();
 896
 897         /*
 898          * RTA is disabled during initialization as per erratum i608
 899          * it is safer to disable RTA by the bootloader, but we would like
 900          * to be doubly sure here and prevent any mishaps.
 901          */
 902         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 903                 omap3630_ctrl_disable_rta();
 904
 905         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 906         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 907                 omap3_secure_ram_storage =
 908                         kmalloc(0x803F, GFP_KERNEL);
 909                 if (!omap3_secure_ram_storage)
 910                         printk(KERN_ERR "Memory allocation failed when"
 911                                         "allocating for secure sram context\n");
 912
 913                 local_irq_disable();
 914                 local_fiq_disable();
 915
 916                 omap_dma_global_context_save();
 917                 omap3_save_secure_ram_context();
 918                 omap_dma_global_context_restore();
 919
 920                 local_irq_enable();
 921                 local_fiq_enable();
 922         }
 923
 924         omap3_save_scratchpad_contents();
 925 err1:
 926         return ret;
 927 err2:
 928         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 929         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 930                 list_del(&pwrst->node);
 931                 kfree(pwrst);
 932         }
 933         return ret;
 934 }
 935
 936 late_initcall(omap3_pm_init);