Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph...
[firefly-linux-kernel-4.4.55.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2  * Hardware modules present on the OMAP44xx chips
3  *
4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Paul Walmsley
8  * Benoit Cousson
9  *
10  * This file is automatically generated from the OMAP hardware databases.
11  * We respectfully ask that any modifications to this file be coordinated
12  * with the public linux-omap@vger.kernel.org mailing list and the
13  * authors above to ensure that the autogeneration scripts are kept
14  * up-to-date with the file contents.
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20
21 #include <linux/io.h>
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/platform_data/omap_ocp2scp.h>
25 #include <linux/i2c-omap.h>
26
27 #include <linux/omap-dma.h>
28
29 #include <linux/platform_data/spi-omap2-mcspi.h>
30 #include <linux/platform_data/asoc-ti-mcbsp.h>
31 #include <linux/platform_data/iommu-omap.h>
32 #include <plat/dmtimer.h>
33
34 #include "omap_hwmod.h"
35 #include "omap_hwmod_common_data.h"
36 #include "cm1_44xx.h"
37 #include "cm2_44xx.h"
38 #include "prm44xx.h"
39 #include "prm-regbits-44xx.h"
40 #include "i2c.h"
41 #include "mmc.h"
42 #include "wd_timer.h"
43
44 /* Base offset for all OMAP4 interrupts external to MPUSS */
45 #define OMAP44XX_IRQ_GIC_START  32
46
47 /* Base offset for all OMAP4 dma requests */
48 #define OMAP44XX_DMA_REQ_START  1
49
50 /*
51  * IP blocks
52  */
53
54 /*
55  * 'c2c_target_fw' class
56  * instance(s): c2c_target_fw
57  */
58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
59         .name   = "c2c_target_fw",
60 };
61
62 /* c2c_target_fw */
63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
64         .name           = "c2c_target_fw",
65         .class          = &omap44xx_c2c_target_fw_hwmod_class,
66         .clkdm_name     = "d2d_clkdm",
67         .prcm = {
68                 .omap4 = {
69                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
70                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
71                 },
72         },
73 };
74
75 /*
76  * 'dmm' class
77  * instance(s): dmm
78  */
79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
80         .name   = "dmm",
81 };
82
83 /* dmm */
84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
85         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
86         { .irq = -1 }
87 };
88
89 static struct omap_hwmod omap44xx_dmm_hwmod = {
90         .name           = "dmm",
91         .class          = &omap44xx_dmm_hwmod_class,
92         .clkdm_name     = "l3_emif_clkdm",
93         .mpu_irqs       = omap44xx_dmm_irqs,
94         .prcm = {
95                 .omap4 = {
96                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
97                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
98                 },
99         },
100 };
101
102 /*
103  * 'emif_fw' class
104  * instance(s): emif_fw
105  */
106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
107         .name   = "emif_fw",
108 };
109
110 /* emif_fw */
111 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
112         .name           = "emif_fw",
113         .class          = &omap44xx_emif_fw_hwmod_class,
114         .clkdm_name     = "l3_emif_clkdm",
115         .prcm = {
116                 .omap4 = {
117                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
118                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
119                 },
120         },
121 };
122
123 /*
124  * 'l3' class
125  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
126  */
127 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
128         .name   = "l3",
129 };
130
131 /* l3_instr */
132 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
133         .name           = "l3_instr",
134         .class          = &omap44xx_l3_hwmod_class,
135         .clkdm_name     = "l3_instr_clkdm",
136         .prcm = {
137                 .omap4 = {
138                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
139                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
140                         .modulemode   = MODULEMODE_HWCTRL,
141                 },
142         },
143 };
144
145 /* l3_main_1 */
146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
147         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
148         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
149         { .irq = -1 }
150 };
151
152 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
153         .name           = "l3_main_1",
154         .class          = &omap44xx_l3_hwmod_class,
155         .clkdm_name     = "l3_1_clkdm",
156         .mpu_irqs       = omap44xx_l3_main_1_irqs,
157         .prcm = {
158                 .omap4 = {
159                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
160                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
161                 },
162         },
163 };
164
165 /* l3_main_2 */
166 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
167         .name           = "l3_main_2",
168         .class          = &omap44xx_l3_hwmod_class,
169         .clkdm_name     = "l3_2_clkdm",
170         .prcm = {
171                 .omap4 = {
172                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
173                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
174                 },
175         },
176 };
177
178 /* l3_main_3 */
179 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
180         .name           = "l3_main_3",
181         .class          = &omap44xx_l3_hwmod_class,
182         .clkdm_name     = "l3_instr_clkdm",
183         .prcm = {
184                 .omap4 = {
185                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
186                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
187                         .modulemode   = MODULEMODE_HWCTRL,
188                 },
189         },
190 };
191
192 /*
193  * 'l4' class
194  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
195  */
196 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
197         .name   = "l4",
198 };
199
200 /* l4_abe */
201 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
202         .name           = "l4_abe",
203         .class          = &omap44xx_l4_hwmod_class,
204         .clkdm_name     = "abe_clkdm",
205         .prcm = {
206                 .omap4 = {
207                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
208                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
209                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
210                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
211                 },
212         },
213 };
214
215 /* l4_cfg */
216 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
217         .name           = "l4_cfg",
218         .class          = &omap44xx_l4_hwmod_class,
219         .clkdm_name     = "l4_cfg_clkdm",
220         .prcm = {
221                 .omap4 = {
222                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
223                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
224                 },
225         },
226 };
227
228 /* l4_per */
229 static struct omap_hwmod omap44xx_l4_per_hwmod = {
230         .name           = "l4_per",
231         .class          = &omap44xx_l4_hwmod_class,
232         .clkdm_name     = "l4_per_clkdm",
233         .prcm = {
234                 .omap4 = {
235                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
236                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
237                 },
238         },
239 };
240
241 /* l4_wkup */
242 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
243         .name           = "l4_wkup",
244         .class          = &omap44xx_l4_hwmod_class,
245         .clkdm_name     = "l4_wkup_clkdm",
246         .prcm = {
247                 .omap4 = {
248                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
249                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
250                 },
251         },
252 };
253
254 /*
255  * 'mpu_bus' class
256  * instance(s): mpu_private
257  */
258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
259         .name   = "mpu_bus",
260 };
261
262 /* mpu_private */
263 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
264         .name           = "mpu_private",
265         .class          = &omap44xx_mpu_bus_hwmod_class,
266         .clkdm_name     = "mpuss_clkdm",
267         .prcm = {
268                 .omap4 = {
269                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
270                 },
271         },
272 };
273
274 /*
275  * 'ocp_wp_noc' class
276  * instance(s): ocp_wp_noc
277  */
278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
279         .name   = "ocp_wp_noc",
280 };
281
282 /* ocp_wp_noc */
283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
284         .name           = "ocp_wp_noc",
285         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
286         .clkdm_name     = "l3_instr_clkdm",
287         .prcm = {
288                 .omap4 = {
289                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
290                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
291                         .modulemode   = MODULEMODE_HWCTRL,
292                 },
293         },
294 };
295
296 /*
297  * Modules omap_hwmod structures
298  *
299  * The following IPs are excluded for the moment because:
300  * - They do not need an explicit SW control using omap_hwmod API.
301  * - They still need to be validated with the driver
302  *   properly adapted to omap_hwmod / omap_device
303  *
304  * usim
305  */
306
307 /*
308  * 'aess' class
309  * audio engine sub system
310  */
311
312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
313         .rev_offs       = 0x0000,
314         .sysc_offs      = 0x0010,
315         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
316         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
317                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
318                            MSTANDBY_SMART_WKUP),
319         .sysc_fields    = &omap_hwmod_sysc_type2,
320 };
321
322 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
323         .name   = "aess",
324         .sysc   = &omap44xx_aess_sysc,
325 };
326
327 /* aess */
328 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
329         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
330         { .irq = -1 }
331 };
332
333 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
334         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
335         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
336         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
337         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
338         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
339         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
340         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
341         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
342         { .dma_req = -1 }
343 };
344
345 static struct omap_hwmod omap44xx_aess_hwmod = {
346         .name           = "aess",
347         .class          = &omap44xx_aess_hwmod_class,
348         .clkdm_name     = "abe_clkdm",
349         .mpu_irqs       = omap44xx_aess_irqs,
350         .sdma_reqs      = omap44xx_aess_sdma_reqs,
351         .main_clk       = "aess_fck",
352         .prcm = {
353                 .omap4 = {
354                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
355                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
356                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
357                         .modulemode   = MODULEMODE_SWCTRL,
358                 },
359         },
360 };
361
362 /*
363  * 'c2c' class
364  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
365  * soc
366  */
367
368 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
369         .name   = "c2c",
370 };
371
372 /* c2c */
373 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
374         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
375         { .irq = -1 }
376 };
377
378 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
379         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
380         { .dma_req = -1 }
381 };
382
383 static struct omap_hwmod omap44xx_c2c_hwmod = {
384         .name           = "c2c",
385         .class          = &omap44xx_c2c_hwmod_class,
386         .clkdm_name     = "d2d_clkdm",
387         .mpu_irqs       = omap44xx_c2c_irqs,
388         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
389         .prcm = {
390                 .omap4 = {
391                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
392                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
393                 },
394         },
395 };
396
397 /*
398  * 'counter' class
399  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
400  */
401
402 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
403         .rev_offs       = 0x0000,
404         .sysc_offs      = 0x0004,
405         .sysc_flags     = SYSC_HAS_SIDLEMODE,
406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
407         .sysc_fields    = &omap_hwmod_sysc_type1,
408 };
409
410 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
411         .name   = "counter",
412         .sysc   = &omap44xx_counter_sysc,
413 };
414
415 /* counter_32k */
416 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
417         .name           = "counter_32k",
418         .class          = &omap44xx_counter_hwmod_class,
419         .clkdm_name     = "l4_wkup_clkdm",
420         .flags          = HWMOD_SWSUP_SIDLE,
421         .main_clk       = "sys_32k_ck",
422         .prcm = {
423                 .omap4 = {
424                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
425                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
426                 },
427         },
428 };
429
430 /*
431  * 'ctrl_module' class
432  * attila core control module + core pad control module + wkup pad control
433  * module + attila wkup control module
434  */
435
436 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
437         .rev_offs       = 0x0000,
438         .sysc_offs      = 0x0010,
439         .sysc_flags     = SYSC_HAS_SIDLEMODE,
440         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
441                            SIDLE_SMART_WKUP),
442         .sysc_fields    = &omap_hwmod_sysc_type2,
443 };
444
445 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
446         .name   = "ctrl_module",
447         .sysc   = &omap44xx_ctrl_module_sysc,
448 };
449
450 /* ctrl_module_core */
451 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
452         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
453         { .irq = -1 }
454 };
455
456 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
457         .name           = "ctrl_module_core",
458         .class          = &omap44xx_ctrl_module_hwmod_class,
459         .clkdm_name     = "l4_cfg_clkdm",
460         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
461         .prcm = {
462                 .omap4 = {
463                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
464                 },
465         },
466 };
467
468 /* ctrl_module_pad_core */
469 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
470         .name           = "ctrl_module_pad_core",
471         .class          = &omap44xx_ctrl_module_hwmod_class,
472         .clkdm_name     = "l4_cfg_clkdm",
473         .prcm = {
474                 .omap4 = {
475                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
476                 },
477         },
478 };
479
480 /* ctrl_module_wkup */
481 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
482         .name           = "ctrl_module_wkup",
483         .class          = &omap44xx_ctrl_module_hwmod_class,
484         .clkdm_name     = "l4_wkup_clkdm",
485         .prcm = {
486                 .omap4 = {
487                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
488                 },
489         },
490 };
491
492 /* ctrl_module_pad_wkup */
493 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
494         .name           = "ctrl_module_pad_wkup",
495         .class          = &omap44xx_ctrl_module_hwmod_class,
496         .clkdm_name     = "l4_wkup_clkdm",
497         .prcm = {
498                 .omap4 = {
499                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
500                 },
501         },
502 };
503
504 /*
505  * 'debugss' class
506  * debug and emulation sub system
507  */
508
509 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
510         .name   = "debugss",
511 };
512
513 /* debugss */
514 static struct omap_hwmod omap44xx_debugss_hwmod = {
515         .name           = "debugss",
516         .class          = &omap44xx_debugss_hwmod_class,
517         .clkdm_name     = "emu_sys_clkdm",
518         .main_clk       = "trace_clk_div_ck",
519         .prcm = {
520                 .omap4 = {
521                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
522                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
523                 },
524         },
525 };
526
527 /*
528  * 'dma' class
529  * dma controller for data exchange between memory to memory (i.e. internal or
530  * external memory) and gp peripherals to memory or memory to gp peripherals
531  */
532
533 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
534         .rev_offs       = 0x0000,
535         .sysc_offs      = 0x002c,
536         .syss_offs      = 0x0028,
537         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
538                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
539                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
540                            SYSS_HAS_RESET_STATUS),
541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
542                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
543         .sysc_fields    = &omap_hwmod_sysc_type1,
544 };
545
546 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
547         .name   = "dma",
548         .sysc   = &omap44xx_dma_sysc,
549 };
550
551 /* dma dev_attr */
552 static struct omap_dma_dev_attr dma_dev_attr = {
553         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
554                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
555         .lch_count      = 32,
556 };
557
558 /* dma_system */
559 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
560         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
561         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
562         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
563         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
564         { .irq = -1 }
565 };
566
567 static struct omap_hwmod omap44xx_dma_system_hwmod = {
568         .name           = "dma_system",
569         .class          = &omap44xx_dma_hwmod_class,
570         .clkdm_name     = "l3_dma_clkdm",
571         .mpu_irqs       = omap44xx_dma_system_irqs,
572         .main_clk       = "l3_div_ck",
573         .prcm = {
574                 .omap4 = {
575                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
576                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
577                 },
578         },
579         .dev_attr       = &dma_dev_attr,
580 };
581
582 /*
583  * 'dmic' class
584  * digital microphone controller
585  */
586
587 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
588         .rev_offs       = 0x0000,
589         .sysc_offs      = 0x0010,
590         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
591                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
592         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
593                            SIDLE_SMART_WKUP),
594         .sysc_fields    = &omap_hwmod_sysc_type2,
595 };
596
597 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
598         .name   = "dmic",
599         .sysc   = &omap44xx_dmic_sysc,
600 };
601
602 /* dmic */
603 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
604         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
605         { .irq = -1 }
606 };
607
608 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
609         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
610         { .dma_req = -1 }
611 };
612
613 static struct omap_hwmod omap44xx_dmic_hwmod = {
614         .name           = "dmic",
615         .class          = &omap44xx_dmic_hwmod_class,
616         .clkdm_name     = "abe_clkdm",
617         .mpu_irqs       = omap44xx_dmic_irqs,
618         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
619         .main_clk       = "func_dmic_abe_gfclk",
620         .prcm = {
621                 .omap4 = {
622                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
623                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
624                         .modulemode   = MODULEMODE_SWCTRL,
625                 },
626         },
627 };
628
629 /*
630  * 'dsp' class
631  * dsp sub-system
632  */
633
634 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
635         .name   = "dsp",
636 };
637
638 /* dsp */
639 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
640         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
641         { .irq = -1 }
642 };
643
644 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
645         { .name = "dsp", .rst_shift = 0 },
646 };
647
648 static struct omap_hwmod omap44xx_dsp_hwmod = {
649         .name           = "dsp",
650         .class          = &omap44xx_dsp_hwmod_class,
651         .clkdm_name     = "tesla_clkdm",
652         .mpu_irqs       = omap44xx_dsp_irqs,
653         .rst_lines      = omap44xx_dsp_resets,
654         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
655         .main_clk       = "dpll_iva_m4x2_ck",
656         .prcm = {
657                 .omap4 = {
658                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
659                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
660                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
661                         .modulemode   = MODULEMODE_HWCTRL,
662                 },
663         },
664 };
665
666 /*
667  * 'dss' class
668  * display sub-system
669  */
670
671 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
672         .rev_offs       = 0x0000,
673         .syss_offs      = 0x0014,
674         .sysc_flags     = SYSS_HAS_RESET_STATUS,
675 };
676
677 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
678         .name   = "dss",
679         .sysc   = &omap44xx_dss_sysc,
680         .reset  = omap_dss_reset,
681 };
682
683 /* dss */
684 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
685         { .role = "sys_clk", .clk = "dss_sys_clk" },
686         { .role = "tv_clk", .clk = "dss_tv_clk" },
687         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
688 };
689
690 static struct omap_hwmod omap44xx_dss_hwmod = {
691         .name           = "dss_core",
692         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
693         .class          = &omap44xx_dss_hwmod_class,
694         .clkdm_name     = "l3_dss_clkdm",
695         .main_clk       = "dss_dss_clk",
696         .prcm = {
697                 .omap4 = {
698                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
699                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
700                 },
701         },
702         .opt_clks       = dss_opt_clks,
703         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
704 };
705
706 /*
707  * 'dispc' class
708  * display controller
709  */
710
711 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
712         .rev_offs       = 0x0000,
713         .sysc_offs      = 0x0010,
714         .syss_offs      = 0x0014,
715         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
716                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
717                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
718                            SYSS_HAS_RESET_STATUS),
719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
720                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
721         .sysc_fields    = &omap_hwmod_sysc_type1,
722 };
723
724 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
725         .name   = "dispc",
726         .sysc   = &omap44xx_dispc_sysc,
727 };
728
729 /* dss_dispc */
730 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
731         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
732         { .irq = -1 }
733 };
734
735 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
736         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
737         { .dma_req = -1 }
738 };
739
740 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
741         .manager_count          = 3,
742         .has_framedonetv_irq    = 1
743 };
744
745 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
746         .name           = "dss_dispc",
747         .class          = &omap44xx_dispc_hwmod_class,
748         .clkdm_name     = "l3_dss_clkdm",
749         .mpu_irqs       = omap44xx_dss_dispc_irqs,
750         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
751         .main_clk       = "dss_dss_clk",
752         .prcm = {
753                 .omap4 = {
754                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
755                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
756                 },
757         },
758         .dev_attr       = &omap44xx_dss_dispc_dev_attr
759 };
760
761 /*
762  * 'dsi' class
763  * display serial interface controller
764  */
765
766 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
767         .rev_offs       = 0x0000,
768         .sysc_offs      = 0x0010,
769         .syss_offs      = 0x0014,
770         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
771                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
772                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
774         .sysc_fields    = &omap_hwmod_sysc_type1,
775 };
776
777 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
778         .name   = "dsi",
779         .sysc   = &omap44xx_dsi_sysc,
780 };
781
782 /* dss_dsi1 */
783 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
784         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
785         { .irq = -1 }
786 };
787
788 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
789         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
790         { .dma_req = -1 }
791 };
792
793 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
794         { .role = "sys_clk", .clk = "dss_sys_clk" },
795 };
796
797 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
798         .name           = "dss_dsi1",
799         .class          = &omap44xx_dsi_hwmod_class,
800         .clkdm_name     = "l3_dss_clkdm",
801         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
802         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
803         .main_clk       = "dss_dss_clk",
804         .prcm = {
805                 .omap4 = {
806                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
807                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
808                 },
809         },
810         .opt_clks       = dss_dsi1_opt_clks,
811         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
812 };
813
814 /* dss_dsi2 */
815 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
816         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
817         { .irq = -1 }
818 };
819
820 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
821         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
822         { .dma_req = -1 }
823 };
824
825 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
826         { .role = "sys_clk", .clk = "dss_sys_clk" },
827 };
828
829 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
830         .name           = "dss_dsi2",
831         .class          = &omap44xx_dsi_hwmod_class,
832         .clkdm_name     = "l3_dss_clkdm",
833         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
834         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
835         .main_clk       = "dss_dss_clk",
836         .prcm = {
837                 .omap4 = {
838                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
839                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
840                 },
841         },
842         .opt_clks       = dss_dsi2_opt_clks,
843         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
844 };
845
846 /*
847  * 'hdmi' class
848  * hdmi controller
849  */
850
851 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
852         .rev_offs       = 0x0000,
853         .sysc_offs      = 0x0010,
854         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
855                            SYSC_HAS_SOFTRESET),
856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
857                            SIDLE_SMART_WKUP),
858         .sysc_fields    = &omap_hwmod_sysc_type2,
859 };
860
861 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
862         .name   = "hdmi",
863         .sysc   = &omap44xx_hdmi_sysc,
864 };
865
866 /* dss_hdmi */
867 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
868         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
869         { .irq = -1 }
870 };
871
872 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
873         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
874         { .dma_req = -1 }
875 };
876
877 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
878         { .role = "sys_clk", .clk = "dss_sys_clk" },
879 };
880
881 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
882         .name           = "dss_hdmi",
883         .class          = &omap44xx_hdmi_hwmod_class,
884         .clkdm_name     = "l3_dss_clkdm",
885         /*
886          * HDMI audio requires to use no-idle mode. Hence,
887          * set idle mode by software.
888          */
889         .flags          = HWMOD_SWSUP_SIDLE,
890         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
891         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
892         .main_clk       = "dss_48mhz_clk",
893         .prcm = {
894                 .omap4 = {
895                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
896                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
897                 },
898         },
899         .opt_clks       = dss_hdmi_opt_clks,
900         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
901 };
902
903 /*
904  * 'rfbi' class
905  * remote frame buffer interface
906  */
907
908 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
909         .rev_offs       = 0x0000,
910         .sysc_offs      = 0x0010,
911         .syss_offs      = 0x0014,
912         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
913                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
914         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
915         .sysc_fields    = &omap_hwmod_sysc_type1,
916 };
917
918 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
919         .name   = "rfbi",
920         .sysc   = &omap44xx_rfbi_sysc,
921 };
922
923 /* dss_rfbi */
924 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
925         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
926         { .dma_req = -1 }
927 };
928
929 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
930         { .role = "ick", .clk = "dss_fck" },
931 };
932
933 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
934         .name           = "dss_rfbi",
935         .class          = &omap44xx_rfbi_hwmod_class,
936         .clkdm_name     = "l3_dss_clkdm",
937         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
938         .main_clk       = "dss_dss_clk",
939         .prcm = {
940                 .omap4 = {
941                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
942                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
943                 },
944         },
945         .opt_clks       = dss_rfbi_opt_clks,
946         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
947 };
948
949 /*
950  * 'venc' class
951  * video encoder
952  */
953
954 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
955         .name   = "venc",
956 };
957
958 /* dss_venc */
959 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
960         .name           = "dss_venc",
961         .class          = &omap44xx_venc_hwmod_class,
962         .clkdm_name     = "l3_dss_clkdm",
963         .main_clk       = "dss_tv_clk",
964         .prcm = {
965                 .omap4 = {
966                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
967                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
968                 },
969         },
970 };
971
972 /*
973  * 'elm' class
974  * bch error location module
975  */
976
977 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
978         .rev_offs       = 0x0000,
979         .sysc_offs      = 0x0010,
980         .syss_offs      = 0x0014,
981         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
982                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
983                            SYSS_HAS_RESET_STATUS),
984         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
985         .sysc_fields    = &omap_hwmod_sysc_type1,
986 };
987
988 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
989         .name   = "elm",
990         .sysc   = &omap44xx_elm_sysc,
991 };
992
993 /* elm */
994 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
995         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
996         { .irq = -1 }
997 };
998
999 static struct omap_hwmod omap44xx_elm_hwmod = {
1000         .name           = "elm",
1001         .class          = &omap44xx_elm_hwmod_class,
1002         .clkdm_name     = "l4_per_clkdm",
1003         .mpu_irqs       = omap44xx_elm_irqs,
1004         .prcm = {
1005                 .omap4 = {
1006                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1007                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1008                 },
1009         },
1010 };
1011
1012 /*
1013  * 'emif' class
1014  * external memory interface no1
1015  */
1016
1017 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1018         .rev_offs       = 0x0000,
1019 };
1020
1021 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1022         .name   = "emif",
1023         .sysc   = &omap44xx_emif_sysc,
1024 };
1025
1026 /* emif1 */
1027 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1028         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1029         { .irq = -1 }
1030 };
1031
1032 static struct omap_hwmod omap44xx_emif1_hwmod = {
1033         .name           = "emif1",
1034         .class          = &omap44xx_emif_hwmod_class,
1035         .clkdm_name     = "l3_emif_clkdm",
1036         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1037         .mpu_irqs       = omap44xx_emif1_irqs,
1038         .main_clk       = "ddrphy_ck",
1039         .prcm = {
1040                 .omap4 = {
1041                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1042                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1043                         .modulemode   = MODULEMODE_HWCTRL,
1044                 },
1045         },
1046 };
1047
1048 /* emif2 */
1049 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1050         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1051         { .irq = -1 }
1052 };
1053
1054 static struct omap_hwmod omap44xx_emif2_hwmod = {
1055         .name           = "emif2",
1056         .class          = &omap44xx_emif_hwmod_class,
1057         .clkdm_name     = "l3_emif_clkdm",
1058         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1059         .mpu_irqs       = omap44xx_emif2_irqs,
1060         .main_clk       = "ddrphy_ck",
1061         .prcm = {
1062                 .omap4 = {
1063                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1064                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1065                         .modulemode   = MODULEMODE_HWCTRL,
1066                 },
1067         },
1068 };
1069
1070 /*
1071  * 'fdif' class
1072  * face detection hw accelerator module
1073  */
1074
1075 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1076         .rev_offs       = 0x0000,
1077         .sysc_offs      = 0x0010,
1078         /*
1079          * FDIF needs 100 OCP clk cycles delay after a softreset before
1080          * accessing sysconfig again.
1081          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1082          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1083          *
1084          * TODO: Indicate errata when available.
1085          */
1086         .srst_udelay    = 2,
1087         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1088                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1089         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1090                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1091         .sysc_fields    = &omap_hwmod_sysc_type2,
1092 };
1093
1094 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1095         .name   = "fdif",
1096         .sysc   = &omap44xx_fdif_sysc,
1097 };
1098
1099 /* fdif */
1100 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1101         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1102         { .irq = -1 }
1103 };
1104
1105 static struct omap_hwmod omap44xx_fdif_hwmod = {
1106         .name           = "fdif",
1107         .class          = &omap44xx_fdif_hwmod_class,
1108         .clkdm_name     = "iss_clkdm",
1109         .mpu_irqs       = omap44xx_fdif_irqs,
1110         .main_clk       = "fdif_fck",
1111         .prcm = {
1112                 .omap4 = {
1113                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1114                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1115                         .modulemode   = MODULEMODE_SWCTRL,
1116                 },
1117         },
1118 };
1119
1120 /*
1121  * 'gpio' class
1122  * general purpose io module
1123  */
1124
1125 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1126         .rev_offs       = 0x0000,
1127         .sysc_offs      = 0x0010,
1128         .syss_offs      = 0x0114,
1129         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1130                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1131                            SYSS_HAS_RESET_STATUS),
1132         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1133                            SIDLE_SMART_WKUP),
1134         .sysc_fields    = &omap_hwmod_sysc_type1,
1135 };
1136
1137 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1138         .name   = "gpio",
1139         .sysc   = &omap44xx_gpio_sysc,
1140         .rev    = 2,
1141 };
1142
1143 /* gpio dev_attr */
1144 static struct omap_gpio_dev_attr gpio_dev_attr = {
1145         .bank_width     = 32,
1146         .dbck_flag      = true,
1147 };
1148
1149 /* gpio1 */
1150 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1151         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1152         { .irq = -1 }
1153 };
1154
1155 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1156         { .role = "dbclk", .clk = "gpio1_dbclk" },
1157 };
1158
1159 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1160         .name           = "gpio1",
1161         .class          = &omap44xx_gpio_hwmod_class,
1162         .clkdm_name     = "l4_wkup_clkdm",
1163         .mpu_irqs       = omap44xx_gpio1_irqs,
1164         .main_clk       = "l4_wkup_clk_mux_ck",
1165         .prcm = {
1166                 .omap4 = {
1167                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1168                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1169                         .modulemode   = MODULEMODE_HWCTRL,
1170                 },
1171         },
1172         .opt_clks       = gpio1_opt_clks,
1173         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1174         .dev_attr       = &gpio_dev_attr,
1175 };
1176
1177 /* gpio2 */
1178 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1179         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1180         { .irq = -1 }
1181 };
1182
1183 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1184         { .role = "dbclk", .clk = "gpio2_dbclk" },
1185 };
1186
1187 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1188         .name           = "gpio2",
1189         .class          = &omap44xx_gpio_hwmod_class,
1190         .clkdm_name     = "l4_per_clkdm",
1191         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192         .mpu_irqs       = omap44xx_gpio2_irqs,
1193         .main_clk       = "l4_div_ck",
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1197                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1198                         .modulemode   = MODULEMODE_HWCTRL,
1199                 },
1200         },
1201         .opt_clks       = gpio2_opt_clks,
1202         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1203         .dev_attr       = &gpio_dev_attr,
1204 };
1205
1206 /* gpio3 */
1207 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1208         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1209         { .irq = -1 }
1210 };
1211
1212 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1213         { .role = "dbclk", .clk = "gpio3_dbclk" },
1214 };
1215
1216 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1217         .name           = "gpio3",
1218         .class          = &omap44xx_gpio_hwmod_class,
1219         .clkdm_name     = "l4_per_clkdm",
1220         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221         .mpu_irqs       = omap44xx_gpio3_irqs,
1222         .main_clk       = "l4_div_ck",
1223         .prcm = {
1224                 .omap4 = {
1225                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1226                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1227                         .modulemode   = MODULEMODE_HWCTRL,
1228                 },
1229         },
1230         .opt_clks       = gpio3_opt_clks,
1231         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1232         .dev_attr       = &gpio_dev_attr,
1233 };
1234
1235 /* gpio4 */
1236 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1237         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1238         { .irq = -1 }
1239 };
1240
1241 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1242         { .role = "dbclk", .clk = "gpio4_dbclk" },
1243 };
1244
1245 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1246         .name           = "gpio4",
1247         .class          = &omap44xx_gpio_hwmod_class,
1248         .clkdm_name     = "l4_per_clkdm",
1249         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250         .mpu_irqs       = omap44xx_gpio4_irqs,
1251         .main_clk       = "l4_div_ck",
1252         .prcm = {
1253                 .omap4 = {
1254                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1255                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1256                         .modulemode   = MODULEMODE_HWCTRL,
1257                 },
1258         },
1259         .opt_clks       = gpio4_opt_clks,
1260         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1261         .dev_attr       = &gpio_dev_attr,
1262 };
1263
1264 /* gpio5 */
1265 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1266         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1267         { .irq = -1 }
1268 };
1269
1270 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1271         { .role = "dbclk", .clk = "gpio5_dbclk" },
1272 };
1273
1274 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1275         .name           = "gpio5",
1276         .class          = &omap44xx_gpio_hwmod_class,
1277         .clkdm_name     = "l4_per_clkdm",
1278         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279         .mpu_irqs       = omap44xx_gpio5_irqs,
1280         .main_clk       = "l4_div_ck",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1284                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1285                         .modulemode   = MODULEMODE_HWCTRL,
1286                 },
1287         },
1288         .opt_clks       = gpio5_opt_clks,
1289         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1290         .dev_attr       = &gpio_dev_attr,
1291 };
1292
1293 /* gpio6 */
1294 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1295         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1296         { .irq = -1 }
1297 };
1298
1299 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1300         { .role = "dbclk", .clk = "gpio6_dbclk" },
1301 };
1302
1303 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1304         .name           = "gpio6",
1305         .class          = &omap44xx_gpio_hwmod_class,
1306         .clkdm_name     = "l4_per_clkdm",
1307         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1308         .mpu_irqs       = omap44xx_gpio6_irqs,
1309         .main_clk       = "l4_div_ck",
1310         .prcm = {
1311                 .omap4 = {
1312                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1313                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1314                         .modulemode   = MODULEMODE_HWCTRL,
1315                 },
1316         },
1317         .opt_clks       = gpio6_opt_clks,
1318         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1319         .dev_attr       = &gpio_dev_attr,
1320 };
1321
1322 /*
1323  * 'gpmc' class
1324  * general purpose memory controller
1325  */
1326
1327 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1328         .rev_offs       = 0x0000,
1329         .sysc_offs      = 0x0010,
1330         .syss_offs      = 0x0014,
1331         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1332                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1333         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1334         .sysc_fields    = &omap_hwmod_sysc_type1,
1335 };
1336
1337 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1338         .name   = "gpmc",
1339         .sysc   = &omap44xx_gpmc_sysc,
1340 };
1341
1342 /* gpmc */
1343 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1344         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1345         { .irq = -1 }
1346 };
1347
1348 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1349         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1350         { .dma_req = -1 }
1351 };
1352
1353 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1354         .name           = "gpmc",
1355         .class          = &omap44xx_gpmc_hwmod_class,
1356         .clkdm_name     = "l3_2_clkdm",
1357         /*
1358          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1359          * block.  It is not being added due to any known bugs with
1360          * resetting the GPMC IP block, but rather because any timings
1361          * set by the bootloader are not being correctly programmed by
1362          * the kernel from the board file or DT data.
1363          * HWMOD_INIT_NO_RESET should be removed ASAP.
1364          */
1365         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1366         .mpu_irqs       = omap44xx_gpmc_irqs,
1367         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1368         .prcm = {
1369                 .omap4 = {
1370                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1371                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1372                         .modulemode   = MODULEMODE_HWCTRL,
1373                 },
1374         },
1375 };
1376
1377 /*
1378  * 'gpu' class
1379  * 2d/3d graphics accelerator
1380  */
1381
1382 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1383         .rev_offs       = 0x1fc00,
1384         .sysc_offs      = 0x1fc10,
1385         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1386         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1387                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1388                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1389         .sysc_fields    = &omap_hwmod_sysc_type2,
1390 };
1391
1392 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1393         .name   = "gpu",
1394         .sysc   = &omap44xx_gpu_sysc,
1395 };
1396
1397 /* gpu */
1398 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1399         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1400         { .irq = -1 }
1401 };
1402
1403 static struct omap_hwmod omap44xx_gpu_hwmod = {
1404         .name           = "gpu",
1405         .class          = &omap44xx_gpu_hwmod_class,
1406         .clkdm_name     = "l3_gfx_clkdm",
1407         .mpu_irqs       = omap44xx_gpu_irqs,
1408         .main_clk       = "sgx_clk_mux",
1409         .prcm = {
1410                 .omap4 = {
1411                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1412                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1413                         .modulemode   = MODULEMODE_SWCTRL,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'hdq1w' class
1420  * hdq / 1-wire serial interface controller
1421  */
1422
1423 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1424         .rev_offs       = 0x0000,
1425         .sysc_offs      = 0x0014,
1426         .syss_offs      = 0x0018,
1427         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1428                            SYSS_HAS_RESET_STATUS),
1429         .sysc_fields    = &omap_hwmod_sysc_type1,
1430 };
1431
1432 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1433         .name   = "hdq1w",
1434         .sysc   = &omap44xx_hdq1w_sysc,
1435 };
1436
1437 /* hdq1w */
1438 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1439         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1440         { .irq = -1 }
1441 };
1442
1443 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1444         .name           = "hdq1w",
1445         .class          = &omap44xx_hdq1w_hwmod_class,
1446         .clkdm_name     = "l4_per_clkdm",
1447         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1448         .mpu_irqs       = omap44xx_hdq1w_irqs,
1449         .main_clk       = "func_12m_fclk",
1450         .prcm = {
1451                 .omap4 = {
1452                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1453                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1454                         .modulemode   = MODULEMODE_SWCTRL,
1455                 },
1456         },
1457 };
1458
1459 /*
1460  * 'hsi' class
1461  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1462  * serial if)
1463  */
1464
1465 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1466         .rev_offs       = 0x0000,
1467         .sysc_offs      = 0x0010,
1468         .syss_offs      = 0x0014,
1469         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1470                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1471                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1472         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1473                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1474                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1475         .sysc_fields    = &omap_hwmod_sysc_type1,
1476 };
1477
1478 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1479         .name   = "hsi",
1480         .sysc   = &omap44xx_hsi_sysc,
1481 };
1482
1483 /* hsi */
1484 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1485         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1486         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1488         { .irq = -1 }
1489 };
1490
1491 static struct omap_hwmod omap44xx_hsi_hwmod = {
1492         .name           = "hsi",
1493         .class          = &omap44xx_hsi_hwmod_class,
1494         .clkdm_name     = "l3_init_clkdm",
1495         .mpu_irqs       = omap44xx_hsi_irqs,
1496         .main_clk       = "hsi_fck",
1497         .prcm = {
1498                 .omap4 = {
1499                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1500                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1501                         .modulemode   = MODULEMODE_HWCTRL,
1502                 },
1503         },
1504 };
1505
1506 /*
1507  * 'i2c' class
1508  * multimaster high-speed i2c controller
1509  */
1510
1511 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1512         .sysc_offs      = 0x0010,
1513         .syss_offs      = 0x0090,
1514         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1515                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1516                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1517         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1518                            SIDLE_SMART_WKUP),
1519         .clockact       = CLOCKACT_TEST_ICLK,
1520         .sysc_fields    = &omap_hwmod_sysc_type1,
1521 };
1522
1523 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1524         .name   = "i2c",
1525         .sysc   = &omap44xx_i2c_sysc,
1526         .rev    = OMAP_I2C_IP_VERSION_2,
1527         .reset  = &omap_i2c_reset,
1528 };
1529
1530 static struct omap_i2c_dev_attr i2c_dev_attr = {
1531         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1532 };
1533
1534 /* i2c1 */
1535 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1536         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1537         { .irq = -1 }
1538 };
1539
1540 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1541         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1542         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1543         { .dma_req = -1 }
1544 };
1545
1546 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1547         .name           = "i2c1",
1548         .class          = &omap44xx_i2c_hwmod_class,
1549         .clkdm_name     = "l4_per_clkdm",
1550         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1551         .mpu_irqs       = omap44xx_i2c1_irqs,
1552         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1553         .main_clk       = "func_96m_fclk",
1554         .prcm = {
1555                 .omap4 = {
1556                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1557                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1558                         .modulemode   = MODULEMODE_SWCTRL,
1559                 },
1560         },
1561         .dev_attr       = &i2c_dev_attr,
1562 };
1563
1564 /* i2c2 */
1565 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1566         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1567         { .irq = -1 }
1568 };
1569
1570 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1571         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1572         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1573         { .dma_req = -1 }
1574 };
1575
1576 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1577         .name           = "i2c2",
1578         .class          = &omap44xx_i2c_hwmod_class,
1579         .clkdm_name     = "l4_per_clkdm",
1580         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1581         .mpu_irqs       = omap44xx_i2c2_irqs,
1582         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1583         .main_clk       = "func_96m_fclk",
1584         .prcm = {
1585                 .omap4 = {
1586                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1587                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1588                         .modulemode   = MODULEMODE_SWCTRL,
1589                 },
1590         },
1591         .dev_attr       = &i2c_dev_attr,
1592 };
1593
1594 /* i2c3 */
1595 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1596         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1597         { .irq = -1 }
1598 };
1599
1600 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1601         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1602         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1603         { .dma_req = -1 }
1604 };
1605
1606 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1607         .name           = "i2c3",
1608         .class          = &omap44xx_i2c_hwmod_class,
1609         .clkdm_name     = "l4_per_clkdm",
1610         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1611         .mpu_irqs       = omap44xx_i2c3_irqs,
1612         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1613         .main_clk       = "func_96m_fclk",
1614         .prcm = {
1615                 .omap4 = {
1616                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1617                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1618                         .modulemode   = MODULEMODE_SWCTRL,
1619                 },
1620         },
1621         .dev_attr       = &i2c_dev_attr,
1622 };
1623
1624 /* i2c4 */
1625 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1626         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1627         { .irq = -1 }
1628 };
1629
1630 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1631         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1632         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1633         { .dma_req = -1 }
1634 };
1635
1636 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1637         .name           = "i2c4",
1638         .class          = &omap44xx_i2c_hwmod_class,
1639         .clkdm_name     = "l4_per_clkdm",
1640         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1641         .mpu_irqs       = omap44xx_i2c4_irqs,
1642         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1643         .main_clk       = "func_96m_fclk",
1644         .prcm = {
1645                 .omap4 = {
1646                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1647                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1648                         .modulemode   = MODULEMODE_SWCTRL,
1649                 },
1650         },
1651         .dev_attr       = &i2c_dev_attr,
1652 };
1653
1654 /*
1655  * 'ipu' class
1656  * imaging processor unit
1657  */
1658
1659 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1660         .name   = "ipu",
1661 };
1662
1663 /* ipu */
1664 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1665         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1666         { .irq = -1 }
1667 };
1668
1669 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1670         { .name = "cpu0", .rst_shift = 0 },
1671         { .name = "cpu1", .rst_shift = 1 },
1672 };
1673
1674 static struct omap_hwmod omap44xx_ipu_hwmod = {
1675         .name           = "ipu",
1676         .class          = &omap44xx_ipu_hwmod_class,
1677         .clkdm_name     = "ducati_clkdm",
1678         .mpu_irqs       = omap44xx_ipu_irqs,
1679         .rst_lines      = omap44xx_ipu_resets,
1680         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1681         .main_clk       = "ducati_clk_mux_ck",
1682         .prcm = {
1683                 .omap4 = {
1684                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1685                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1686                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1687                         .modulemode   = MODULEMODE_HWCTRL,
1688                 },
1689         },
1690 };
1691
1692 /*
1693  * 'iss' class
1694  * external images sensor pixel data processor
1695  */
1696
1697 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1698         .rev_offs       = 0x0000,
1699         .sysc_offs      = 0x0010,
1700         /*
1701          * ISS needs 100 OCP clk cycles delay after a softreset before
1702          * accessing sysconfig again.
1703          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1704          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1705          *
1706          * TODO: Indicate errata when available.
1707          */
1708         .srst_udelay    = 2,
1709         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1710                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1711         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1712                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1713                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1714         .sysc_fields    = &omap_hwmod_sysc_type2,
1715 };
1716
1717 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1718         .name   = "iss",
1719         .sysc   = &omap44xx_iss_sysc,
1720 };
1721
1722 /* iss */
1723 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1724         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1725         { .irq = -1 }
1726 };
1727
1728 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1729         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1730         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1731         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1732         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1733         { .dma_req = -1 }
1734 };
1735
1736 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1737         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1738 };
1739
1740 static struct omap_hwmod omap44xx_iss_hwmod = {
1741         .name           = "iss",
1742         .class          = &omap44xx_iss_hwmod_class,
1743         .clkdm_name     = "iss_clkdm",
1744         .mpu_irqs       = omap44xx_iss_irqs,
1745         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1746         .main_clk       = "ducati_clk_mux_ck",
1747         .prcm = {
1748                 .omap4 = {
1749                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1750                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1751                         .modulemode   = MODULEMODE_SWCTRL,
1752                 },
1753         },
1754         .opt_clks       = iss_opt_clks,
1755         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1756 };
1757
1758 /*
1759  * 'iva' class
1760  * multi-standard video encoder/decoder hardware accelerator
1761  */
1762
1763 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1764         .name   = "iva",
1765 };
1766
1767 /* iva */
1768 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1769         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1770         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1772         { .irq = -1 }
1773 };
1774
1775 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1776         { .name = "seq0", .rst_shift = 0 },
1777         { .name = "seq1", .rst_shift = 1 },
1778         { .name = "logic", .rst_shift = 2 },
1779 };
1780
1781 static struct omap_hwmod omap44xx_iva_hwmod = {
1782         .name           = "iva",
1783         .class          = &omap44xx_iva_hwmod_class,
1784         .clkdm_name     = "ivahd_clkdm",
1785         .mpu_irqs       = omap44xx_iva_irqs,
1786         .rst_lines      = omap44xx_iva_resets,
1787         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1788         .main_clk       = "dpll_iva_m5x2_ck",
1789         .prcm = {
1790                 .omap4 = {
1791                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1792                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1793                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1794                         .modulemode   = MODULEMODE_HWCTRL,
1795                 },
1796         },
1797 };
1798
1799 /*
1800  * 'kbd' class
1801  * keyboard controller
1802  */
1803
1804 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1805         .rev_offs       = 0x0000,
1806         .sysc_offs      = 0x0010,
1807         .syss_offs      = 0x0014,
1808         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1809                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1810                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1811                            SYSS_HAS_RESET_STATUS),
1812         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1813         .sysc_fields    = &omap_hwmod_sysc_type1,
1814 };
1815
1816 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1817         .name   = "kbd",
1818         .sysc   = &omap44xx_kbd_sysc,
1819 };
1820
1821 /* kbd */
1822 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1823         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1824         { .irq = -1 }
1825 };
1826
1827 static struct omap_hwmod omap44xx_kbd_hwmod = {
1828         .name           = "kbd",
1829         .class          = &omap44xx_kbd_hwmod_class,
1830         .clkdm_name     = "l4_wkup_clkdm",
1831         .mpu_irqs       = omap44xx_kbd_irqs,
1832         .main_clk       = "sys_32k_ck",
1833         .prcm = {
1834                 .omap4 = {
1835                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1836                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1837                         .modulemode   = MODULEMODE_SWCTRL,
1838                 },
1839         },
1840 };
1841
1842 /*
1843  * 'mailbox' class
1844  * mailbox module allowing communication between the on-chip processors using a
1845  * queued mailbox-interrupt mechanism.
1846  */
1847
1848 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1849         .rev_offs       = 0x0000,
1850         .sysc_offs      = 0x0010,
1851         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1852                            SYSC_HAS_SOFTRESET),
1853         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1854         .sysc_fields    = &omap_hwmod_sysc_type2,
1855 };
1856
1857 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1858         .name   = "mailbox",
1859         .sysc   = &omap44xx_mailbox_sysc,
1860 };
1861
1862 /* mailbox */
1863 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1864         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1865         { .irq = -1 }
1866 };
1867
1868 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1869         .name           = "mailbox",
1870         .class          = &omap44xx_mailbox_hwmod_class,
1871         .clkdm_name     = "l4_cfg_clkdm",
1872         .mpu_irqs       = omap44xx_mailbox_irqs,
1873         .prcm = {
1874                 .omap4 = {
1875                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1876                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1877                 },
1878         },
1879 };
1880
1881 /*
1882  * 'mcasp' class
1883  * multi-channel audio serial port controller
1884  */
1885
1886 /* The IP is not compliant to type1 / type2 scheme */
1887 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1888         .sidle_shift    = 0,
1889 };
1890
1891 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1892         .sysc_offs      = 0x0004,
1893         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1894         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1895                            SIDLE_SMART_WKUP),
1896         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1897 };
1898
1899 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1900         .name   = "mcasp",
1901         .sysc   = &omap44xx_mcasp_sysc,
1902 };
1903
1904 /* mcasp */
1905 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1906         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1907         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1908         { .irq = -1 }
1909 };
1910
1911 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1912         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1913         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1914         { .dma_req = -1 }
1915 };
1916
1917 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1918         .name           = "mcasp",
1919         .class          = &omap44xx_mcasp_hwmod_class,
1920         .clkdm_name     = "abe_clkdm",
1921         .mpu_irqs       = omap44xx_mcasp_irqs,
1922         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1923         .main_clk       = "func_mcasp_abe_gfclk",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1927                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1928                         .modulemode   = MODULEMODE_SWCTRL,
1929                 },
1930         },
1931 };
1932
1933 /*
1934  * 'mcbsp' class
1935  * multi channel buffered serial port controller
1936  */
1937
1938 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1939         .sysc_offs      = 0x008c,
1940         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1941                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1943         .sysc_fields    = &omap_hwmod_sysc_type1,
1944 };
1945
1946 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1947         .name   = "mcbsp",
1948         .sysc   = &omap44xx_mcbsp_sysc,
1949         .rev    = MCBSP_CONFIG_TYPE4,
1950 };
1951
1952 /* mcbsp1 */
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1954         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1955         { .irq = -1 }
1956 };
1957
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1959         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1960         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1961         { .dma_req = -1 }
1962 };
1963
1964 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1965         { .role = "pad_fck", .clk = "pad_clks_ck" },
1966         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1967 };
1968
1969 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1970         .name           = "mcbsp1",
1971         .class          = &omap44xx_mcbsp_hwmod_class,
1972         .clkdm_name     = "abe_clkdm",
1973         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1974         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1975         .main_clk       = "func_mcbsp1_gfclk",
1976         .prcm = {
1977                 .omap4 = {
1978                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1979                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1980                         .modulemode   = MODULEMODE_SWCTRL,
1981                 },
1982         },
1983         .opt_clks       = mcbsp1_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1985 };
1986
1987 /* mcbsp2 */
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1989         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1990         { .irq = -1 }
1991 };
1992
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1994         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1995         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1996         { .dma_req = -1 }
1997 };
1998
1999 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2000         { .role = "pad_fck", .clk = "pad_clks_ck" },
2001         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2002 };
2003
2004 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2005         .name           = "mcbsp2",
2006         .class          = &omap44xx_mcbsp_hwmod_class,
2007         .clkdm_name     = "abe_clkdm",
2008         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2009         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2010         .main_clk       = "func_mcbsp2_gfclk",
2011         .prcm = {
2012                 .omap4 = {
2013                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2014                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2015                         .modulemode   = MODULEMODE_SWCTRL,
2016                 },
2017         },
2018         .opt_clks       = mcbsp2_opt_clks,
2019         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2020 };
2021
2022 /* mcbsp3 */
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2024         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2025         { .irq = -1 }
2026 };
2027
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2029         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2030         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2031         { .dma_req = -1 }
2032 };
2033
2034 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2035         { .role = "pad_fck", .clk = "pad_clks_ck" },
2036         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2037 };
2038
2039 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2040         .name           = "mcbsp3",
2041         .class          = &omap44xx_mcbsp_hwmod_class,
2042         .clkdm_name     = "abe_clkdm",
2043         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2044         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2045         .main_clk       = "func_mcbsp3_gfclk",
2046         .prcm = {
2047                 .omap4 = {
2048                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2049                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2050                         .modulemode   = MODULEMODE_SWCTRL,
2051                 },
2052         },
2053         .opt_clks       = mcbsp3_opt_clks,
2054         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2055 };
2056
2057 /* mcbsp4 */
2058 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2059         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2060         { .irq = -1 }
2061 };
2062
2063 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2064         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2065         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2066         { .dma_req = -1 }
2067 };
2068
2069 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2070         { .role = "pad_fck", .clk = "pad_clks_ck" },
2071         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2072 };
2073
2074 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2075         .name           = "mcbsp4",
2076         .class          = &omap44xx_mcbsp_hwmod_class,
2077         .clkdm_name     = "l4_per_clkdm",
2078         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2079         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2080         .main_clk       = "per_mcbsp4_gfclk",
2081         .prcm = {
2082                 .omap4 = {
2083                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2084                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2085                         .modulemode   = MODULEMODE_SWCTRL,
2086                 },
2087         },
2088         .opt_clks       = mcbsp4_opt_clks,
2089         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2090 };
2091
2092 /*
2093  * 'mcpdm' class
2094  * multi channel pdm controller (proprietary interface with phoenix power
2095  * ic)
2096  */
2097
2098 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2099         .rev_offs       = 0x0000,
2100         .sysc_offs      = 0x0010,
2101         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2102                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2104                            SIDLE_SMART_WKUP),
2105         .sysc_fields    = &omap_hwmod_sysc_type2,
2106 };
2107
2108 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2109         .name   = "mcpdm",
2110         .sysc   = &omap44xx_mcpdm_sysc,
2111 };
2112
2113 /* mcpdm */
2114 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2115         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2116         { .irq = -1 }
2117 };
2118
2119 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2120         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2121         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2122         { .dma_req = -1 }
2123 };
2124
2125 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2126         .name           = "mcpdm",
2127         .class          = &omap44xx_mcpdm_hwmod_class,
2128         .clkdm_name     = "abe_clkdm",
2129         /*
2130          * It's suspected that the McPDM requires an off-chip main
2131          * functional clock, controlled via I2C.  This IP block is
2132          * currently reset very early during boot, before I2C is
2133          * available, so it doesn't seem that we have any choice in
2134          * the kernel other than to avoid resetting it.
2135          *
2136          * Also, McPDM needs to be configured to NO_IDLE mode when it
2137          * is in used otherwise vital clocks will be gated which
2138          * results 'slow motion' audio playback.
2139          */
2140         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
2141         .mpu_irqs       = omap44xx_mcpdm_irqs,
2142         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2143         .main_clk       = "pad_clks_ck",
2144         .prcm = {
2145                 .omap4 = {
2146                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2147                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2148                         .modulemode   = MODULEMODE_SWCTRL,
2149                 },
2150         },
2151 };
2152
2153 /*
2154  * 'mcspi' class
2155  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2156  * bus
2157  */
2158
2159 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2160         .rev_offs       = 0x0000,
2161         .sysc_offs      = 0x0010,
2162         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2163                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2165                            SIDLE_SMART_WKUP),
2166         .sysc_fields    = &omap_hwmod_sysc_type2,
2167 };
2168
2169 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2170         .name   = "mcspi",
2171         .sysc   = &omap44xx_mcspi_sysc,
2172         .rev    = OMAP4_MCSPI_REV,
2173 };
2174
2175 /* mcspi1 */
2176 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2177         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2178         { .irq = -1 }
2179 };
2180
2181 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2182         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2183         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2184         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2185         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2186         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2187         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2188         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2189         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2190         { .dma_req = -1 }
2191 };
2192
2193 /* mcspi1 dev_attr */
2194 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2195         .num_chipselect = 4,
2196 };
2197
2198 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2199         .name           = "mcspi1",
2200         .class          = &omap44xx_mcspi_hwmod_class,
2201         .clkdm_name     = "l4_per_clkdm",
2202         .mpu_irqs       = omap44xx_mcspi1_irqs,
2203         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2204         .main_clk       = "func_48m_fclk",
2205         .prcm = {
2206                 .omap4 = {
2207                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2208                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2209                         .modulemode   = MODULEMODE_SWCTRL,
2210                 },
2211         },
2212         .dev_attr       = &mcspi1_dev_attr,
2213 };
2214
2215 /* mcspi2 */
2216 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2217         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2218         { .irq = -1 }
2219 };
2220
2221 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2222         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2223         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2224         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2225         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2226         { .dma_req = -1 }
2227 };
2228
2229 /* mcspi2 dev_attr */
2230 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2231         .num_chipselect = 2,
2232 };
2233
2234 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2235         .name           = "mcspi2",
2236         .class          = &omap44xx_mcspi_hwmod_class,
2237         .clkdm_name     = "l4_per_clkdm",
2238         .mpu_irqs       = omap44xx_mcspi2_irqs,
2239         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2240         .main_clk       = "func_48m_fclk",
2241         .prcm = {
2242                 .omap4 = {
2243                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2244                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2245                         .modulemode   = MODULEMODE_SWCTRL,
2246                 },
2247         },
2248         .dev_attr       = &mcspi2_dev_attr,
2249 };
2250
2251 /* mcspi3 */
2252 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2253         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2254         { .irq = -1 }
2255 };
2256
2257 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2258         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2259         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2260         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2261         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2262         { .dma_req = -1 }
2263 };
2264
2265 /* mcspi3 dev_attr */
2266 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2267         .num_chipselect = 2,
2268 };
2269
2270 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2271         .name           = "mcspi3",
2272         .class          = &omap44xx_mcspi_hwmod_class,
2273         .clkdm_name     = "l4_per_clkdm",
2274         .mpu_irqs       = omap44xx_mcspi3_irqs,
2275         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2276         .main_clk       = "func_48m_fclk",
2277         .prcm = {
2278                 .omap4 = {
2279                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2280                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2281                         .modulemode   = MODULEMODE_SWCTRL,
2282                 },
2283         },
2284         .dev_attr       = &mcspi3_dev_attr,
2285 };
2286
2287 /* mcspi4 */
2288 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2289         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2290         { .irq = -1 }
2291 };
2292
2293 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2294         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2295         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2296         { .dma_req = -1 }
2297 };
2298
2299 /* mcspi4 dev_attr */
2300 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2301         .num_chipselect = 1,
2302 };
2303
2304 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2305         .name           = "mcspi4",
2306         .class          = &omap44xx_mcspi_hwmod_class,
2307         .clkdm_name     = "l4_per_clkdm",
2308         .mpu_irqs       = omap44xx_mcspi4_irqs,
2309         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2310         .main_clk       = "func_48m_fclk",
2311         .prcm = {
2312                 .omap4 = {
2313                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2314                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2315                         .modulemode   = MODULEMODE_SWCTRL,
2316                 },
2317         },
2318         .dev_attr       = &mcspi4_dev_attr,
2319 };
2320
2321 /*
2322  * 'mmc' class
2323  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2324  */
2325
2326 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2327         .rev_offs       = 0x0000,
2328         .sysc_offs      = 0x0010,
2329         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2330                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2331                            SYSC_HAS_SOFTRESET),
2332         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2333                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2334                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2335         .sysc_fields    = &omap_hwmod_sysc_type2,
2336 };
2337
2338 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2339         .name   = "mmc",
2340         .sysc   = &omap44xx_mmc_sysc,
2341 };
2342
2343 /* mmc1 */
2344 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2345         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2346         { .irq = -1 }
2347 };
2348
2349 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2350         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2351         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2352         { .dma_req = -1 }
2353 };
2354
2355 /* mmc1 dev_attr */
2356 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2357         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2358 };
2359
2360 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2361         .name           = "mmc1",
2362         .class          = &omap44xx_mmc_hwmod_class,
2363         .clkdm_name     = "l3_init_clkdm",
2364         .mpu_irqs       = omap44xx_mmc1_irqs,
2365         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2366         .main_clk       = "hsmmc1_fclk",
2367         .prcm = {
2368                 .omap4 = {
2369                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2370                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2371                         .modulemode   = MODULEMODE_SWCTRL,
2372                 },
2373         },
2374         .dev_attr       = &mmc1_dev_attr,
2375 };
2376
2377 /* mmc2 */
2378 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2379         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2380         { .irq = -1 }
2381 };
2382
2383 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2384         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2385         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2386         { .dma_req = -1 }
2387 };
2388
2389 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2390         .name           = "mmc2",
2391         .class          = &omap44xx_mmc_hwmod_class,
2392         .clkdm_name     = "l3_init_clkdm",
2393         .mpu_irqs       = omap44xx_mmc2_irqs,
2394         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2395         .main_clk       = "hsmmc2_fclk",
2396         .prcm = {
2397                 .omap4 = {
2398                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2399                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2400                         .modulemode   = MODULEMODE_SWCTRL,
2401                 },
2402         },
2403 };
2404
2405 /* mmc3 */
2406 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2407         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2408         { .irq = -1 }
2409 };
2410
2411 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2412         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2413         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2414         { .dma_req = -1 }
2415 };
2416
2417 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2418         .name           = "mmc3",
2419         .class          = &omap44xx_mmc_hwmod_class,
2420         .clkdm_name     = "l4_per_clkdm",
2421         .mpu_irqs       = omap44xx_mmc3_irqs,
2422         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2423         .main_clk       = "func_48m_fclk",
2424         .prcm = {
2425                 .omap4 = {
2426                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2427                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2428                         .modulemode   = MODULEMODE_SWCTRL,
2429                 },
2430         },
2431 };
2432
2433 /* mmc4 */
2434 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2435         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2436         { .irq = -1 }
2437 };
2438
2439 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2440         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2441         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2442         { .dma_req = -1 }
2443 };
2444
2445 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2446         .name           = "mmc4",
2447         .class          = &omap44xx_mmc_hwmod_class,
2448         .clkdm_name     = "l4_per_clkdm",
2449         .mpu_irqs       = omap44xx_mmc4_irqs,
2450         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2451         .main_clk       = "func_48m_fclk",
2452         .prcm = {
2453                 .omap4 = {
2454                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2455                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2456                         .modulemode   = MODULEMODE_SWCTRL,
2457                 },
2458         },
2459 };
2460
2461 /* mmc5 */
2462 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2463         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2464         { .irq = -1 }
2465 };
2466
2467 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2468         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2469         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2470         { .dma_req = -1 }
2471 };
2472
2473 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2474         .name           = "mmc5",
2475         .class          = &omap44xx_mmc_hwmod_class,
2476         .clkdm_name     = "l4_per_clkdm",
2477         .mpu_irqs       = omap44xx_mmc5_irqs,
2478         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2479         .main_clk       = "func_48m_fclk",
2480         .prcm = {
2481                 .omap4 = {
2482                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2483                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2484                         .modulemode   = MODULEMODE_SWCTRL,
2485                 },
2486         },
2487 };
2488
2489 /*
2490  * 'mmu' class
2491  * The memory management unit performs virtual to physical address translation
2492  * for its requestors.
2493  */
2494
2495 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2496         .rev_offs       = 0x000,
2497         .sysc_offs      = 0x010,
2498         .syss_offs      = 0x014,
2499         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2500                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2501         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2502         .sysc_fields    = &omap_hwmod_sysc_type1,
2503 };
2504
2505 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2506         .name = "mmu",
2507         .sysc = &mmu_sysc,
2508 };
2509
2510 /* mmu ipu */
2511
2512 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2513         .da_start       = 0x0,
2514         .da_end         = 0xfffff000,
2515         .nr_tlb_entries = 32,
2516 };
2517
2518 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2519 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2520         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2521         { .irq = -1 }
2522 };
2523
2524 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2525         { .name = "mmu_cache", .rst_shift = 2 },
2526 };
2527
2528 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2529         {
2530                 .pa_start       = 0x55082000,
2531                 .pa_end         = 0x550820ff,
2532                 .flags          = ADDR_TYPE_RT,
2533         },
2534         { }
2535 };
2536
2537 /* l3_main_2 -> mmu_ipu */
2538 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2539         .master         = &omap44xx_l3_main_2_hwmod,
2540         .slave          = &omap44xx_mmu_ipu_hwmod,
2541         .clk            = "l3_div_ck",
2542         .addr           = omap44xx_mmu_ipu_addrs,
2543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2544 };
2545
2546 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2547         .name           = "mmu_ipu",
2548         .class          = &omap44xx_mmu_hwmod_class,
2549         .clkdm_name     = "ducati_clkdm",
2550         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2551         .rst_lines      = omap44xx_mmu_ipu_resets,
2552         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2553         .main_clk       = "ducati_clk_mux_ck",
2554         .prcm = {
2555                 .omap4 = {
2556                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2557                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2558                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2559                         .modulemode   = MODULEMODE_HWCTRL,
2560                 },
2561         },
2562         .dev_attr       = &mmu_ipu_dev_attr,
2563 };
2564
2565 /* mmu dsp */
2566
2567 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2568         .da_start       = 0x0,
2569         .da_end         = 0xfffff000,
2570         .nr_tlb_entries = 32,
2571 };
2572
2573 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2574 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2575         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2576         { .irq = -1 }
2577 };
2578
2579 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2580         { .name = "mmu_cache", .rst_shift = 1 },
2581 };
2582
2583 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2584         {
2585                 .pa_start       = 0x4a066000,
2586                 .pa_end         = 0x4a0660ff,
2587                 .flags          = ADDR_TYPE_RT,
2588         },
2589         { }
2590 };
2591
2592 /* l4_cfg -> dsp */
2593 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2594         .master         = &omap44xx_l4_cfg_hwmod,
2595         .slave          = &omap44xx_mmu_dsp_hwmod,
2596         .clk            = "l4_div_ck",
2597         .addr           = omap44xx_mmu_dsp_addrs,
2598         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2599 };
2600
2601 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2602         .name           = "mmu_dsp",
2603         .class          = &omap44xx_mmu_hwmod_class,
2604         .clkdm_name     = "tesla_clkdm",
2605         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2606         .rst_lines      = omap44xx_mmu_dsp_resets,
2607         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2608         .main_clk       = "dpll_iva_m4x2_ck",
2609         .prcm = {
2610                 .omap4 = {
2611                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2612                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2613                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2614                         .modulemode   = MODULEMODE_HWCTRL,
2615                 },
2616         },
2617         .dev_attr       = &mmu_dsp_dev_attr,
2618 };
2619
2620 /*
2621  * 'mpu' class
2622  * mpu sub-system
2623  */
2624
2625 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2626         .name   = "mpu",
2627 };
2628
2629 /* mpu */
2630 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2631         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2632         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2633         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2634         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2635         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2636         { .irq = -1 }
2637 };
2638
2639 static struct omap_hwmod omap44xx_mpu_hwmod = {
2640         .name           = "mpu",
2641         .class          = &omap44xx_mpu_hwmod_class,
2642         .clkdm_name     = "mpuss_clkdm",
2643         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2644         .mpu_irqs       = omap44xx_mpu_irqs,
2645         .main_clk       = "dpll_mpu_m2_ck",
2646         .prcm = {
2647                 .omap4 = {
2648                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2649                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2650                 },
2651         },
2652 };
2653
2654 /*
2655  * 'ocmc_ram' class
2656  * top-level core on-chip ram
2657  */
2658
2659 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2660         .name   = "ocmc_ram",
2661 };
2662
2663 /* ocmc_ram */
2664 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2665         .name           = "ocmc_ram",
2666         .class          = &omap44xx_ocmc_ram_hwmod_class,
2667         .clkdm_name     = "l3_2_clkdm",
2668         .prcm = {
2669                 .omap4 = {
2670                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2671                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2672                 },
2673         },
2674 };
2675
2676 /*
2677  * 'ocp2scp' class
2678  * bridge to transform ocp interface protocol to scp (serial control port)
2679  * protocol
2680  */
2681
2682 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2683         .rev_offs       = 0x0000,
2684         .sysc_offs      = 0x0010,
2685         .syss_offs      = 0x0014,
2686         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2687                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2688         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2689         .sysc_fields    = &omap_hwmod_sysc_type1,
2690 };
2691
2692 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2693         .name   = "ocp2scp",
2694         .sysc   = &omap44xx_ocp2scp_sysc,
2695 };
2696
2697 /* ocp2scp dev_attr */
2698 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2699         {
2700                 .name           = "usb_phy",
2701                 .start          = 0x4a0ad080,
2702                 .end            = 0x4a0ae000,
2703                 .flags          = IORESOURCE_MEM,
2704         },
2705         { }
2706 };
2707
2708 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2709         {
2710                 .drv_name       = "omap-usb2",
2711                 .res            = omap44xx_usb_phy_and_pll_addrs,
2712         },
2713         { }
2714 };
2715
2716 /* ocp2scp_usb_phy */
2717 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2718         .name           = "ocp2scp_usb_phy",
2719         .class          = &omap44xx_ocp2scp_hwmod_class,
2720         .clkdm_name     = "l3_init_clkdm",
2721         .main_clk       = "func_48m_fclk",
2722         .prcm = {
2723                 .omap4 = {
2724                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2725                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2726                         .modulemode   = MODULEMODE_HWCTRL,
2727                 },
2728         },
2729         .dev_attr       = ocp2scp_dev_attr,
2730 };
2731
2732 /*
2733  * 'prcm' class
2734  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2735  * + clock manager 1 (in always on power domain) + local prm in mpu
2736  */
2737
2738 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2739         .name   = "prcm",
2740 };
2741
2742 /* prcm_mpu */
2743 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2744         .name           = "prcm_mpu",
2745         .class          = &omap44xx_prcm_hwmod_class,
2746         .clkdm_name     = "l4_wkup_clkdm",
2747         .flags          = HWMOD_NO_IDLEST,
2748         .prcm = {
2749                 .omap4 = {
2750                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2751                 },
2752         },
2753 };
2754
2755 /* cm_core_aon */
2756 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2757         .name           = "cm_core_aon",
2758         .class          = &omap44xx_prcm_hwmod_class,
2759         .flags          = HWMOD_NO_IDLEST,
2760         .prcm = {
2761                 .omap4 = {
2762                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2763                 },
2764         },
2765 };
2766
2767 /* cm_core */
2768 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2769         .name           = "cm_core",
2770         .class          = &omap44xx_prcm_hwmod_class,
2771         .flags          = HWMOD_NO_IDLEST,
2772         .prcm = {
2773                 .omap4 = {
2774                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2775                 },
2776         },
2777 };
2778
2779 /* prm */
2780 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2781         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2782         { .irq = -1 }
2783 };
2784
2785 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2786         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2787         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2788 };
2789
2790 static struct omap_hwmod omap44xx_prm_hwmod = {
2791         .name           = "prm",
2792         .class          = &omap44xx_prcm_hwmod_class,
2793         .mpu_irqs       = omap44xx_prm_irqs,
2794         .rst_lines      = omap44xx_prm_resets,
2795         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2796 };
2797
2798 /*
2799  * 'scrm' class
2800  * system clock and reset manager
2801  */
2802
2803 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2804         .name   = "scrm",
2805 };
2806
2807 /* scrm */
2808 static struct omap_hwmod omap44xx_scrm_hwmod = {
2809         .name           = "scrm",
2810         .class          = &omap44xx_scrm_hwmod_class,
2811         .clkdm_name     = "l4_wkup_clkdm",
2812         .prcm = {
2813                 .omap4 = {
2814                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2815                 },
2816         },
2817 };
2818
2819 /*
2820  * 'sl2if' class
2821  * shared level 2 memory interface
2822  */
2823
2824 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2825         .name   = "sl2if",
2826 };
2827
2828 /* sl2if */
2829 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2830         .name           = "sl2if",
2831         .class          = &omap44xx_sl2if_hwmod_class,
2832         .clkdm_name     = "ivahd_clkdm",
2833         .prcm = {
2834                 .omap4 = {
2835                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2836                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2837                         .modulemode   = MODULEMODE_HWCTRL,
2838                 },
2839         },
2840 };
2841
2842 /*
2843  * 'slimbus' class
2844  * bidirectional, multi-drop, multi-channel two-line serial interface between
2845  * the device and external components
2846  */
2847
2848 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2849         .rev_offs       = 0x0000,
2850         .sysc_offs      = 0x0010,
2851         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2852                            SYSC_HAS_SOFTRESET),
2853         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2854                            SIDLE_SMART_WKUP),
2855         .sysc_fields    = &omap_hwmod_sysc_type2,
2856 };
2857
2858 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2859         .name   = "slimbus",
2860         .sysc   = &omap44xx_slimbus_sysc,
2861 };
2862
2863 /* slimbus1 */
2864 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2865         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2866         { .irq = -1 }
2867 };
2868
2869 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2870         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2871         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2872         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2873         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2874         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2875         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2876         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2877         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2878         { .dma_req = -1 }
2879 };
2880
2881 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2882         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2883         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2884         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2885         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2886 };
2887
2888 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2889         .name           = "slimbus1",
2890         .class          = &omap44xx_slimbus_hwmod_class,
2891         .clkdm_name     = "abe_clkdm",
2892         .mpu_irqs       = omap44xx_slimbus1_irqs,
2893         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2894         .prcm = {
2895                 .omap4 = {
2896                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2897                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2898                         .modulemode   = MODULEMODE_SWCTRL,
2899                 },
2900         },
2901         .opt_clks       = slimbus1_opt_clks,
2902         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2903 };
2904
2905 /* slimbus2 */
2906 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2907         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2908         { .irq = -1 }
2909 };
2910
2911 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2912         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2913         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2914         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2915         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2916         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2917         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2918         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2919         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2920         { .dma_req = -1 }
2921 };
2922
2923 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2924         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2925         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2926         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2927 };
2928
2929 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2930         .name           = "slimbus2",
2931         .class          = &omap44xx_slimbus_hwmod_class,
2932         .clkdm_name     = "l4_per_clkdm",
2933         .mpu_irqs       = omap44xx_slimbus2_irqs,
2934         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2935         .prcm = {
2936                 .omap4 = {
2937                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2938                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2939                         .modulemode   = MODULEMODE_SWCTRL,
2940                 },
2941         },
2942         .opt_clks       = slimbus2_opt_clks,
2943         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2944 };
2945
2946 /*
2947  * 'smartreflex' class
2948  * smartreflex module (monitor silicon performance and outputs a measure of
2949  * performance error)
2950  */
2951
2952 /* The IP is not compliant to type1 / type2 scheme */
2953 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2954         .sidle_shift    = 24,
2955         .enwkup_shift   = 26,
2956 };
2957
2958 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2959         .sysc_offs      = 0x0038,
2960         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2961         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2962                            SIDLE_SMART_WKUP),
2963         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2964 };
2965
2966 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2967         .name   = "smartreflex",
2968         .sysc   = &omap44xx_smartreflex_sysc,
2969         .rev    = 2,
2970 };
2971
2972 /* smartreflex_core */
2973 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2974         .sensor_voltdm_name   = "core",
2975 };
2976
2977 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2978         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2979         { .irq = -1 }
2980 };
2981
2982 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2983         .name           = "smartreflex_core",
2984         .class          = &omap44xx_smartreflex_hwmod_class,
2985         .clkdm_name     = "l4_ao_clkdm",
2986         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2987
2988         .main_clk       = "smartreflex_core_fck",
2989         .prcm = {
2990                 .omap4 = {
2991                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2992                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2993                         .modulemode   = MODULEMODE_SWCTRL,
2994                 },
2995         },
2996         .dev_attr       = &smartreflex_core_dev_attr,
2997 };
2998
2999 /* smartreflex_iva */
3000 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3001         .sensor_voltdm_name     = "iva",
3002 };
3003
3004 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3005         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3006         { .irq = -1 }
3007 };
3008
3009 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3010         .name           = "smartreflex_iva",
3011         .class          = &omap44xx_smartreflex_hwmod_class,
3012         .clkdm_name     = "l4_ao_clkdm",
3013         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3014         .main_clk       = "smartreflex_iva_fck",
3015         .prcm = {
3016                 .omap4 = {
3017                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3018                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3019                         .modulemode   = MODULEMODE_SWCTRL,
3020                 },
3021         },
3022         .dev_attr       = &smartreflex_iva_dev_attr,
3023 };
3024
3025 /* smartreflex_mpu */
3026 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3027         .sensor_voltdm_name     = "mpu",
3028 };
3029
3030 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3031         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3032         { .irq = -1 }
3033 };
3034
3035 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3036         .name           = "smartreflex_mpu",
3037         .class          = &omap44xx_smartreflex_hwmod_class,
3038         .clkdm_name     = "l4_ao_clkdm",
3039         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3040         .main_clk       = "smartreflex_mpu_fck",
3041         .prcm = {
3042                 .omap4 = {
3043                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3044                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3045                         .modulemode   = MODULEMODE_SWCTRL,
3046                 },
3047         },
3048         .dev_attr       = &smartreflex_mpu_dev_attr,
3049 };
3050
3051 /*
3052  * 'spinlock' class
3053  * spinlock provides hardware assistance for synchronizing the processes
3054  * running on multiple processors
3055  */
3056
3057 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3058         .rev_offs       = 0x0000,
3059         .sysc_offs      = 0x0010,
3060         .syss_offs      = 0x0014,
3061         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3062                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3063                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3064         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3065                            SIDLE_SMART_WKUP),
3066         .sysc_fields    = &omap_hwmod_sysc_type1,
3067 };
3068
3069 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3070         .name   = "spinlock",
3071         .sysc   = &omap44xx_spinlock_sysc,
3072 };
3073
3074 /* spinlock */
3075 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3076         .name           = "spinlock",
3077         .class          = &omap44xx_spinlock_hwmod_class,
3078         .clkdm_name     = "l4_cfg_clkdm",
3079         .prcm = {
3080                 .omap4 = {
3081                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3082                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3083                 },
3084         },
3085 };
3086
3087 /*
3088  * 'timer' class
3089  * general purpose timer module with accurate 1ms tick
3090  * This class contains several variants: ['timer_1ms', 'timer']
3091  */
3092
3093 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3094         .rev_offs       = 0x0000,
3095         .sysc_offs      = 0x0010,
3096         .syss_offs      = 0x0014,
3097         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3098                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3099                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3100                            SYSS_HAS_RESET_STATUS),
3101         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3102         .clockact       = CLOCKACT_TEST_ICLK,
3103         .sysc_fields    = &omap_hwmod_sysc_type1,
3104 };
3105
3106 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3107         .name   = "timer",
3108         .sysc   = &omap44xx_timer_1ms_sysc,
3109 };
3110
3111 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3112         .rev_offs       = 0x0000,
3113         .sysc_offs      = 0x0010,
3114         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3115                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3116         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3117                            SIDLE_SMART_WKUP),
3118         .sysc_fields    = &omap_hwmod_sysc_type2,
3119 };
3120
3121 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3122         .name   = "timer",
3123         .sysc   = &omap44xx_timer_sysc,
3124 };
3125
3126 /* always-on timers dev attribute */
3127 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3128         .timer_capability       = OMAP_TIMER_ALWON,
3129 };
3130
3131 /* pwm timers dev attribute */
3132 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3133         .timer_capability       = OMAP_TIMER_HAS_PWM,
3134 };
3135
3136 /* timers with DSP interrupt dev attribute */
3137 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3138         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3139 };
3140
3141 /* pwm timers with DSP interrupt dev attribute */
3142 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3143         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3144 };
3145
3146 /* timer1 */
3147 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3148         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3149         { .irq = -1 }
3150 };
3151
3152 static struct omap_hwmod omap44xx_timer1_hwmod = {
3153         .name           = "timer1",
3154         .class          = &omap44xx_timer_1ms_hwmod_class,
3155         .clkdm_name     = "l4_wkup_clkdm",
3156         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3157         .mpu_irqs       = omap44xx_timer1_irqs,
3158         .main_clk       = "dmt1_clk_mux",
3159         .prcm = {
3160                 .omap4 = {
3161                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3162                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3163                         .modulemode   = MODULEMODE_SWCTRL,
3164                 },
3165         },
3166         .dev_attr       = &capability_alwon_dev_attr,
3167 };
3168
3169 /* timer2 */
3170 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3171         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3172         { .irq = -1 }
3173 };
3174
3175 static struct omap_hwmod omap44xx_timer2_hwmod = {
3176         .name           = "timer2",
3177         .class          = &omap44xx_timer_1ms_hwmod_class,
3178         .clkdm_name     = "l4_per_clkdm",
3179         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3180         .mpu_irqs       = omap44xx_timer2_irqs,
3181         .main_clk       = "cm2_dm2_mux",
3182         .prcm = {
3183                 .omap4 = {
3184                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3185                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3186                         .modulemode   = MODULEMODE_SWCTRL,
3187                 },
3188         },
3189 };
3190
3191 /* timer3 */
3192 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3193         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3194         { .irq = -1 }
3195 };
3196
3197 static struct omap_hwmod omap44xx_timer3_hwmod = {
3198         .name           = "timer3",
3199         .class          = &omap44xx_timer_hwmod_class,
3200         .clkdm_name     = "l4_per_clkdm",
3201         .mpu_irqs       = omap44xx_timer3_irqs,
3202         .main_clk       = "cm2_dm3_mux",
3203         .prcm = {
3204                 .omap4 = {
3205                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3206                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3207                         .modulemode   = MODULEMODE_SWCTRL,
3208                 },
3209         },
3210 };
3211
3212 /* timer4 */
3213 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3214         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3215         { .irq = -1 }
3216 };
3217
3218 static struct omap_hwmod omap44xx_timer4_hwmod = {
3219         .name           = "timer4",
3220         .class          = &omap44xx_timer_hwmod_class,
3221         .clkdm_name     = "l4_per_clkdm",
3222         .mpu_irqs       = omap44xx_timer4_irqs,
3223         .main_clk       = "cm2_dm4_mux",
3224         .prcm = {
3225                 .omap4 = {
3226                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3227                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3228                         .modulemode   = MODULEMODE_SWCTRL,
3229                 },
3230         },
3231 };
3232
3233 /* timer5 */
3234 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3235         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3236         { .irq = -1 }
3237 };
3238
3239 static struct omap_hwmod omap44xx_timer5_hwmod = {
3240         .name           = "timer5",
3241         .class          = &omap44xx_timer_hwmod_class,
3242         .clkdm_name     = "abe_clkdm",
3243         .mpu_irqs       = omap44xx_timer5_irqs,
3244         .main_clk       = "timer5_sync_mux",
3245         .prcm = {
3246                 .omap4 = {
3247                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3248                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3249                         .modulemode   = MODULEMODE_SWCTRL,
3250                 },
3251         },
3252         .dev_attr       = &capability_dsp_dev_attr,
3253 };
3254
3255 /* timer6 */
3256 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3257         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3258         { .irq = -1 }
3259 };
3260
3261 static struct omap_hwmod omap44xx_timer6_hwmod = {
3262         .name           = "timer6",
3263         .class          = &omap44xx_timer_hwmod_class,
3264         .clkdm_name     = "abe_clkdm",
3265         .mpu_irqs       = omap44xx_timer6_irqs,
3266         .main_clk       = "timer6_sync_mux",
3267         .prcm = {
3268                 .omap4 = {
3269                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3270                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3271                         .modulemode   = MODULEMODE_SWCTRL,
3272                 },
3273         },
3274         .dev_attr       = &capability_dsp_dev_attr,
3275 };
3276
3277 /* timer7 */
3278 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3279         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3280         { .irq = -1 }
3281 };
3282
3283 static struct omap_hwmod omap44xx_timer7_hwmod = {
3284         .name           = "timer7",
3285         .class          = &omap44xx_timer_hwmod_class,
3286         .clkdm_name     = "abe_clkdm",
3287         .mpu_irqs       = omap44xx_timer7_irqs,
3288         .main_clk       = "timer7_sync_mux",
3289         .prcm = {
3290                 .omap4 = {
3291                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3292                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3293                         .modulemode   = MODULEMODE_SWCTRL,
3294                 },
3295         },
3296         .dev_attr       = &capability_dsp_dev_attr,
3297 };
3298
3299 /* timer8 */
3300 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3301         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3302         { .irq = -1 }
3303 };
3304
3305 static struct omap_hwmod omap44xx_timer8_hwmod = {
3306         .name           = "timer8",
3307         .class          = &omap44xx_timer_hwmod_class,
3308         .clkdm_name     = "abe_clkdm",
3309         .mpu_irqs       = omap44xx_timer8_irqs,
3310         .main_clk       = "timer8_sync_mux",
3311         .prcm = {
3312                 .omap4 = {
3313                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3314                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3315                         .modulemode   = MODULEMODE_SWCTRL,
3316                 },
3317         },
3318         .dev_attr       = &capability_dsp_pwm_dev_attr,
3319 };
3320
3321 /* timer9 */
3322 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3323         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3324         { .irq = -1 }
3325 };
3326
3327 static struct omap_hwmod omap44xx_timer9_hwmod = {
3328         .name           = "timer9",
3329         .class          = &omap44xx_timer_hwmod_class,
3330         .clkdm_name     = "l4_per_clkdm",
3331         .mpu_irqs       = omap44xx_timer9_irqs,
3332         .main_clk       = "cm2_dm9_mux",
3333         .prcm = {
3334                 .omap4 = {
3335                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3336                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3337                         .modulemode   = MODULEMODE_SWCTRL,
3338                 },
3339         },
3340         .dev_attr       = &capability_pwm_dev_attr,
3341 };
3342
3343 /* timer10 */
3344 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3345         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3346         { .irq = -1 }
3347 };
3348
3349 static struct omap_hwmod omap44xx_timer10_hwmod = {
3350         .name           = "timer10",
3351         .class          = &omap44xx_timer_1ms_hwmod_class,
3352         .clkdm_name     = "l4_per_clkdm",
3353         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3354         .mpu_irqs       = omap44xx_timer10_irqs,
3355         .main_clk       = "cm2_dm10_mux",
3356         .prcm = {
3357                 .omap4 = {
3358                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3359                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3360                         .modulemode   = MODULEMODE_SWCTRL,
3361                 },
3362         },
3363         .dev_attr       = &capability_pwm_dev_attr,
3364 };
3365
3366 /* timer11 */
3367 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3368         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3369         { .irq = -1 }
3370 };
3371
3372 static struct omap_hwmod omap44xx_timer11_hwmod = {
3373         .name           = "timer11",
3374         .class          = &omap44xx_timer_hwmod_class,
3375         .clkdm_name     = "l4_per_clkdm",
3376         .mpu_irqs       = omap44xx_timer11_irqs,
3377         .main_clk       = "cm2_dm11_mux",
3378         .prcm = {
3379                 .omap4 = {
3380                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3381                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3382                         .modulemode   = MODULEMODE_SWCTRL,
3383                 },
3384         },
3385         .dev_attr       = &capability_pwm_dev_attr,
3386 };
3387
3388 /*
3389  * 'uart' class
3390  * universal asynchronous receiver/transmitter (uart)
3391  */
3392
3393 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3394         .rev_offs       = 0x0050,
3395         .sysc_offs      = 0x0054,
3396         .syss_offs      = 0x0058,
3397         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3398                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3399                            SYSS_HAS_RESET_STATUS),
3400         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3401                            SIDLE_SMART_WKUP),
3402         .sysc_fields    = &omap_hwmod_sysc_type1,
3403 };
3404
3405 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3406         .name   = "uart",
3407         .sysc   = &omap44xx_uart_sysc,
3408 };
3409
3410 /* uart1 */
3411 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3412         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3413         { .irq = -1 }
3414 };
3415
3416 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3417         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3418         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3419         { .dma_req = -1 }
3420 };
3421
3422 static struct omap_hwmod omap44xx_uart1_hwmod = {
3423         .name           = "uart1",
3424         .class          = &omap44xx_uart_hwmod_class,
3425         .clkdm_name     = "l4_per_clkdm",
3426         .mpu_irqs       = omap44xx_uart1_irqs,
3427         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3428         .main_clk       = "func_48m_fclk",
3429         .prcm = {
3430                 .omap4 = {
3431                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3432                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3433                         .modulemode   = MODULEMODE_SWCTRL,
3434                 },
3435         },
3436 };
3437
3438 /* uart2 */
3439 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3440         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3441         { .irq = -1 }
3442 };
3443
3444 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3445         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3446         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3447         { .dma_req = -1 }
3448 };
3449
3450 static struct omap_hwmod omap44xx_uart2_hwmod = {
3451         .name           = "uart2",
3452         .class          = &omap44xx_uart_hwmod_class,
3453         .clkdm_name     = "l4_per_clkdm",
3454         .mpu_irqs       = omap44xx_uart2_irqs,
3455         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3456         .main_clk       = "func_48m_fclk",
3457         .prcm = {
3458                 .omap4 = {
3459                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3460                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3461                         .modulemode   = MODULEMODE_SWCTRL,
3462                 },
3463         },
3464 };
3465
3466 /* uart3 */
3467 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3468         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3469         { .irq = -1 }
3470 };
3471
3472 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3473         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3474         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3475         { .dma_req = -1 }
3476 };
3477
3478 static struct omap_hwmod omap44xx_uart3_hwmod = {
3479         .name           = "uart3",
3480         .class          = &omap44xx_uart_hwmod_class,
3481         .clkdm_name     = "l4_per_clkdm",
3482         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3483         .mpu_irqs       = omap44xx_uart3_irqs,
3484         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3485         .main_clk       = "func_48m_fclk",
3486         .prcm = {
3487                 .omap4 = {
3488                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3489                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3490                         .modulemode   = MODULEMODE_SWCTRL,
3491                 },
3492         },
3493 };
3494
3495 /* uart4 */
3496 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3497         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3498         { .irq = -1 }
3499 };
3500
3501 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3502         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3503         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3504         { .dma_req = -1 }
3505 };
3506
3507 static struct omap_hwmod omap44xx_uart4_hwmod = {
3508         .name           = "uart4",
3509         .class          = &omap44xx_uart_hwmod_class,
3510         .clkdm_name     = "l4_per_clkdm",
3511         .mpu_irqs       = omap44xx_uart4_irqs,
3512         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3513         .main_clk       = "func_48m_fclk",
3514         .prcm = {
3515                 .omap4 = {
3516                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3517                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3518                         .modulemode   = MODULEMODE_SWCTRL,
3519                 },
3520         },
3521 };
3522
3523 /*
3524  * 'usb_host_fs' class
3525  * full-speed usb host controller
3526  */
3527
3528 /* The IP is not compliant to type1 / type2 scheme */
3529 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3530         .midle_shift    = 4,
3531         .sidle_shift    = 2,
3532         .srst_shift     = 1,
3533 };
3534
3535 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3536         .rev_offs       = 0x0000,
3537         .sysc_offs      = 0x0210,
3538         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3539                            SYSC_HAS_SOFTRESET),
3540         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3541                            SIDLE_SMART_WKUP),
3542         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3543 };
3544
3545 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3546         .name   = "usb_host_fs",
3547         .sysc   = &omap44xx_usb_host_fs_sysc,
3548 };
3549
3550 /* usb_host_fs */
3551 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3552         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3553         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3554         { .irq = -1 }
3555 };
3556
3557 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3558         .name           = "usb_host_fs",
3559         .class          = &omap44xx_usb_host_fs_hwmod_class,
3560         .clkdm_name     = "l3_init_clkdm",
3561         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3562         .main_clk       = "usb_host_fs_fck",
3563         .prcm = {
3564                 .omap4 = {
3565                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3566                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3567                         .modulemode   = MODULEMODE_SWCTRL,
3568                 },
3569         },
3570 };
3571
3572 /*
3573  * 'usb_host_hs' class
3574  * high-speed multi-port usb host controller
3575  */
3576
3577 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3578         .rev_offs       = 0x0000,
3579         .sysc_offs      = 0x0010,
3580         .syss_offs      = 0x0014,
3581         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3582                            SYSC_HAS_SOFTRESET),
3583         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3584                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3585                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3586         .sysc_fields    = &omap_hwmod_sysc_type2,
3587 };
3588
3589 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3590         .name   = "usb_host_hs",
3591         .sysc   = &omap44xx_usb_host_hs_sysc,
3592 };
3593
3594 /* usb_host_hs */
3595 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3596         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3597         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3598         { .irq = -1 }
3599 };
3600
3601 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3602         .name           = "usb_host_hs",
3603         .class          = &omap44xx_usb_host_hs_hwmod_class,
3604         .clkdm_name     = "l3_init_clkdm",
3605         .main_clk       = "usb_host_hs_fck",
3606         .prcm = {
3607                 .omap4 = {
3608                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3609                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3610                         .modulemode   = MODULEMODE_SWCTRL,
3611                 },
3612         },
3613         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3614
3615         /*
3616          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3617          * id: i660
3618          *
3619          * Description:
3620          * In the following configuration :
3621          * - USBHOST module is set to smart-idle mode
3622          * - PRCM asserts idle_req to the USBHOST module ( This typically
3623          *   happens when the system is going to a low power mode : all ports
3624          *   have been suspended, the master part of the USBHOST module has
3625          *   entered the standby state, and SW has cut the functional clocks)
3626          * - an USBHOST interrupt occurs before the module is able to answer
3627          *   idle_ack, typically a remote wakeup IRQ.
3628          * Then the USB HOST module will enter a deadlock situation where it
3629          * is no more accessible nor functional.
3630          *
3631          * Workaround:
3632          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3633          */
3634
3635         /*
3636          * Errata: USB host EHCI may stall when entering smart-standby mode
3637          * Id: i571
3638          *
3639          * Description:
3640          * When the USBHOST module is set to smart-standby mode, and when it is
3641          * ready to enter the standby state (i.e. all ports are suspended and
3642          * all attached devices are in suspend mode), then it can wrongly assert
3643          * the Mstandby signal too early while there are still some residual OCP
3644          * transactions ongoing. If this condition occurs, the internal state
3645          * machine may go to an undefined state and the USB link may be stuck
3646          * upon the next resume.
3647          *
3648          * Workaround:
3649          * Don't use smart standby; use only force standby,
3650          * hence HWMOD_SWSUP_MSTANDBY
3651          */
3652
3653         /*
3654          * During system boot; If the hwmod framework resets the module
3655          * the module will have smart idle settings; which can lead to deadlock
3656          * (above Errata Id:i660); so, dont reset the module during boot;
3657          * Use HWMOD_INIT_NO_RESET.
3658          */
3659
3660         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3661                           HWMOD_INIT_NO_RESET,
3662 };
3663
3664 /*
3665  * 'usb_otg_hs' class
3666  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3667  */
3668
3669 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3670         .rev_offs       = 0x0400,
3671         .sysc_offs      = 0x0404,
3672         .syss_offs      = 0x0408,
3673         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3674                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3675                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3676         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3677                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3678                            MSTANDBY_SMART),
3679         .sysc_fields    = &omap_hwmod_sysc_type1,
3680 };
3681
3682 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3683         .name   = "usb_otg_hs",
3684         .sysc   = &omap44xx_usb_otg_hs_sysc,
3685 };
3686
3687 /* usb_otg_hs */
3688 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3689         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3690         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3691         { .irq = -1 }
3692 };
3693
3694 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3695         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3696 };
3697
3698 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3699         .name           = "usb_otg_hs",
3700         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3701         .clkdm_name     = "l3_init_clkdm",
3702         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3703         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3704         .main_clk       = "usb_otg_hs_ick",
3705         .prcm = {
3706                 .omap4 = {
3707                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3708                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3709                         .modulemode   = MODULEMODE_HWCTRL,
3710                 },
3711         },
3712         .opt_clks       = usb_otg_hs_opt_clks,
3713         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3714 };
3715
3716 /*
3717  * 'usb_tll_hs' class
3718  * usb_tll_hs module is the adapter on the usb_host_hs ports
3719  */
3720
3721 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3722         .rev_offs       = 0x0000,
3723         .sysc_offs      = 0x0010,
3724         .syss_offs      = 0x0014,
3725         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3726                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3727                            SYSC_HAS_AUTOIDLE),
3728         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3729         .sysc_fields    = &omap_hwmod_sysc_type1,
3730 };
3731
3732 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3733         .name   = "usb_tll_hs",
3734         .sysc   = &omap44xx_usb_tll_hs_sysc,
3735 };
3736
3737 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3738         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3739         { .irq = -1 }
3740 };
3741
3742 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3743         .name           = "usb_tll_hs",
3744         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3745         .clkdm_name     = "l3_init_clkdm",
3746         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3747         .main_clk       = "usb_tll_hs_ick",
3748         .prcm = {
3749                 .omap4 = {
3750                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3751                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3752                         .modulemode   = MODULEMODE_HWCTRL,
3753                 },
3754         },
3755 };
3756
3757 /*
3758  * 'wd_timer' class
3759  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3760  * overflow condition
3761  */
3762
3763 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3764         .rev_offs       = 0x0000,
3765         .sysc_offs      = 0x0010,
3766         .syss_offs      = 0x0014,
3767         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3768                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3769         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3770                            SIDLE_SMART_WKUP),
3771         .sysc_fields    = &omap_hwmod_sysc_type1,
3772 };
3773
3774 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3775         .name           = "wd_timer",
3776         .sysc           = &omap44xx_wd_timer_sysc,
3777         .pre_shutdown   = &omap2_wd_timer_disable,
3778         .reset          = &omap2_wd_timer_reset,
3779 };
3780
3781 /* wd_timer2 */
3782 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3783         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3784         { .irq = -1 }
3785 };
3786
3787 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3788         .name           = "wd_timer2",
3789         .class          = &omap44xx_wd_timer_hwmod_class,
3790         .clkdm_name     = "l4_wkup_clkdm",
3791         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3792         .main_clk       = "sys_32k_ck",
3793         .prcm = {
3794                 .omap4 = {
3795                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3796                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3797                         .modulemode   = MODULEMODE_SWCTRL,
3798                 },
3799         },
3800 };
3801
3802 /* wd_timer3 */
3803 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3804         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3805         { .irq = -1 }
3806 };
3807
3808 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3809         .name           = "wd_timer3",
3810         .class          = &omap44xx_wd_timer_hwmod_class,
3811         .clkdm_name     = "abe_clkdm",
3812         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3813         .main_clk       = "sys_32k_ck",
3814         .prcm = {
3815                 .omap4 = {
3816                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3817                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3818                         .modulemode   = MODULEMODE_SWCTRL,
3819                 },
3820         },
3821 };
3822
3823
3824 /*
3825  * interfaces
3826  */
3827
3828 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3829         {
3830                 .pa_start       = 0x4a204000,
3831                 .pa_end         = 0x4a2040ff,
3832                 .flags          = ADDR_TYPE_RT
3833         },
3834         { }
3835 };
3836
3837 /* c2c -> c2c_target_fw */
3838 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3839         .master         = &omap44xx_c2c_hwmod,
3840         .slave          = &omap44xx_c2c_target_fw_hwmod,
3841         .clk            = "div_core_ck",
3842         .addr           = omap44xx_c2c_target_fw_addrs,
3843         .user           = OCP_USER_MPU,
3844 };
3845
3846 /* l4_cfg -> c2c_target_fw */
3847 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3848         .master         = &omap44xx_l4_cfg_hwmod,
3849         .slave          = &omap44xx_c2c_target_fw_hwmod,
3850         .clk            = "l4_div_ck",
3851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3852 };
3853
3854 /* l3_main_1 -> dmm */
3855 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3856         .master         = &omap44xx_l3_main_1_hwmod,
3857         .slave          = &omap44xx_dmm_hwmod,
3858         .clk            = "l3_div_ck",
3859         .user           = OCP_USER_SDMA,
3860 };
3861
3862 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3863         {
3864                 .pa_start       = 0x4e000000,
3865                 .pa_end         = 0x4e0007ff,
3866                 .flags          = ADDR_TYPE_RT
3867         },
3868         { }
3869 };
3870
3871 /* mpu -> dmm */
3872 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3873         .master         = &omap44xx_mpu_hwmod,
3874         .slave          = &omap44xx_dmm_hwmod,
3875         .clk            = "l3_div_ck",
3876         .addr           = omap44xx_dmm_addrs,
3877         .user           = OCP_USER_MPU,
3878 };
3879
3880 /* c2c -> emif_fw */
3881 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3882         .master         = &omap44xx_c2c_hwmod,
3883         .slave          = &omap44xx_emif_fw_hwmod,
3884         .clk            = "div_core_ck",
3885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3886 };
3887
3888 /* dmm -> emif_fw */
3889 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3890         .master         = &omap44xx_dmm_hwmod,
3891         .slave          = &omap44xx_emif_fw_hwmod,
3892         .clk            = "l3_div_ck",
3893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3894 };
3895
3896 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3897         {
3898                 .pa_start       = 0x4a20c000,
3899                 .pa_end         = 0x4a20c0ff,
3900                 .flags          = ADDR_TYPE_RT
3901         },
3902         { }
3903 };
3904
3905 /* l4_cfg -> emif_fw */
3906 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3907         .master         = &omap44xx_l4_cfg_hwmod,
3908         .slave          = &omap44xx_emif_fw_hwmod,
3909         .clk            = "l4_div_ck",
3910         .addr           = omap44xx_emif_fw_addrs,
3911         .user           = OCP_USER_MPU,
3912 };
3913
3914 /* iva -> l3_instr */
3915 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3916         .master         = &omap44xx_iva_hwmod,
3917         .slave          = &omap44xx_l3_instr_hwmod,
3918         .clk            = "l3_div_ck",
3919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3920 };
3921
3922 /* l3_main_3 -> l3_instr */
3923 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3924         .master         = &omap44xx_l3_main_3_hwmod,
3925         .slave          = &omap44xx_l3_instr_hwmod,
3926         .clk            = "l3_div_ck",
3927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3928 };
3929
3930 /* ocp_wp_noc -> l3_instr */
3931 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3932         .master         = &omap44xx_ocp_wp_noc_hwmod,
3933         .slave          = &omap44xx_l3_instr_hwmod,
3934         .clk            = "l3_div_ck",
3935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3936 };
3937
3938 /* dsp -> l3_main_1 */
3939 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3940         .master         = &omap44xx_dsp_hwmod,
3941         .slave          = &omap44xx_l3_main_1_hwmod,
3942         .clk            = "l3_div_ck",
3943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3944 };
3945
3946 /* dss -> l3_main_1 */
3947 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3948         .master         = &omap44xx_dss_hwmod,
3949         .slave          = &omap44xx_l3_main_1_hwmod,
3950         .clk            = "l3_div_ck",
3951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3952 };
3953
3954 /* l3_main_2 -> l3_main_1 */
3955 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3956         .master         = &omap44xx_l3_main_2_hwmod,
3957         .slave          = &omap44xx_l3_main_1_hwmod,
3958         .clk            = "l3_div_ck",
3959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3960 };
3961
3962 /* l4_cfg -> l3_main_1 */
3963 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3964         .master         = &omap44xx_l4_cfg_hwmod,
3965         .slave          = &omap44xx_l3_main_1_hwmod,
3966         .clk            = "l4_div_ck",
3967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3968 };
3969
3970 /* mmc1 -> l3_main_1 */
3971 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3972         .master         = &omap44xx_mmc1_hwmod,
3973         .slave          = &omap44xx_l3_main_1_hwmod,
3974         .clk            = "l3_div_ck",
3975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3976 };
3977
3978 /* mmc2 -> l3_main_1 */
3979 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3980         .master         = &omap44xx_mmc2_hwmod,
3981         .slave          = &omap44xx_l3_main_1_hwmod,
3982         .clk            = "l3_div_ck",
3983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3984 };
3985
3986 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3987         {
3988                 .pa_start       = 0x44000000,
3989                 .pa_end         = 0x44000fff,
3990                 .flags          = ADDR_TYPE_RT
3991         },
3992         { }
3993 };
3994
3995 /* mpu -> l3_main_1 */
3996 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3997         .master         = &omap44xx_mpu_hwmod,
3998         .slave          = &omap44xx_l3_main_1_hwmod,
3999         .clk            = "l3_div_ck",
4000         .addr           = omap44xx_l3_main_1_addrs,
4001         .user           = OCP_USER_MPU,
4002 };
4003
4004 /* c2c_target_fw -> l3_main_2 */
4005 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4006         .master         = &omap44xx_c2c_target_fw_hwmod,
4007         .slave          = &omap44xx_l3_main_2_hwmod,
4008         .clk            = "l3_div_ck",
4009         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4010 };
4011
4012 /* debugss -> l3_main_2 */
4013 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4014         .master         = &omap44xx_debugss_hwmod,
4015         .slave          = &omap44xx_l3_main_2_hwmod,
4016         .clk            = "dbgclk_mux_ck",
4017         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4018 };
4019
4020 /* dma_system -> l3_main_2 */
4021 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4022         .master         = &omap44xx_dma_system_hwmod,
4023         .slave          = &omap44xx_l3_main_2_hwmod,
4024         .clk            = "l3_div_ck",
4025         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4026 };
4027
4028 /* fdif -> l3_main_2 */
4029 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4030         .master         = &omap44xx_fdif_hwmod,
4031         .slave          = &omap44xx_l3_main_2_hwmod,
4032         .clk            = "l3_div_ck",
4033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4034 };
4035
4036 /* gpu -> l3_main_2 */
4037 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4038         .master         = &omap44xx_gpu_hwmod,
4039         .slave          = &omap44xx_l3_main_2_hwmod,
4040         .clk            = "l3_div_ck",
4041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4043
4044 /* hsi -> l3_main_2 */
4045 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4046         .master         = &omap44xx_hsi_hwmod,
4047         .slave          = &omap44xx_l3_main_2_hwmod,
4048         .clk            = "l3_div_ck",
4049         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4050 };
4051
4052 /* ipu -> l3_main_2 */
4053 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4054         .master         = &omap44xx_ipu_hwmod,
4055         .slave          = &omap44xx_l3_main_2_hwmod,
4056         .clk            = "l3_div_ck",
4057         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4058 };
4059
4060 /* iss -> l3_main_2 */
4061 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4062         .master         = &omap44xx_iss_hwmod,
4063         .slave          = &omap44xx_l3_main_2_hwmod,
4064         .clk            = "l3_div_ck",
4065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4066 };
4067
4068 /* iva -> l3_main_2 */
4069 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4070         .master         = &omap44xx_iva_hwmod,
4071         .slave          = &omap44xx_l3_main_2_hwmod,
4072         .clk            = "l3_div_ck",
4073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4074 };
4075
4076 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4077         {
4078                 .pa_start       = 0x44800000,
4079                 .pa_end         = 0x44801fff,
4080                 .flags          = ADDR_TYPE_RT
4081         },
4082         { }
4083 };
4084
4085 /* l3_main_1 -> l3_main_2 */
4086 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4087         .master         = &omap44xx_l3_main_1_hwmod,
4088         .slave          = &omap44xx_l3_main_2_hwmod,
4089         .clk            = "l3_div_ck",
4090         .addr           = omap44xx_l3_main_2_addrs,
4091         .user           = OCP_USER_MPU,
4092 };
4093
4094 /* l4_cfg -> l3_main_2 */
4095 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4096         .master         = &omap44xx_l4_cfg_hwmod,
4097         .slave          = &omap44xx_l3_main_2_hwmod,
4098         .clk            = "l4_div_ck",
4099         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4100 };
4101
4102 /* usb_host_fs -> l3_main_2 */
4103 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4104         .master         = &omap44xx_usb_host_fs_hwmod,
4105         .slave          = &omap44xx_l3_main_2_hwmod,
4106         .clk            = "l3_div_ck",
4107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4108 };
4109
4110 /* usb_host_hs -> l3_main_2 */
4111 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4112         .master         = &omap44xx_usb_host_hs_hwmod,
4113         .slave          = &omap44xx_l3_main_2_hwmod,
4114         .clk            = "l3_div_ck",
4115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4116 };
4117
4118 /* usb_otg_hs -> l3_main_2 */
4119 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4120         .master         = &omap44xx_usb_otg_hs_hwmod,
4121         .slave          = &omap44xx_l3_main_2_hwmod,
4122         .clk            = "l3_div_ck",
4123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4124 };
4125
4126 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4127         {
4128                 .pa_start       = 0x45000000,
4129                 .pa_end         = 0x45000fff,
4130                 .flags          = ADDR_TYPE_RT
4131         },
4132         { }
4133 };
4134
4135 /* l3_main_1 -> l3_main_3 */
4136 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4137         .master         = &omap44xx_l3_main_1_hwmod,
4138         .slave          = &omap44xx_l3_main_3_hwmod,
4139         .clk            = "l3_div_ck",
4140         .addr           = omap44xx_l3_main_3_addrs,
4141         .user           = OCP_USER_MPU,
4142 };
4143
4144 /* l3_main_2 -> l3_main_3 */
4145 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4146         .master         = &omap44xx_l3_main_2_hwmod,
4147         .slave          = &omap44xx_l3_main_3_hwmod,
4148         .clk            = "l3_div_ck",
4149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4150 };
4151
4152 /* l4_cfg -> l3_main_3 */
4153 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4154         .master         = &omap44xx_l4_cfg_hwmod,
4155         .slave          = &omap44xx_l3_main_3_hwmod,
4156         .clk            = "l4_div_ck",
4157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4158 };
4159
4160 /* aess -> l4_abe */
4161 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4162         .master         = &omap44xx_aess_hwmod,
4163         .slave          = &omap44xx_l4_abe_hwmod,
4164         .clk            = "ocp_abe_iclk",
4165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4166 };
4167
4168 /* dsp -> l4_abe */
4169 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4170         .master         = &omap44xx_dsp_hwmod,
4171         .slave          = &omap44xx_l4_abe_hwmod,
4172         .clk            = "ocp_abe_iclk",
4173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4174 };
4175
4176 /* l3_main_1 -> l4_abe */
4177 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4178         .master         = &omap44xx_l3_main_1_hwmod,
4179         .slave          = &omap44xx_l4_abe_hwmod,
4180         .clk            = "l3_div_ck",
4181         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4182 };
4183
4184 /* mpu -> l4_abe */
4185 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4186         .master         = &omap44xx_mpu_hwmod,
4187         .slave          = &omap44xx_l4_abe_hwmod,
4188         .clk            = "ocp_abe_iclk",
4189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4190 };
4191
4192 /* l3_main_1 -> l4_cfg */
4193 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4194         .master         = &omap44xx_l3_main_1_hwmod,
4195         .slave          = &omap44xx_l4_cfg_hwmod,
4196         .clk            = "l3_div_ck",
4197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4198 };
4199
4200 /* l3_main_2 -> l4_per */
4201 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4202         .master         = &omap44xx_l3_main_2_hwmod,
4203         .slave          = &omap44xx_l4_per_hwmod,
4204         .clk            = "l3_div_ck",
4205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4206 };
4207
4208 /* l4_cfg -> l4_wkup */
4209 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4210         .master         = &omap44xx_l4_cfg_hwmod,
4211         .slave          = &omap44xx_l4_wkup_hwmod,
4212         .clk            = "l4_div_ck",
4213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4214 };
4215
4216 /* mpu -> mpu_private */
4217 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4218         .master         = &omap44xx_mpu_hwmod,
4219         .slave          = &omap44xx_mpu_private_hwmod,
4220         .clk            = "l3_div_ck",
4221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4222 };
4223
4224 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4225         {
4226                 .pa_start       = 0x4a102000,
4227                 .pa_end         = 0x4a10207f,
4228                 .flags          = ADDR_TYPE_RT
4229         },
4230         { }
4231 };
4232
4233 /* l4_cfg -> ocp_wp_noc */
4234 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4235         .master         = &omap44xx_l4_cfg_hwmod,
4236         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4237         .clk            = "l4_div_ck",
4238         .addr           = omap44xx_ocp_wp_noc_addrs,
4239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4240 };
4241
4242 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4243         {
4244                 .pa_start       = 0x401f1000,
4245                 .pa_end         = 0x401f13ff,
4246                 .flags          = ADDR_TYPE_RT
4247         },
4248         { }
4249 };
4250
4251 /* l4_abe -> aess */
4252 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4253         .master         = &omap44xx_l4_abe_hwmod,
4254         .slave          = &omap44xx_aess_hwmod,
4255         .clk            = "ocp_abe_iclk",
4256         .addr           = omap44xx_aess_addrs,
4257         .user           = OCP_USER_MPU,
4258 };
4259
4260 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4261         {
4262                 .pa_start       = 0x490f1000,
4263                 .pa_end         = 0x490f13ff,
4264                 .flags          = ADDR_TYPE_RT
4265         },
4266         { }
4267 };
4268
4269 /* l4_abe -> aess (dma) */
4270 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4271         .master         = &omap44xx_l4_abe_hwmod,
4272         .slave          = &omap44xx_aess_hwmod,
4273         .clk            = "ocp_abe_iclk",
4274         .addr           = omap44xx_aess_dma_addrs,
4275         .user           = OCP_USER_SDMA,
4276 };
4277
4278 /* l3_main_2 -> c2c */
4279 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4280         .master         = &omap44xx_l3_main_2_hwmod,
4281         .slave          = &omap44xx_c2c_hwmod,
4282         .clk            = "l3_div_ck",
4283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4284 };
4285
4286 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4287         {
4288                 .pa_start       = 0x4a304000,
4289                 .pa_end         = 0x4a30401f,
4290                 .flags          = ADDR_TYPE_RT
4291         },
4292         { }
4293 };
4294
4295 /* l4_wkup -> counter_32k */
4296 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4297         .master         = &omap44xx_l4_wkup_hwmod,
4298         .slave          = &omap44xx_counter_32k_hwmod,
4299         .clk            = "l4_wkup_clk_mux_ck",
4300         .addr           = omap44xx_counter_32k_addrs,
4301         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4302 };
4303
4304 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4305         {
4306                 .pa_start       = 0x4a002000,
4307                 .pa_end         = 0x4a0027ff,
4308                 .flags          = ADDR_TYPE_RT
4309         },
4310         { }
4311 };
4312
4313 /* l4_cfg -> ctrl_module_core */
4314 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4315         .master         = &omap44xx_l4_cfg_hwmod,
4316         .slave          = &omap44xx_ctrl_module_core_hwmod,
4317         .clk            = "l4_div_ck",
4318         .addr           = omap44xx_ctrl_module_core_addrs,
4319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4320 };
4321
4322 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4323         {
4324                 .pa_start       = 0x4a100000,
4325                 .pa_end         = 0x4a1007ff,
4326                 .flags          = ADDR_TYPE_RT
4327         },
4328         { }
4329 };
4330
4331 /* l4_cfg -> ctrl_module_pad_core */
4332 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4333         .master         = &omap44xx_l4_cfg_hwmod,
4334         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4335         .clk            = "l4_div_ck",
4336         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4338 };
4339
4340 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4341         {
4342                 .pa_start       = 0x4a30c000,
4343                 .pa_end         = 0x4a30c7ff,
4344                 .flags          = ADDR_TYPE_RT
4345         },
4346         { }
4347 };
4348
4349 /* l4_wkup -> ctrl_module_wkup */
4350 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4351         .master         = &omap44xx_l4_wkup_hwmod,
4352         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4353         .clk            = "l4_wkup_clk_mux_ck",
4354         .addr           = omap44xx_ctrl_module_wkup_addrs,
4355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4356 };
4357
4358 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4359         {
4360                 .pa_start       = 0x4a31e000,
4361                 .pa_end         = 0x4a31e7ff,
4362                 .flags          = ADDR_TYPE_RT
4363         },
4364         { }
4365 };
4366
4367 /* l4_wkup -> ctrl_module_pad_wkup */
4368 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4369         .master         = &omap44xx_l4_wkup_hwmod,
4370         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4371         .clk            = "l4_wkup_clk_mux_ck",
4372         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4374 };
4375
4376 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4377         {
4378                 .pa_start       = 0x54160000,
4379                 .pa_end         = 0x54167fff,
4380                 .flags          = ADDR_TYPE_RT
4381         },
4382         { }
4383 };
4384
4385 /* l3_instr -> debugss */
4386 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4387         .master         = &omap44xx_l3_instr_hwmod,
4388         .slave          = &omap44xx_debugss_hwmod,
4389         .clk            = "l3_div_ck",
4390         .addr           = omap44xx_debugss_addrs,
4391         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4392 };
4393
4394 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4395         {
4396                 .pa_start       = 0x4a056000,
4397                 .pa_end         = 0x4a056fff,
4398                 .flags          = ADDR_TYPE_RT
4399         },
4400         { }
4401 };
4402
4403 /* l4_cfg -> dma_system */
4404 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4405         .master         = &omap44xx_l4_cfg_hwmod,
4406         .slave          = &omap44xx_dma_system_hwmod,
4407         .clk            = "l4_div_ck",
4408         .addr           = omap44xx_dma_system_addrs,
4409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4410 };
4411
4412 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4413         {
4414                 .name           = "mpu",
4415                 .pa_start       = 0x4012e000,
4416                 .pa_end         = 0x4012e07f,
4417                 .flags          = ADDR_TYPE_RT
4418         },
4419         { }
4420 };
4421
4422 /* l4_abe -> dmic */
4423 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4424         .master         = &omap44xx_l4_abe_hwmod,
4425         .slave          = &omap44xx_dmic_hwmod,
4426         .clk            = "ocp_abe_iclk",
4427         .addr           = omap44xx_dmic_addrs,
4428         .user           = OCP_USER_MPU,
4429 };
4430
4431 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4432         {
4433                 .name           = "dma",
4434                 .pa_start       = 0x4902e000,
4435                 .pa_end         = 0x4902e07f,
4436                 .flags          = ADDR_TYPE_RT
4437         },
4438         { }
4439 };
4440
4441 /* l4_abe -> dmic (dma) */
4442 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4443         .master         = &omap44xx_l4_abe_hwmod,
4444         .slave          = &omap44xx_dmic_hwmod,
4445         .clk            = "ocp_abe_iclk",
4446         .addr           = omap44xx_dmic_dma_addrs,
4447         .user           = OCP_USER_SDMA,
4448 };
4449
4450 /* dsp -> iva */
4451 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4452         .master         = &omap44xx_dsp_hwmod,
4453         .slave          = &omap44xx_iva_hwmod,
4454         .clk            = "dpll_iva_m5x2_ck",
4455         .user           = OCP_USER_DSP,
4456 };
4457
4458 /* dsp -> sl2if */
4459 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4460         .master         = &omap44xx_dsp_hwmod,
4461         .slave          = &omap44xx_sl2if_hwmod,
4462         .clk            = "dpll_iva_m5x2_ck",
4463         .user           = OCP_USER_DSP,
4464 };
4465
4466 /* l4_cfg -> dsp */
4467 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4468         .master         = &omap44xx_l4_cfg_hwmod,
4469         .slave          = &omap44xx_dsp_hwmod,
4470         .clk            = "l4_div_ck",
4471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4472 };
4473
4474 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4475         {
4476                 .pa_start       = 0x58000000,
4477                 .pa_end         = 0x5800007f,
4478                 .flags          = ADDR_TYPE_RT
4479         },
4480         { }
4481 };
4482
4483 /* l3_main_2 -> dss */
4484 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4485         .master         = &omap44xx_l3_main_2_hwmod,
4486         .slave          = &omap44xx_dss_hwmod,
4487         .clk            = "dss_fck",
4488         .addr           = omap44xx_dss_dma_addrs,
4489         .user           = OCP_USER_SDMA,
4490 };
4491
4492 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4493         {
4494                 .pa_start       = 0x48040000,
4495                 .pa_end         = 0x4804007f,
4496                 .flags          = ADDR_TYPE_RT
4497         },
4498         { }
4499 };
4500
4501 /* l4_per -> dss */
4502 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4503         .master         = &omap44xx_l4_per_hwmod,
4504         .slave          = &omap44xx_dss_hwmod,
4505         .clk            = "l4_div_ck",
4506         .addr           = omap44xx_dss_addrs,
4507         .user           = OCP_USER_MPU,
4508 };
4509
4510 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4511         {
4512                 .pa_start       = 0x58001000,
4513                 .pa_end         = 0x58001fff,
4514                 .flags          = ADDR_TYPE_RT
4515         },
4516         { }
4517 };
4518
4519 /* l3_main_2 -> dss_dispc */
4520 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4521         .master         = &omap44xx_l3_main_2_hwmod,
4522         .slave          = &omap44xx_dss_dispc_hwmod,
4523         .clk            = "dss_fck",
4524         .addr           = omap44xx_dss_dispc_dma_addrs,
4525         .user           = OCP_USER_SDMA,
4526 };
4527
4528 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4529         {
4530                 .pa_start       = 0x48041000,
4531                 .pa_end         = 0x48041fff,
4532                 .flags          = ADDR_TYPE_RT
4533         },
4534         { }
4535 };
4536
4537 /* l4_per -> dss_dispc */
4538 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4539         .master         = &omap44xx_l4_per_hwmod,
4540         .slave          = &omap44xx_dss_dispc_hwmod,
4541         .clk            = "l4_div_ck",
4542         .addr           = omap44xx_dss_dispc_addrs,
4543         .user           = OCP_USER_MPU,
4544 };
4545
4546 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4547         {
4548                 .pa_start       = 0x58004000,
4549                 .pa_end         = 0x580041ff,
4550                 .flags          = ADDR_TYPE_RT
4551         },
4552         { }
4553 };
4554
4555 /* l3_main_2 -> dss_dsi1 */
4556 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4557         .master         = &omap44xx_l3_main_2_hwmod,
4558         .slave          = &omap44xx_dss_dsi1_hwmod,
4559         .clk            = "dss_fck",
4560         .addr           = omap44xx_dss_dsi1_dma_addrs,
4561         .user           = OCP_USER_SDMA,
4562 };
4563
4564 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4565         {
4566                 .pa_start       = 0x48044000,
4567                 .pa_end         = 0x480441ff,
4568                 .flags          = ADDR_TYPE_RT
4569         },
4570         { }
4571 };
4572
4573 /* l4_per -> dss_dsi1 */
4574 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4575         .master         = &omap44xx_l4_per_hwmod,
4576         .slave          = &omap44xx_dss_dsi1_hwmod,
4577         .clk            = "l4_div_ck",
4578         .addr           = omap44xx_dss_dsi1_addrs,
4579         .user           = OCP_USER_MPU,
4580 };
4581
4582 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4583         {
4584                 .pa_start       = 0x58005000,
4585                 .pa_end         = 0x580051ff,
4586                 .flags          = ADDR_TYPE_RT
4587         },
4588         { }
4589 };
4590
4591 /* l3_main_2 -> dss_dsi2 */
4592 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4593         .master         = &omap44xx_l3_main_2_hwmod,
4594         .slave          = &omap44xx_dss_dsi2_hwmod,
4595         .clk            = "dss_fck",
4596         .addr           = omap44xx_dss_dsi2_dma_addrs,
4597         .user           = OCP_USER_SDMA,
4598 };
4599
4600 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4601         {
4602                 .pa_start       = 0x48045000,
4603                 .pa_end         = 0x480451ff,
4604                 .flags          = ADDR_TYPE_RT
4605         },
4606         { }
4607 };
4608
4609 /* l4_per -> dss_dsi2 */
4610 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4611         .master         = &omap44xx_l4_per_hwmod,
4612         .slave          = &omap44xx_dss_dsi2_hwmod,
4613         .clk            = "l4_div_ck",
4614         .addr           = omap44xx_dss_dsi2_addrs,
4615         .user           = OCP_USER_MPU,
4616 };
4617
4618 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4619         {
4620                 .pa_start       = 0x58006000,
4621                 .pa_end         = 0x58006fff,
4622                 .flags          = ADDR_TYPE_RT
4623         },
4624         { }
4625 };
4626
4627 /* l3_main_2 -> dss_hdmi */
4628 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4629         .master         = &omap44xx_l3_main_2_hwmod,
4630         .slave          = &omap44xx_dss_hdmi_hwmod,
4631         .clk            = "dss_fck",
4632         .addr           = omap44xx_dss_hdmi_dma_addrs,
4633         .user           = OCP_USER_SDMA,
4634 };
4635
4636 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4637         {
4638                 .pa_start       = 0x48046000,
4639                 .pa_end         = 0x48046fff,
4640                 .flags          = ADDR_TYPE_RT
4641         },
4642         { }
4643 };
4644
4645 /* l4_per -> dss_hdmi */
4646 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4647         .master         = &omap44xx_l4_per_hwmod,
4648         .slave          = &omap44xx_dss_hdmi_hwmod,
4649         .clk            = "l4_div_ck",
4650         .addr           = omap44xx_dss_hdmi_addrs,
4651         .user           = OCP_USER_MPU,
4652 };
4653
4654 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4655         {
4656                 .pa_start       = 0x58002000,
4657                 .pa_end         = 0x580020ff,
4658                 .flags          = ADDR_TYPE_RT
4659         },
4660         { }
4661 };
4662
4663 /* l3_main_2 -> dss_rfbi */
4664 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4665         .master         = &omap44xx_l3_main_2_hwmod,
4666         .slave          = &omap44xx_dss_rfbi_hwmod,
4667         .clk            = "dss_fck",
4668         .addr           = omap44xx_dss_rfbi_dma_addrs,
4669         .user           = OCP_USER_SDMA,
4670 };
4671
4672 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4673         {
4674                 .pa_start       = 0x48042000,
4675                 .pa_end         = 0x480420ff,
4676                 .flags          = ADDR_TYPE_RT
4677         },
4678         { }
4679 };
4680
4681 /* l4_per -> dss_rfbi */
4682 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4683         .master         = &omap44xx_l4_per_hwmod,
4684         .slave          = &omap44xx_dss_rfbi_hwmod,
4685         .clk            = "l4_div_ck",
4686         .addr           = omap44xx_dss_rfbi_addrs,
4687         .user           = OCP_USER_MPU,
4688 };
4689
4690 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4691         {
4692                 .pa_start       = 0x58003000,
4693                 .pa_end         = 0x580030ff,
4694                 .flags          = ADDR_TYPE_RT
4695         },
4696         { }
4697 };
4698
4699 /* l3_main_2 -> dss_venc */
4700 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4701         .master         = &omap44xx_l3_main_2_hwmod,
4702         .slave          = &omap44xx_dss_venc_hwmod,
4703         .clk            = "dss_fck",
4704         .addr           = omap44xx_dss_venc_dma_addrs,
4705         .user           = OCP_USER_SDMA,
4706 };
4707
4708 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4709         {
4710                 .pa_start       = 0x48043000,
4711                 .pa_end         = 0x480430ff,
4712                 .flags          = ADDR_TYPE_RT
4713         },
4714         { }
4715 };
4716
4717 /* l4_per -> dss_venc */
4718 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4719         .master         = &omap44xx_l4_per_hwmod,
4720         .slave          = &omap44xx_dss_venc_hwmod,
4721         .clk            = "l4_div_ck",
4722         .addr           = omap44xx_dss_venc_addrs,
4723         .user           = OCP_USER_MPU,
4724 };
4725
4726 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4727         {
4728                 .pa_start       = 0x48078000,
4729                 .pa_end         = 0x48078fff,
4730                 .flags          = ADDR_TYPE_RT
4731         },
4732         { }
4733 };
4734
4735 /* l4_per -> elm */
4736 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4737         .master         = &omap44xx_l4_per_hwmod,
4738         .slave          = &omap44xx_elm_hwmod,
4739         .clk            = "l4_div_ck",
4740         .addr           = omap44xx_elm_addrs,
4741         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4742 };
4743
4744 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4745         {
4746                 .pa_start       = 0x4c000000,
4747                 .pa_end         = 0x4c0000ff,
4748                 .flags          = ADDR_TYPE_RT
4749         },
4750         { }
4751 };
4752
4753 /* emif_fw -> emif1 */
4754 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4755         .master         = &omap44xx_emif_fw_hwmod,
4756         .slave          = &omap44xx_emif1_hwmod,
4757         .clk            = "l3_div_ck",
4758         .addr           = omap44xx_emif1_addrs,
4759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4760 };
4761
4762 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4763         {
4764                 .pa_start       = 0x4d000000,
4765                 .pa_end         = 0x4d0000ff,
4766                 .flags          = ADDR_TYPE_RT
4767         },
4768         { }
4769 };
4770
4771 /* emif_fw -> emif2 */
4772 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4773         .master         = &omap44xx_emif_fw_hwmod,
4774         .slave          = &omap44xx_emif2_hwmod,
4775         .clk            = "l3_div_ck",
4776         .addr           = omap44xx_emif2_addrs,
4777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4778 };
4779
4780 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4781         {
4782                 .pa_start       = 0x4a10a000,
4783                 .pa_end         = 0x4a10a1ff,
4784                 .flags          = ADDR_TYPE_RT
4785         },
4786         { }
4787 };
4788
4789 /* l4_cfg -> fdif */
4790 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4791         .master         = &omap44xx_l4_cfg_hwmod,
4792         .slave          = &omap44xx_fdif_hwmod,
4793         .clk            = "l4_div_ck",
4794         .addr           = omap44xx_fdif_addrs,
4795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4796 };
4797
4798 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4799         {
4800                 .pa_start       = 0x4a310000,
4801                 .pa_end         = 0x4a3101ff,
4802                 .flags          = ADDR_TYPE_RT
4803         },
4804         { }
4805 };
4806
4807 /* l4_wkup -> gpio1 */
4808 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4809         .master         = &omap44xx_l4_wkup_hwmod,
4810         .slave          = &omap44xx_gpio1_hwmod,
4811         .clk            = "l4_wkup_clk_mux_ck",
4812         .addr           = omap44xx_gpio1_addrs,
4813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4814 };
4815
4816 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4817         {
4818                 .pa_start       = 0x48055000,
4819                 .pa_end         = 0x480551ff,
4820                 .flags          = ADDR_TYPE_RT
4821         },
4822         { }
4823 };
4824
4825 /* l4_per -> gpio2 */
4826 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4827         .master         = &omap44xx_l4_per_hwmod,
4828         .slave          = &omap44xx_gpio2_hwmod,
4829         .clk            = "l4_div_ck",
4830         .addr           = omap44xx_gpio2_addrs,
4831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4832 };
4833
4834 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4835         {
4836                 .pa_start       = 0x48057000,
4837                 .pa_end         = 0x480571ff,
4838                 .flags          = ADDR_TYPE_RT
4839         },
4840         { }
4841 };
4842
4843 /* l4_per -> gpio3 */
4844 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4845         .master         = &omap44xx_l4_per_hwmod,
4846         .slave          = &omap44xx_gpio3_hwmod,
4847         .clk            = "l4_div_ck",
4848         .addr           = omap44xx_gpio3_addrs,
4849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4850 };
4851
4852 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4853         {
4854                 .pa_start       = 0x48059000,
4855                 .pa_end         = 0x480591ff,
4856                 .flags          = ADDR_TYPE_RT
4857         },
4858         { }
4859 };
4860
4861 /* l4_per -> gpio4 */
4862 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4863         .master         = &omap44xx_l4_per_hwmod,
4864         .slave          = &omap44xx_gpio4_hwmod,
4865         .clk            = "l4_div_ck",
4866         .addr           = omap44xx_gpio4_addrs,
4867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4868 };
4869
4870 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4871         {
4872                 .pa_start       = 0x4805b000,
4873                 .pa_end         = 0x4805b1ff,
4874                 .flags          = ADDR_TYPE_RT
4875         },
4876         { }
4877 };
4878
4879 /* l4_per -> gpio5 */
4880 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4881         .master         = &omap44xx_l4_per_hwmod,
4882         .slave          = &omap44xx_gpio5_hwmod,
4883         .clk            = "l4_div_ck",
4884         .addr           = omap44xx_gpio5_addrs,
4885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4886 };
4887
4888 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4889         {
4890                 .pa_start       = 0x4805d000,
4891                 .pa_end         = 0x4805d1ff,
4892                 .flags          = ADDR_TYPE_RT
4893         },
4894         { }
4895 };
4896
4897 /* l4_per -> gpio6 */
4898 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4899         .master         = &omap44xx_l4_per_hwmod,
4900         .slave          = &omap44xx_gpio6_hwmod,
4901         .clk            = "l4_div_ck",
4902         .addr           = omap44xx_gpio6_addrs,
4903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4904 };
4905
4906 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4907         {
4908                 .pa_start       = 0x50000000,
4909                 .pa_end         = 0x500003ff,
4910                 .flags          = ADDR_TYPE_RT
4911         },
4912         { }
4913 };
4914
4915 /* l3_main_2 -> gpmc */
4916 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4917         .master         = &omap44xx_l3_main_2_hwmod,
4918         .slave          = &omap44xx_gpmc_hwmod,
4919         .clk            = "l3_div_ck",
4920         .addr           = omap44xx_gpmc_addrs,
4921         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4922 };
4923
4924 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4925         {
4926                 .pa_start       = 0x56000000,
4927                 .pa_end         = 0x5600ffff,
4928                 .flags          = ADDR_TYPE_RT
4929         },
4930         { }
4931 };
4932
4933 /* l3_main_2 -> gpu */
4934 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4935         .master         = &omap44xx_l3_main_2_hwmod,
4936         .slave          = &omap44xx_gpu_hwmod,
4937         .clk            = "l3_div_ck",
4938         .addr           = omap44xx_gpu_addrs,
4939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4940 };
4941
4942 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4943         {
4944                 .pa_start       = 0x480b2000,
4945                 .pa_end         = 0x480b201f,
4946                 .flags          = ADDR_TYPE_RT
4947         },
4948         { }
4949 };
4950
4951 /* l4_per -> hdq1w */
4952 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4953         .master         = &omap44xx_l4_per_hwmod,
4954         .slave          = &omap44xx_hdq1w_hwmod,
4955         .clk            = "l4_div_ck",
4956         .addr           = omap44xx_hdq1w_addrs,
4957         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4958 };
4959
4960 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4961         {
4962                 .pa_start       = 0x4a058000,
4963                 .pa_end         = 0x4a05bfff,
4964                 .flags          = ADDR_TYPE_RT
4965         },
4966         { }
4967 };
4968
4969 /* l4_cfg -> hsi */
4970 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4971         .master         = &omap44xx_l4_cfg_hwmod,
4972         .slave          = &omap44xx_hsi_hwmod,
4973         .clk            = "l4_div_ck",
4974         .addr           = omap44xx_hsi_addrs,
4975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4976 };
4977
4978 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4979         {
4980                 .pa_start       = 0x48070000,
4981                 .pa_end         = 0x480700ff,
4982                 .flags          = ADDR_TYPE_RT
4983         },
4984         { }
4985 };
4986
4987 /* l4_per -> i2c1 */
4988 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4989         .master         = &omap44xx_l4_per_hwmod,
4990         .slave          = &omap44xx_i2c1_hwmod,
4991         .clk            = "l4_div_ck",
4992         .addr           = omap44xx_i2c1_addrs,
4993         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4994 };
4995
4996 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4997         {
4998                 .pa_start       = 0x48072000,
4999                 .pa_end         = 0x480720ff,
5000                 .flags          = ADDR_TYPE_RT
5001         },
5002         { }
5003 };
5004
5005 /* l4_per -> i2c2 */
5006 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5007         .master         = &omap44xx_l4_per_hwmod,
5008         .slave          = &omap44xx_i2c2_hwmod,
5009         .clk            = "l4_div_ck",
5010         .addr           = omap44xx_i2c2_addrs,
5011         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5012 };
5013
5014 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5015         {
5016                 .pa_start       = 0x48060000,
5017                 .pa_end         = 0x480600ff,
5018                 .flags          = ADDR_TYPE_RT
5019         },
5020         { }
5021 };
5022
5023 /* l4_per -> i2c3 */
5024 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5025         .master         = &omap44xx_l4_per_hwmod,
5026         .slave          = &omap44xx_i2c3_hwmod,
5027         .clk            = "l4_div_ck",
5028         .addr           = omap44xx_i2c3_addrs,
5029         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5030 };
5031
5032 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5033         {
5034                 .pa_start       = 0x48350000,
5035                 .pa_end         = 0x483500ff,
5036                 .flags          = ADDR_TYPE_RT
5037         },
5038         { }
5039 };
5040
5041 /* l4_per -> i2c4 */
5042 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5043         .master         = &omap44xx_l4_per_hwmod,
5044         .slave          = &omap44xx_i2c4_hwmod,
5045         .clk            = "l4_div_ck",
5046         .addr           = omap44xx_i2c4_addrs,
5047         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5048 };
5049
5050 /* l3_main_2 -> ipu */
5051 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5052         .master         = &omap44xx_l3_main_2_hwmod,
5053         .slave          = &omap44xx_ipu_hwmod,
5054         .clk            = "l3_div_ck",
5055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5056 };
5057
5058 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5059         {
5060                 .pa_start       = 0x52000000,
5061                 .pa_end         = 0x520000ff,
5062                 .flags          = ADDR_TYPE_RT
5063         },
5064         { }
5065 };
5066
5067 /* l3_main_2 -> iss */
5068 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5069         .master         = &omap44xx_l3_main_2_hwmod,
5070         .slave          = &omap44xx_iss_hwmod,
5071         .clk            = "l3_div_ck",
5072         .addr           = omap44xx_iss_addrs,
5073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5074 };
5075
5076 /* iva -> sl2if */
5077 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5078         .master         = &omap44xx_iva_hwmod,
5079         .slave          = &omap44xx_sl2if_hwmod,
5080         .clk            = "dpll_iva_m5x2_ck",
5081         .user           = OCP_USER_IVA,
5082 };
5083
5084 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5085         {
5086                 .pa_start       = 0x5a000000,
5087                 .pa_end         = 0x5a07ffff,
5088                 .flags          = ADDR_TYPE_RT
5089         },
5090         { }
5091 };
5092
5093 /* l3_main_2 -> iva */
5094 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5095         .master         = &omap44xx_l3_main_2_hwmod,
5096         .slave          = &omap44xx_iva_hwmod,
5097         .clk            = "l3_div_ck",
5098         .addr           = omap44xx_iva_addrs,
5099         .user           = OCP_USER_MPU,
5100 };
5101
5102 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5103         {
5104                 .pa_start       = 0x4a31c000,
5105                 .pa_end         = 0x4a31c07f,
5106                 .flags          = ADDR_TYPE_RT
5107         },
5108         { }
5109 };
5110
5111 /* l4_wkup -> kbd */
5112 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5113         .master         = &omap44xx_l4_wkup_hwmod,
5114         .slave          = &omap44xx_kbd_hwmod,
5115         .clk            = "l4_wkup_clk_mux_ck",
5116         .addr           = omap44xx_kbd_addrs,
5117         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5118 };
5119
5120 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5121         {
5122                 .pa_start       = 0x4a0f4000,
5123                 .pa_end         = 0x4a0f41ff,
5124                 .flags          = ADDR_TYPE_RT
5125         },
5126         { }
5127 };
5128
5129 /* l4_cfg -> mailbox */
5130 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5131         .master         = &omap44xx_l4_cfg_hwmod,
5132         .slave          = &omap44xx_mailbox_hwmod,
5133         .clk            = "l4_div_ck",
5134         .addr           = omap44xx_mailbox_addrs,
5135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5136 };
5137
5138 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5139         {
5140                 .pa_start       = 0x40128000,
5141                 .pa_end         = 0x401283ff,
5142                 .flags          = ADDR_TYPE_RT
5143         },
5144         { }
5145 };
5146
5147 /* l4_abe -> mcasp */
5148 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5149         .master         = &omap44xx_l4_abe_hwmod,
5150         .slave          = &omap44xx_mcasp_hwmod,
5151         .clk            = "ocp_abe_iclk",
5152         .addr           = omap44xx_mcasp_addrs,
5153         .user           = OCP_USER_MPU,
5154 };
5155
5156 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5157         {
5158                 .pa_start       = 0x49028000,
5159                 .pa_end         = 0x490283ff,
5160                 .flags          = ADDR_TYPE_RT
5161         },
5162         { }
5163 };
5164
5165 /* l4_abe -> mcasp (dma) */
5166 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5167         .master         = &omap44xx_l4_abe_hwmod,
5168         .slave          = &omap44xx_mcasp_hwmod,
5169         .clk            = "ocp_abe_iclk",
5170         .addr           = omap44xx_mcasp_dma_addrs,
5171         .user           = OCP_USER_SDMA,
5172 };
5173
5174 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5175         {
5176                 .name           = "mpu",
5177                 .pa_start       = 0x40122000,
5178                 .pa_end         = 0x401220ff,
5179                 .flags          = ADDR_TYPE_RT
5180         },
5181         { }
5182 };
5183
5184 /* l4_abe -> mcbsp1 */
5185 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5186         .master         = &omap44xx_l4_abe_hwmod,
5187         .slave          = &omap44xx_mcbsp1_hwmod,
5188         .clk            = "ocp_abe_iclk",
5189         .addr           = omap44xx_mcbsp1_addrs,
5190         .user           = OCP_USER_MPU,
5191 };
5192
5193 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5194         {
5195                 .name           = "dma",
5196                 .pa_start       = 0x49022000,
5197                 .pa_end         = 0x490220ff,
5198                 .flags          = ADDR_TYPE_RT
5199         },
5200         { }
5201 };
5202
5203 /* l4_abe -> mcbsp1 (dma) */
5204 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5205         .master         = &omap44xx_l4_abe_hwmod,
5206         .slave          = &omap44xx_mcbsp1_hwmod,
5207         .clk            = "ocp_abe_iclk",
5208         .addr           = omap44xx_mcbsp1_dma_addrs,
5209         .user           = OCP_USER_SDMA,
5210 };
5211
5212 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5213         {
5214                 .name           = "mpu",
5215                 .pa_start       = 0x40124000,
5216                 .pa_end         = 0x401240ff,
5217                 .flags          = ADDR_TYPE_RT
5218         },
5219         { }
5220 };
5221
5222 /* l4_abe -> mcbsp2 */
5223 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5224         .master         = &omap44xx_l4_abe_hwmod,
5225         .slave          = &omap44xx_mcbsp2_hwmod,
5226         .clk            = "ocp_abe_iclk",
5227         .addr           = omap44xx_mcbsp2_addrs,
5228         .user           = OCP_USER_MPU,
5229 };
5230
5231 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5232         {
5233                 .name           = "dma",
5234                 .pa_start       = 0x49024000,
5235                 .pa_end         = 0x490240ff,
5236                 .flags          = ADDR_TYPE_RT
5237         },
5238         { }
5239 };
5240
5241 /* l4_abe -> mcbsp2 (dma) */
5242 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5243         .master         = &omap44xx_l4_abe_hwmod,
5244         .slave          = &omap44xx_mcbsp2_hwmod,
5245         .clk            = "ocp_abe_iclk",
5246         .addr           = omap44xx_mcbsp2_dma_addrs,
5247         .user           = OCP_USER_SDMA,
5248 };
5249
5250 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5251         {
5252                 .name           = "mpu",
5253                 .pa_start       = 0x40126000,
5254                 .pa_end         = 0x401260ff,
5255                 .flags          = ADDR_TYPE_RT
5256         },
5257         { }
5258 };
5259
5260 /* l4_abe -> mcbsp3 */
5261 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5262         .master         = &omap44xx_l4_abe_hwmod,
5263         .slave          = &omap44xx_mcbsp3_hwmod,
5264         .clk            = "ocp_abe_iclk",
5265         .addr           = omap44xx_mcbsp3_addrs,
5266         .user           = OCP_USER_MPU,
5267 };
5268
5269 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5270         {
5271                 .name           = "dma",
5272                 .pa_start       = 0x49026000,
5273                 .pa_end         = 0x490260ff,
5274                 .flags          = ADDR_TYPE_RT
5275         },
5276         { }
5277 };
5278
5279 /* l4_abe -> mcbsp3 (dma) */
5280 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5281         .master         = &omap44xx_l4_abe_hwmod,
5282         .slave          = &omap44xx_mcbsp3_hwmod,
5283         .clk            = "ocp_abe_iclk",
5284         .addr           = omap44xx_mcbsp3_dma_addrs,
5285         .user           = OCP_USER_SDMA,
5286 };
5287
5288 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5289         {
5290                 .pa_start       = 0x48096000,
5291                 .pa_end         = 0x480960ff,
5292                 .flags          = ADDR_TYPE_RT
5293         },
5294         { }
5295 };
5296
5297 /* l4_per -> mcbsp4 */
5298 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5299         .master         = &omap44xx_l4_per_hwmod,
5300         .slave          = &omap44xx_mcbsp4_hwmod,
5301         .clk            = "l4_div_ck",
5302         .addr           = omap44xx_mcbsp4_addrs,
5303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5304 };
5305
5306 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5307         {
5308                 .name           = "mpu",
5309                 .pa_start       = 0x40132000,
5310                 .pa_end         = 0x4013207f,
5311                 .flags          = ADDR_TYPE_RT
5312         },
5313         { }
5314 };
5315
5316 /* l4_abe -> mcpdm */
5317 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5318         .master         = &omap44xx_l4_abe_hwmod,
5319         .slave          = &omap44xx_mcpdm_hwmod,
5320         .clk            = "ocp_abe_iclk",
5321         .addr           = omap44xx_mcpdm_addrs,
5322         .user           = OCP_USER_MPU,
5323 };
5324
5325 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5326         {
5327                 .name           = "dma",
5328                 .pa_start       = 0x49032000,
5329                 .pa_end         = 0x4903207f,
5330                 .flags          = ADDR_TYPE_RT
5331         },
5332         { }
5333 };
5334
5335 /* l4_abe -> mcpdm (dma) */
5336 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5337         .master         = &omap44xx_l4_abe_hwmod,
5338         .slave          = &omap44xx_mcpdm_hwmod,
5339         .clk            = "ocp_abe_iclk",
5340         .addr           = omap44xx_mcpdm_dma_addrs,
5341         .user           = OCP_USER_SDMA,
5342 };
5343
5344 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5345         {
5346                 .pa_start       = 0x48098000,
5347                 .pa_end         = 0x480981ff,
5348                 .flags          = ADDR_TYPE_RT
5349         },
5350         { }
5351 };
5352
5353 /* l4_per -> mcspi1 */
5354 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5355         .master         = &omap44xx_l4_per_hwmod,
5356         .slave          = &omap44xx_mcspi1_hwmod,
5357         .clk            = "l4_div_ck",
5358         .addr           = omap44xx_mcspi1_addrs,
5359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5360 };
5361
5362 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5363         {
5364                 .pa_start       = 0x4809a000,
5365                 .pa_end         = 0x4809a1ff,
5366                 .flags          = ADDR_TYPE_RT
5367         },
5368         { }
5369 };
5370
5371 /* l4_per -> mcspi2 */
5372 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5373         .master         = &omap44xx_l4_per_hwmod,
5374         .slave          = &omap44xx_mcspi2_hwmod,
5375         .clk            = "l4_div_ck",
5376         .addr           = omap44xx_mcspi2_addrs,
5377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5378 };
5379
5380 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5381         {
5382                 .pa_start       = 0x480b8000,
5383                 .pa_end         = 0x480b81ff,
5384                 .flags          = ADDR_TYPE_RT
5385         },
5386         { }
5387 };
5388
5389 /* l4_per -> mcspi3 */
5390 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5391         .master         = &omap44xx_l4_per_hwmod,
5392         .slave          = &omap44xx_mcspi3_hwmod,
5393         .clk            = "l4_div_ck",
5394         .addr           = omap44xx_mcspi3_addrs,
5395         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5396 };
5397
5398 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5399         {
5400                 .pa_start       = 0x480ba000,
5401                 .pa_end         = 0x480ba1ff,
5402                 .flags          = ADDR_TYPE_RT
5403         },
5404         { }
5405 };
5406
5407 /* l4_per -> mcspi4 */
5408 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5409         .master         = &omap44xx_l4_per_hwmod,
5410         .slave          = &omap44xx_mcspi4_hwmod,
5411         .clk            = "l4_div_ck",
5412         .addr           = omap44xx_mcspi4_addrs,
5413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5414 };
5415
5416 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5417         {
5418                 .pa_start       = 0x4809c000,
5419                 .pa_end         = 0x4809c3ff,
5420                 .flags          = ADDR_TYPE_RT
5421         },
5422         { }
5423 };
5424
5425 /* l4_per -> mmc1 */
5426 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5427         .master         = &omap44xx_l4_per_hwmod,
5428         .slave          = &omap44xx_mmc1_hwmod,
5429         .clk            = "l4_div_ck",
5430         .addr           = omap44xx_mmc1_addrs,
5431         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5432 };
5433
5434 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5435         {
5436                 .pa_start       = 0x480b4000,
5437                 .pa_end         = 0x480b43ff,
5438                 .flags          = ADDR_TYPE_RT
5439         },
5440         { }
5441 };
5442
5443 /* l4_per -> mmc2 */
5444 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5445         .master         = &omap44xx_l4_per_hwmod,
5446         .slave          = &omap44xx_mmc2_hwmod,
5447         .clk            = "l4_div_ck",
5448         .addr           = omap44xx_mmc2_addrs,
5449         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5450 };
5451
5452 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5453         {
5454                 .pa_start       = 0x480ad000,
5455                 .pa_end         = 0x480ad3ff,
5456                 .flags          = ADDR_TYPE_RT
5457         },
5458         { }
5459 };
5460
5461 /* l4_per -> mmc3 */
5462 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5463         .master         = &omap44xx_l4_per_hwmod,
5464         .slave          = &omap44xx_mmc3_hwmod,
5465         .clk            = "l4_div_ck",
5466         .addr           = omap44xx_mmc3_addrs,
5467         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5468 };
5469
5470 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5471         {
5472                 .pa_start       = 0x480d1000,
5473                 .pa_end         = 0x480d13ff,
5474                 .flags          = ADDR_TYPE_RT
5475         },
5476         { }
5477 };
5478
5479 /* l4_per -> mmc4 */
5480 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5481         .master         = &omap44xx_l4_per_hwmod,
5482         .slave          = &omap44xx_mmc4_hwmod,
5483         .clk            = "l4_div_ck",
5484         .addr           = omap44xx_mmc4_addrs,
5485         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5486 };
5487
5488 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5489         {
5490                 .pa_start       = 0x480d5000,
5491                 .pa_end         = 0x480d53ff,
5492                 .flags          = ADDR_TYPE_RT
5493         },
5494         { }
5495 };
5496
5497 /* l4_per -> mmc5 */
5498 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5499         .master         = &omap44xx_l4_per_hwmod,
5500         .slave          = &omap44xx_mmc5_hwmod,
5501         .clk            = "l4_div_ck",
5502         .addr           = omap44xx_mmc5_addrs,
5503         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5504 };
5505
5506 /* l3_main_2 -> ocmc_ram */
5507 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5508         .master         = &omap44xx_l3_main_2_hwmod,
5509         .slave          = &omap44xx_ocmc_ram_hwmod,
5510         .clk            = "l3_div_ck",
5511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5512 };
5513
5514 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5515         {
5516                 .pa_start       = 0x4a0ad000,
5517                 .pa_end         = 0x4a0ad01f,
5518                 .flags          = ADDR_TYPE_RT
5519         },
5520         { }
5521 };
5522
5523 /* l4_cfg -> ocp2scp_usb_phy */
5524 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5525         .master         = &omap44xx_l4_cfg_hwmod,
5526         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5527         .clk            = "l4_div_ck",
5528         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5529         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5530 };
5531
5532 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5533         {
5534                 .pa_start       = 0x48243000,
5535                 .pa_end         = 0x48243fff,
5536                 .flags          = ADDR_TYPE_RT
5537         },
5538         { }
5539 };
5540
5541 /* mpu_private -> prcm_mpu */
5542 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5543         .master         = &omap44xx_mpu_private_hwmod,
5544         .slave          = &omap44xx_prcm_mpu_hwmod,
5545         .clk            = "l3_div_ck",
5546         .addr           = omap44xx_prcm_mpu_addrs,
5547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5548 };
5549
5550 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5551         {
5552                 .pa_start       = 0x4a004000,
5553                 .pa_end         = 0x4a004fff,
5554                 .flags          = ADDR_TYPE_RT
5555         },
5556         { }
5557 };
5558
5559 /* l4_wkup -> cm_core_aon */
5560 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5561         .master         = &omap44xx_l4_wkup_hwmod,
5562         .slave          = &omap44xx_cm_core_aon_hwmod,
5563         .clk            = "l4_wkup_clk_mux_ck",
5564         .addr           = omap44xx_cm_core_aon_addrs,
5565         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5566 };
5567
5568 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5569         {
5570                 .pa_start       = 0x4a008000,
5571                 .pa_end         = 0x4a009fff,
5572                 .flags          = ADDR_TYPE_RT
5573         },
5574         { }
5575 };
5576
5577 /* l4_cfg -> cm_core */
5578 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5579         .master         = &omap44xx_l4_cfg_hwmod,
5580         .slave          = &omap44xx_cm_core_hwmod,
5581         .clk            = "l4_div_ck",
5582         .addr           = omap44xx_cm_core_addrs,
5583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5584 };
5585
5586 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5587         {
5588                 .pa_start       = 0x4a306000,
5589                 .pa_end         = 0x4a307fff,
5590                 .flags          = ADDR_TYPE_RT
5591         },
5592         { }
5593 };
5594
5595 /* l4_wkup -> prm */
5596 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5597         .master         = &omap44xx_l4_wkup_hwmod,
5598         .slave          = &omap44xx_prm_hwmod,
5599         .clk            = "l4_wkup_clk_mux_ck",
5600         .addr           = omap44xx_prm_addrs,
5601         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5602 };
5603
5604 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5605         {
5606                 .pa_start       = 0x4a30a000,
5607                 .pa_end         = 0x4a30a7ff,
5608                 .flags          = ADDR_TYPE_RT
5609         },
5610         { }
5611 };
5612
5613 /* l4_wkup -> scrm */
5614 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5615         .master         = &omap44xx_l4_wkup_hwmod,
5616         .slave          = &omap44xx_scrm_hwmod,
5617         .clk            = "l4_wkup_clk_mux_ck",
5618         .addr           = omap44xx_scrm_addrs,
5619         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5620 };
5621
5622 /* l3_main_2 -> sl2if */
5623 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5624         .master         = &omap44xx_l3_main_2_hwmod,
5625         .slave          = &omap44xx_sl2if_hwmod,
5626         .clk            = "l3_div_ck",
5627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5628 };
5629
5630 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5631         {
5632                 .pa_start       = 0x4012c000,
5633                 .pa_end         = 0x4012c3ff,
5634                 .flags          = ADDR_TYPE_RT
5635         },
5636         { }
5637 };
5638
5639 /* l4_abe -> slimbus1 */
5640 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5641         .master         = &omap44xx_l4_abe_hwmod,
5642         .slave          = &omap44xx_slimbus1_hwmod,
5643         .clk            = "ocp_abe_iclk",
5644         .addr           = omap44xx_slimbus1_addrs,
5645         .user           = OCP_USER_MPU,
5646 };
5647
5648 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5649         {
5650                 .pa_start       = 0x4902c000,
5651                 .pa_end         = 0x4902c3ff,
5652                 .flags          = ADDR_TYPE_RT
5653         },
5654         { }
5655 };
5656
5657 /* l4_abe -> slimbus1 (dma) */
5658 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5659         .master         = &omap44xx_l4_abe_hwmod,
5660         .slave          = &omap44xx_slimbus1_hwmod,
5661         .clk            = "ocp_abe_iclk",
5662         .addr           = omap44xx_slimbus1_dma_addrs,
5663         .user           = OCP_USER_SDMA,
5664 };
5665
5666 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5667         {
5668                 .pa_start       = 0x48076000,
5669                 .pa_end         = 0x480763ff,
5670                 .flags          = ADDR_TYPE_RT
5671         },
5672         { }
5673 };
5674
5675 /* l4_per -> slimbus2 */
5676 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5677         .master         = &omap44xx_l4_per_hwmod,
5678         .slave          = &omap44xx_slimbus2_hwmod,
5679         .clk            = "l4_div_ck",
5680         .addr           = omap44xx_slimbus2_addrs,
5681         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5682 };
5683
5684 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5685         {
5686                 .pa_start       = 0x4a0dd000,
5687                 .pa_end         = 0x4a0dd03f,
5688                 .flags          = ADDR_TYPE_RT
5689         },
5690         { }
5691 };
5692
5693 /* l4_cfg -> smartreflex_core */
5694 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5695         .master         = &omap44xx_l4_cfg_hwmod,
5696         .slave          = &omap44xx_smartreflex_core_hwmod,
5697         .clk            = "l4_div_ck",
5698         .addr           = omap44xx_smartreflex_core_addrs,
5699         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5700 };
5701
5702 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5703         {
5704                 .pa_start       = 0x4a0db000,
5705                 .pa_end         = 0x4a0db03f,
5706                 .flags          = ADDR_TYPE_RT
5707         },
5708         { }
5709 };
5710
5711 /* l4_cfg -> smartreflex_iva */
5712 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5713         .master         = &omap44xx_l4_cfg_hwmod,
5714         .slave          = &omap44xx_smartreflex_iva_hwmod,
5715         .clk            = "l4_div_ck",
5716         .addr           = omap44xx_smartreflex_iva_addrs,
5717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5718 };
5719
5720 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5721         {
5722                 .pa_start       = 0x4a0d9000,
5723                 .pa_end         = 0x4a0d903f,
5724                 .flags          = ADDR_TYPE_RT
5725         },
5726         { }
5727 };
5728
5729 /* l4_cfg -> smartreflex_mpu */
5730 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5731         .master         = &omap44xx_l4_cfg_hwmod,
5732         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5733         .clk            = "l4_div_ck",
5734         .addr           = omap44xx_smartreflex_mpu_addrs,
5735         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5736 };
5737
5738 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5739         {
5740                 .pa_start       = 0x4a0f6000,
5741                 .pa_end         = 0x4a0f6fff,
5742                 .flags          = ADDR_TYPE_RT
5743         },
5744         { }
5745 };
5746
5747 /* l4_cfg -> spinlock */
5748 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5749         .master         = &omap44xx_l4_cfg_hwmod,
5750         .slave          = &omap44xx_spinlock_hwmod,
5751         .clk            = "l4_div_ck",
5752         .addr           = omap44xx_spinlock_addrs,
5753         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5754 };
5755
5756 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5757         {
5758                 .pa_start       = 0x4a318000,
5759                 .pa_end         = 0x4a31807f,
5760                 .flags          = ADDR_TYPE_RT
5761         },
5762         { }
5763 };
5764
5765 /* l4_wkup -> timer1 */
5766 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5767         .master         = &omap44xx_l4_wkup_hwmod,
5768         .slave          = &omap44xx_timer1_hwmod,
5769         .clk            = "l4_wkup_clk_mux_ck",
5770         .addr           = omap44xx_timer1_addrs,
5771         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5772 };
5773
5774 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5775         {
5776                 .pa_start       = 0x48032000,
5777                 .pa_end         = 0x4803207f,
5778                 .flags          = ADDR_TYPE_RT
5779         },
5780         { }
5781 };
5782
5783 /* l4_per -> timer2 */
5784 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5785         .master         = &omap44xx_l4_per_hwmod,
5786         .slave          = &omap44xx_timer2_hwmod,
5787         .clk            = "l4_div_ck",
5788         .addr           = omap44xx_timer2_addrs,
5789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5790 };
5791
5792 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5793         {
5794                 .pa_start       = 0x48034000,
5795                 .pa_end         = 0x4803407f,
5796                 .flags          = ADDR_TYPE_RT
5797         },
5798         { }
5799 };
5800
5801 /* l4_per -> timer3 */
5802 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5803         .master         = &omap44xx_l4_per_hwmod,
5804         .slave          = &omap44xx_timer3_hwmod,
5805         .clk            = "l4_div_ck",
5806         .addr           = omap44xx_timer3_addrs,
5807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5808 };
5809
5810 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5811         {
5812                 .pa_start       = 0x48036000,
5813                 .pa_end         = 0x4803607f,
5814                 .flags          = ADDR_TYPE_RT
5815         },
5816         { }
5817 };
5818
5819 /* l4_per -> timer4 */
5820 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5821         .master         = &omap44xx_l4_per_hwmod,
5822         .slave          = &omap44xx_timer4_hwmod,
5823         .clk            = "l4_div_ck",
5824         .addr           = omap44xx_timer4_addrs,
5825         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5826 };
5827
5828 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5829         {
5830                 .pa_start       = 0x40138000,
5831                 .pa_end         = 0x4013807f,
5832                 .flags          = ADDR_TYPE_RT
5833         },
5834         { }
5835 };
5836
5837 /* l4_abe -> timer5 */
5838 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5839         .master         = &omap44xx_l4_abe_hwmod,
5840         .slave          = &omap44xx_timer5_hwmod,
5841         .clk            = "ocp_abe_iclk",
5842         .addr           = omap44xx_timer5_addrs,
5843         .user           = OCP_USER_MPU,
5844 };
5845
5846 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5847         {
5848                 .pa_start       = 0x49038000,
5849                 .pa_end         = 0x4903807f,
5850                 .flags          = ADDR_TYPE_RT
5851         },
5852         { }
5853 };
5854
5855 /* l4_abe -> timer5 (dma) */
5856 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5857         .master         = &omap44xx_l4_abe_hwmod,
5858         .slave          = &omap44xx_timer5_hwmod,
5859         .clk            = "ocp_abe_iclk",
5860         .addr           = omap44xx_timer5_dma_addrs,
5861         .user           = OCP_USER_SDMA,
5862 };
5863
5864 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5865         {
5866                 .pa_start       = 0x4013a000,
5867                 .pa_end         = 0x4013a07f,
5868                 .flags          = ADDR_TYPE_RT
5869         },
5870         { }
5871 };
5872
5873 /* l4_abe -> timer6 */
5874 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5875         .master         = &omap44xx_l4_abe_hwmod,
5876         .slave          = &omap44xx_timer6_hwmod,
5877         .clk            = "ocp_abe_iclk",
5878         .addr           = omap44xx_timer6_addrs,
5879         .user           = OCP_USER_MPU,
5880 };
5881
5882 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5883         {
5884                 .pa_start       = 0x4903a000,
5885                 .pa_end         = 0x4903a07f,
5886                 .flags          = ADDR_TYPE_RT
5887         },
5888         { }
5889 };
5890
5891 /* l4_abe -> timer6 (dma) */
5892 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5893         .master         = &omap44xx_l4_abe_hwmod,
5894         .slave          = &omap44xx_timer6_hwmod,
5895         .clk            = "ocp_abe_iclk",
5896         .addr           = omap44xx_timer6_dma_addrs,
5897         .user           = OCP_USER_SDMA,
5898 };
5899
5900 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5901         {
5902                 .pa_start       = 0x4013c000,
5903                 .pa_end         = 0x4013c07f,
5904                 .flags          = ADDR_TYPE_RT
5905         },
5906         { }
5907 };
5908
5909 /* l4_abe -> timer7 */
5910 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5911         .master         = &omap44xx_l4_abe_hwmod,
5912         .slave          = &omap44xx_timer7_hwmod,
5913         .clk            = "ocp_abe_iclk",
5914         .addr           = omap44xx_timer7_addrs,
5915         .user           = OCP_USER_MPU,
5916 };
5917
5918 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5919         {
5920                 .pa_start       = 0x4903c000,
5921                 .pa_end         = 0x4903c07f,
5922                 .flags          = ADDR_TYPE_RT
5923         },
5924         { }
5925 };
5926
5927 /* l4_abe -> timer7 (dma) */
5928 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5929         .master         = &omap44xx_l4_abe_hwmod,
5930         .slave          = &omap44xx_timer7_hwmod,
5931         .clk            = "ocp_abe_iclk",
5932         .addr           = omap44xx_timer7_dma_addrs,
5933         .user           = OCP_USER_SDMA,
5934 };
5935
5936 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5937         {
5938                 .pa_start       = 0x4013e000,
5939                 .pa_end         = 0x4013e07f,
5940                 .flags          = ADDR_TYPE_RT
5941         },
5942         { }
5943 };
5944
5945 /* l4_abe -> timer8 */
5946 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5947         .master         = &omap44xx_l4_abe_hwmod,
5948         .slave          = &omap44xx_timer8_hwmod,
5949         .clk            = "ocp_abe_iclk",
5950         .addr           = omap44xx_timer8_addrs,
5951         .user           = OCP_USER_MPU,
5952 };
5953
5954 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5955         {
5956                 .pa_start       = 0x4903e000,
5957                 .pa_end         = 0x4903e07f,
5958                 .flags          = ADDR_TYPE_RT
5959         },
5960         { }
5961 };
5962
5963 /* l4_abe -> timer8 (dma) */
5964 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5965         .master         = &omap44xx_l4_abe_hwmod,
5966         .slave          = &omap44xx_timer8_hwmod,
5967         .clk            = "ocp_abe_iclk",
5968         .addr           = omap44xx_timer8_dma_addrs,
5969         .user           = OCP_USER_SDMA,
5970 };
5971
5972 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5973         {
5974                 .pa_start       = 0x4803e000,
5975                 .pa_end         = 0x4803e07f,
5976                 .flags          = ADDR_TYPE_RT
5977         },
5978         { }
5979 };
5980
5981 /* l4_per -> timer9 */
5982 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5983         .master         = &omap44xx_l4_per_hwmod,
5984         .slave          = &omap44xx_timer9_hwmod,
5985         .clk            = "l4_div_ck",
5986         .addr           = omap44xx_timer9_addrs,
5987         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5988 };
5989
5990 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5991         {
5992                 .pa_start       = 0x48086000,
5993                 .pa_end         = 0x4808607f,
5994                 .flags          = ADDR_TYPE_RT
5995         },
5996         { }
5997 };
5998
5999 /* l4_per -> timer10 */
6000 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6001         .master         = &omap44xx_l4_per_hwmod,
6002         .slave          = &omap44xx_timer10_hwmod,
6003         .clk            = "l4_div_ck",
6004         .addr           = omap44xx_timer10_addrs,
6005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6006 };
6007
6008 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6009         {
6010                 .pa_start       = 0x48088000,
6011                 .pa_end         = 0x4808807f,
6012                 .flags          = ADDR_TYPE_RT
6013         },
6014         { }
6015 };
6016
6017 /* l4_per -> timer11 */
6018 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6019         .master         = &omap44xx_l4_per_hwmod,
6020         .slave          = &omap44xx_timer11_hwmod,
6021         .clk            = "l4_div_ck",
6022         .addr           = omap44xx_timer11_addrs,
6023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6024 };
6025
6026 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6027         {
6028                 .pa_start       = 0x4806a000,
6029                 .pa_end         = 0x4806a0ff,
6030                 .flags          = ADDR_TYPE_RT
6031         },
6032         { }
6033 };
6034
6035 /* l4_per -> uart1 */
6036 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6037         .master         = &omap44xx_l4_per_hwmod,
6038         .slave          = &omap44xx_uart1_hwmod,
6039         .clk            = "l4_div_ck",
6040         .addr           = omap44xx_uart1_addrs,
6041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6042 };
6043
6044 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6045         {
6046                 .pa_start       = 0x4806c000,
6047                 .pa_end         = 0x4806c0ff,
6048                 .flags          = ADDR_TYPE_RT
6049         },
6050         { }
6051 };
6052
6053 /* l4_per -> uart2 */
6054 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6055         .master         = &omap44xx_l4_per_hwmod,
6056         .slave          = &omap44xx_uart2_hwmod,
6057         .clk            = "l4_div_ck",
6058         .addr           = omap44xx_uart2_addrs,
6059         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6060 };
6061
6062 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6063         {
6064                 .pa_start       = 0x48020000,
6065                 .pa_end         = 0x480200ff,
6066                 .flags          = ADDR_TYPE_RT
6067         },
6068         { }
6069 };
6070
6071 /* l4_per -> uart3 */
6072 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6073         .master         = &omap44xx_l4_per_hwmod,
6074         .slave          = &omap44xx_uart3_hwmod,
6075         .clk            = "l4_div_ck",
6076         .addr           = omap44xx_uart3_addrs,
6077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6078 };
6079
6080 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6081         {
6082                 .pa_start       = 0x4806e000,
6083                 .pa_end         = 0x4806e0ff,
6084                 .flags          = ADDR_TYPE_RT
6085         },
6086         { }
6087 };
6088
6089 /* l4_per -> uart4 */
6090 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6091         .master         = &omap44xx_l4_per_hwmod,
6092         .slave          = &omap44xx_uart4_hwmod,
6093         .clk            = "l4_div_ck",
6094         .addr           = omap44xx_uart4_addrs,
6095         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6096 };
6097
6098 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6099         {
6100                 .pa_start       = 0x4a0a9000,
6101                 .pa_end         = 0x4a0a93ff,
6102                 .flags          = ADDR_TYPE_RT
6103         },
6104         { }
6105 };
6106
6107 /* l4_cfg -> usb_host_fs */
6108 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6109         .master         = &omap44xx_l4_cfg_hwmod,
6110         .slave          = &omap44xx_usb_host_fs_hwmod,
6111         .clk            = "l4_div_ck",
6112         .addr           = omap44xx_usb_host_fs_addrs,
6113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6114 };
6115
6116 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6117         {
6118                 .name           = "uhh",
6119                 .pa_start       = 0x4a064000,
6120                 .pa_end         = 0x4a0647ff,
6121                 .flags          = ADDR_TYPE_RT
6122         },
6123         {
6124                 .name           = "ohci",
6125                 .pa_start       = 0x4a064800,
6126                 .pa_end         = 0x4a064bff,
6127         },
6128         {
6129                 .name           = "ehci",
6130                 .pa_start       = 0x4a064c00,
6131                 .pa_end         = 0x4a064fff,
6132         },
6133         {}
6134 };
6135
6136 /* l4_cfg -> usb_host_hs */
6137 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6138         .master         = &omap44xx_l4_cfg_hwmod,
6139         .slave          = &omap44xx_usb_host_hs_hwmod,
6140         .clk            = "l4_div_ck",
6141         .addr           = omap44xx_usb_host_hs_addrs,
6142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6143 };
6144
6145 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6146         {
6147                 .pa_start       = 0x4a0ab000,
6148                 .pa_end         = 0x4a0ab7ff,
6149                 .flags          = ADDR_TYPE_RT
6150         },
6151         { }
6152 };
6153
6154 /* l4_cfg -> usb_otg_hs */
6155 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6156         .master         = &omap44xx_l4_cfg_hwmod,
6157         .slave          = &omap44xx_usb_otg_hs_hwmod,
6158         .clk            = "l4_div_ck",
6159         .addr           = omap44xx_usb_otg_hs_addrs,
6160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6161 };
6162
6163 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6164         {
6165                 .name           = "tll",
6166                 .pa_start       = 0x4a062000,
6167                 .pa_end         = 0x4a063fff,
6168                 .flags          = ADDR_TYPE_RT
6169         },
6170         {}
6171 };
6172
6173 /* l4_cfg -> usb_tll_hs */
6174 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6175         .master         = &omap44xx_l4_cfg_hwmod,
6176         .slave          = &omap44xx_usb_tll_hs_hwmod,
6177         .clk            = "l4_div_ck",
6178         .addr           = omap44xx_usb_tll_hs_addrs,
6179         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6180 };
6181
6182 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6183         {
6184                 .pa_start       = 0x4a314000,
6185                 .pa_end         = 0x4a31407f,
6186                 .flags          = ADDR_TYPE_RT
6187         },
6188         { }
6189 };
6190
6191 /* l4_wkup -> wd_timer2 */
6192 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6193         .master         = &omap44xx_l4_wkup_hwmod,
6194         .slave          = &omap44xx_wd_timer2_hwmod,
6195         .clk            = "l4_wkup_clk_mux_ck",
6196         .addr           = omap44xx_wd_timer2_addrs,
6197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6198 };
6199
6200 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6201         {
6202                 .pa_start       = 0x40130000,
6203                 .pa_end         = 0x4013007f,
6204                 .flags          = ADDR_TYPE_RT
6205         },
6206         { }
6207 };
6208
6209 /* l4_abe -> wd_timer3 */
6210 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6211         .master         = &omap44xx_l4_abe_hwmod,
6212         .slave          = &omap44xx_wd_timer3_hwmod,
6213         .clk            = "ocp_abe_iclk",
6214         .addr           = omap44xx_wd_timer3_addrs,
6215         .user           = OCP_USER_MPU,
6216 };
6217
6218 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6219         {
6220                 .pa_start       = 0x49030000,
6221                 .pa_end         = 0x4903007f,
6222                 .flags          = ADDR_TYPE_RT
6223         },
6224         { }
6225 };
6226
6227 /* l4_abe -> wd_timer3 (dma) */
6228 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6229         .master         = &omap44xx_l4_abe_hwmod,
6230         .slave          = &omap44xx_wd_timer3_hwmod,
6231         .clk            = "ocp_abe_iclk",
6232         .addr           = omap44xx_wd_timer3_dma_addrs,
6233         .user           = OCP_USER_SDMA,
6234 };
6235
6236 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6237         &omap44xx_c2c__c2c_target_fw,
6238         &omap44xx_l4_cfg__c2c_target_fw,
6239         &omap44xx_l3_main_1__dmm,
6240         &omap44xx_mpu__dmm,
6241         &omap44xx_c2c__emif_fw,
6242         &omap44xx_dmm__emif_fw,
6243         &omap44xx_l4_cfg__emif_fw,
6244         &omap44xx_iva__l3_instr,
6245         &omap44xx_l3_main_3__l3_instr,
6246         &omap44xx_ocp_wp_noc__l3_instr,
6247         &omap44xx_dsp__l3_main_1,
6248         &omap44xx_dss__l3_main_1,
6249         &omap44xx_l3_main_2__l3_main_1,
6250         &omap44xx_l4_cfg__l3_main_1,
6251         &omap44xx_mmc1__l3_main_1,
6252         &omap44xx_mmc2__l3_main_1,
6253         &omap44xx_mpu__l3_main_1,
6254         &omap44xx_c2c_target_fw__l3_main_2,
6255         &omap44xx_debugss__l3_main_2,
6256         &omap44xx_dma_system__l3_main_2,
6257         &omap44xx_fdif__l3_main_2,
6258         &omap44xx_gpu__l3_main_2,
6259         &omap44xx_hsi__l3_main_2,
6260         &omap44xx_ipu__l3_main_2,
6261         &omap44xx_iss__l3_main_2,
6262         &omap44xx_iva__l3_main_2,
6263         &omap44xx_l3_main_1__l3_main_2,
6264         &omap44xx_l4_cfg__l3_main_2,
6265         /* &omap44xx_usb_host_fs__l3_main_2, */
6266         &omap44xx_usb_host_hs__l3_main_2,
6267         &omap44xx_usb_otg_hs__l3_main_2,
6268         &omap44xx_l3_main_1__l3_main_3,
6269         &omap44xx_l3_main_2__l3_main_3,
6270         &omap44xx_l4_cfg__l3_main_3,
6271         /* &omap44xx_aess__l4_abe, */
6272         &omap44xx_dsp__l4_abe,
6273         &omap44xx_l3_main_1__l4_abe,
6274         &omap44xx_mpu__l4_abe,
6275         &omap44xx_l3_main_1__l4_cfg,
6276         &omap44xx_l3_main_2__l4_per,
6277         &omap44xx_l4_cfg__l4_wkup,
6278         &omap44xx_mpu__mpu_private,
6279         &omap44xx_l4_cfg__ocp_wp_noc,
6280         /* &omap44xx_l4_abe__aess, */
6281         /* &omap44xx_l4_abe__aess_dma, */
6282         &omap44xx_l3_main_2__c2c,
6283         &omap44xx_l4_wkup__counter_32k,
6284         &omap44xx_l4_cfg__ctrl_module_core,
6285         &omap44xx_l4_cfg__ctrl_module_pad_core,
6286         &omap44xx_l4_wkup__ctrl_module_wkup,
6287         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6288         &omap44xx_l3_instr__debugss,
6289         &omap44xx_l4_cfg__dma_system,
6290         &omap44xx_l4_abe__dmic,
6291         &omap44xx_l4_abe__dmic_dma,
6292         &omap44xx_dsp__iva,
6293         /* &omap44xx_dsp__sl2if, */
6294         &omap44xx_l4_cfg__dsp,
6295         &omap44xx_l3_main_2__dss,
6296         &omap44xx_l4_per__dss,
6297         &omap44xx_l3_main_2__dss_dispc,
6298         &omap44xx_l4_per__dss_dispc,
6299         &omap44xx_l3_main_2__dss_dsi1,
6300         &omap44xx_l4_per__dss_dsi1,
6301         &omap44xx_l3_main_2__dss_dsi2,
6302         &omap44xx_l4_per__dss_dsi2,
6303         &omap44xx_l3_main_2__dss_hdmi,
6304         &omap44xx_l4_per__dss_hdmi,
6305         &omap44xx_l3_main_2__dss_rfbi,
6306         &omap44xx_l4_per__dss_rfbi,
6307         &omap44xx_l3_main_2__dss_venc,
6308         &omap44xx_l4_per__dss_venc,
6309         &omap44xx_l4_per__elm,
6310         &omap44xx_emif_fw__emif1,
6311         &omap44xx_emif_fw__emif2,
6312         &omap44xx_l4_cfg__fdif,
6313         &omap44xx_l4_wkup__gpio1,
6314         &omap44xx_l4_per__gpio2,
6315         &omap44xx_l4_per__gpio3,
6316         &omap44xx_l4_per__gpio4,
6317         &omap44xx_l4_per__gpio5,
6318         &omap44xx_l4_per__gpio6,
6319         &omap44xx_l3_main_2__gpmc,
6320         &omap44xx_l3_main_2__gpu,
6321         &omap44xx_l4_per__hdq1w,
6322         &omap44xx_l4_cfg__hsi,
6323         &omap44xx_l4_per__i2c1,
6324         &omap44xx_l4_per__i2c2,
6325         &omap44xx_l4_per__i2c3,
6326         &omap44xx_l4_per__i2c4,
6327         &omap44xx_l3_main_2__ipu,
6328         &omap44xx_l3_main_2__iss,
6329         /* &omap44xx_iva__sl2if, */
6330         &omap44xx_l3_main_2__iva,
6331         &omap44xx_l4_wkup__kbd,
6332         &omap44xx_l4_cfg__mailbox,
6333         &omap44xx_l4_abe__mcasp,
6334         &omap44xx_l4_abe__mcasp_dma,
6335         &omap44xx_l4_abe__mcbsp1,
6336         &omap44xx_l4_abe__mcbsp1_dma,
6337         &omap44xx_l4_abe__mcbsp2,
6338         &omap44xx_l4_abe__mcbsp2_dma,
6339         &omap44xx_l4_abe__mcbsp3,
6340         &omap44xx_l4_abe__mcbsp3_dma,
6341         &omap44xx_l4_per__mcbsp4,
6342         &omap44xx_l4_abe__mcpdm,
6343         &omap44xx_l4_abe__mcpdm_dma,
6344         &omap44xx_l4_per__mcspi1,
6345         &omap44xx_l4_per__mcspi2,
6346         &omap44xx_l4_per__mcspi3,
6347         &omap44xx_l4_per__mcspi4,
6348         &omap44xx_l4_per__mmc1,
6349         &omap44xx_l4_per__mmc2,
6350         &omap44xx_l4_per__mmc3,
6351         &omap44xx_l4_per__mmc4,
6352         &omap44xx_l4_per__mmc5,
6353         &omap44xx_l3_main_2__mmu_ipu,
6354         &omap44xx_l4_cfg__mmu_dsp,
6355         &omap44xx_l3_main_2__ocmc_ram,
6356         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6357         &omap44xx_mpu_private__prcm_mpu,
6358         &omap44xx_l4_wkup__cm_core_aon,
6359         &omap44xx_l4_cfg__cm_core,
6360         &omap44xx_l4_wkup__prm,
6361         &omap44xx_l4_wkup__scrm,
6362         /* &omap44xx_l3_main_2__sl2if, */
6363         &omap44xx_l4_abe__slimbus1,
6364         &omap44xx_l4_abe__slimbus1_dma,
6365         &omap44xx_l4_per__slimbus2,
6366         &omap44xx_l4_cfg__smartreflex_core,
6367         &omap44xx_l4_cfg__smartreflex_iva,
6368         &omap44xx_l4_cfg__smartreflex_mpu,
6369         &omap44xx_l4_cfg__spinlock,
6370         &omap44xx_l4_wkup__timer1,
6371         &omap44xx_l4_per__timer2,
6372         &omap44xx_l4_per__timer3,
6373         &omap44xx_l4_per__timer4,
6374         &omap44xx_l4_abe__timer5,
6375         &omap44xx_l4_abe__timer5_dma,
6376         &omap44xx_l4_abe__timer6,
6377         &omap44xx_l4_abe__timer6_dma,
6378         &omap44xx_l4_abe__timer7,
6379         &omap44xx_l4_abe__timer7_dma,
6380         &omap44xx_l4_abe__timer8,
6381         &omap44xx_l4_abe__timer8_dma,
6382         &omap44xx_l4_per__timer9,
6383         &omap44xx_l4_per__timer10,
6384         &omap44xx_l4_per__timer11,
6385         &omap44xx_l4_per__uart1,
6386         &omap44xx_l4_per__uart2,
6387         &omap44xx_l4_per__uart3,
6388         &omap44xx_l4_per__uart4,
6389         /* &omap44xx_l4_cfg__usb_host_fs, */
6390         &omap44xx_l4_cfg__usb_host_hs,
6391         &omap44xx_l4_cfg__usb_otg_hs,
6392         &omap44xx_l4_cfg__usb_tll_hs,
6393         &omap44xx_l4_wkup__wd_timer2,
6394         &omap44xx_l4_abe__wd_timer3,
6395         &omap44xx_l4_abe__wd_timer3_dma,
6396         NULL,
6397 };
6398
6399 int __init omap44xx_hwmod_init(void)
6400 {
6401         omap_hwmod_init();
6402         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6403 }
6404