arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/i2c.h>
  32
  33 #include "omap_hwmod_common_data.h"
  34
  35 #include "cm1_44xx.h"
  36 #include "cm2_44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "wd_timer.h"
  40
  41 /* Base offset for all OMAP4 interrupts external to MPUSS */
  42 #define OMAP44XX_IRQ_GIC_START  32
  43
  44 /* Base offset for all OMAP4 dma requests */
  45 #define OMAP44XX_DMA_REQ_START  1
  46
  47 /* Backward references (IPs with Bus Master capability) */
  48 static struct omap_hwmod omap44xx_aess_hwmod;
  49 static struct omap_hwmod omap44xx_dma_system_hwmod;
  50 static struct omap_hwmod omap44xx_dmm_hwmod;
  51 static struct omap_hwmod omap44xx_dsp_hwmod;
  52 static struct omap_hwmod omap44xx_dss_hwmod;
  53 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  54 static struct omap_hwmod omap44xx_hsi_hwmod;
  55 static struct omap_hwmod omap44xx_ipu_hwmod;
  56 static struct omap_hwmod omap44xx_iss_hwmod;
  57 static struct omap_hwmod omap44xx_iva_hwmod;
  58 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  59 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  60 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  61 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  62 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  63 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  64 static struct omap_hwmod omap44xx_l4_per_hwmod;
  65 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  66 static struct omap_hwmod omap44xx_mmc1_hwmod;
  67 static struct omap_hwmod omap44xx_mmc2_hwmod;
  68 static struct omap_hwmod omap44xx_mpu_hwmod;
  69 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  70 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  71
  72 /*
  73  * Interconnects omap_hwmod structures
  74  * hwmods that compose the global OMAP interconnect
  75  */
  76
  77 /*
  78  * 'dmm' class
  79  * instance(s): dmm
  80  */
  81 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  82         .name   = "dmm",
  83 };
  84
  85 /* dmm */
  86 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  87         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  88         { .irq = -1 }
  89 };
  90
  91 /* l3_main_1 -> dmm */
  92 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  93         .master         = &omap44xx_l3_main_1_hwmod,
  94         .slave          = &omap44xx_dmm_hwmod,
  95         .clk            = "l3_div_ck",
  96         .user           = OCP_USER_SDMA,
  97 };
  98
  99 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
 100         {
 101                 .pa_start       = 0x4e000000,
 102                 .pa_end         = 0x4e0007ff,
 103                 .flags          = ADDR_TYPE_RT
 104         },
 105         { }
 106 };
 107
 108 /* mpu -> dmm */
 109 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 110         .master         = &omap44xx_mpu_hwmod,
 111         .slave          = &omap44xx_dmm_hwmod,
 112         .clk            = "l3_div_ck",
 113         .addr           = omap44xx_dmm_addrs,
 114         .user           = OCP_USER_MPU,
 115 };
 116
 117 /* dmm slave ports */
 118 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 119         &omap44xx_l3_main_1__dmm,
 120         &omap44xx_mpu__dmm,
 121 };
 122
 123 static struct omap_hwmod omap44xx_dmm_hwmod = {
 124         .name           = "dmm",
 125         .class          = &omap44xx_dmm_hwmod_class,
 126         .clkdm_name     = "l3_emif_clkdm",
 127         .slaves         = omap44xx_dmm_slaves,
 128         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 129         .mpu_irqs       = omap44xx_dmm_irqs,
 130         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 131 };
 132
 133 /*
 134  * 'emif_fw' class
 135  * instance(s): emif_fw
 136  */
 137 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 138         .name   = "emif_fw",
 139 };
 140
 141 /* emif_fw */
 142 /* dmm -> emif_fw */
 143 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 144         .master         = &omap44xx_dmm_hwmod,
 145         .slave          = &omap44xx_emif_fw_hwmod,
 146         .clk            = "l3_div_ck",
 147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 148 };
 149
 150 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 151         {
 152                 .pa_start       = 0x4a20c000,
 153                 .pa_end         = 0x4a20c0ff,
 154                 .flags          = ADDR_TYPE_RT
 155         },
 156         { }
 157 };
 158
 159 /* l4_cfg -> emif_fw */
 160 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 161         .master         = &omap44xx_l4_cfg_hwmod,
 162         .slave          = &omap44xx_emif_fw_hwmod,
 163         .clk            = "l4_div_ck",
 164         .addr           = omap44xx_emif_fw_addrs,
 165         .user           = OCP_USER_MPU,
 166 };
 167
 168 /* emif_fw slave ports */
 169 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 170         &omap44xx_dmm__emif_fw,
 171         &omap44xx_l4_cfg__emif_fw,
 172 };
 173
 174 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 175         .name           = "emif_fw",
 176         .class          = &omap44xx_emif_fw_hwmod_class,
 177         .clkdm_name     = "l3_emif_clkdm",
 178         .slaves         = omap44xx_emif_fw_slaves,
 179         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 180         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 181 };
 182
 183 /*
 184  * 'l3' class
 185  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 186  */
 187 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 188         .name   = "l3",
 189 };
 190
 191 /* l3_instr */
 192 /* iva -> l3_instr */
 193 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 194         .master         = &omap44xx_iva_hwmod,
 195         .slave          = &omap44xx_l3_instr_hwmod,
 196         .clk            = "l3_div_ck",
 197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 198 };
 199
 200 /* l3_main_3 -> l3_instr */
 201 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 202         .master         = &omap44xx_l3_main_3_hwmod,
 203         .slave          = &omap44xx_l3_instr_hwmod,
 204         .clk            = "l3_div_ck",
 205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 206 };
 207
 208 /* l3_instr slave ports */
 209 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 210         &omap44xx_iva__l3_instr,
 211         &omap44xx_l3_main_3__l3_instr,
 212 };
 213
 214 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 215         .name           = "l3_instr",
 216         .class          = &omap44xx_l3_hwmod_class,
 217         .clkdm_name     = "l3_instr_clkdm",
 218         .slaves         = omap44xx_l3_instr_slaves,
 219         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 220         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 221 };
 222
 223 /* l3_main_1 */
 224 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 225         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 226         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 227         { .irq = -1 }
 228 };
 229
 230 /* dsp -> l3_main_1 */
 231 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 232         .master         = &omap44xx_dsp_hwmod,
 233         .slave          = &omap44xx_l3_main_1_hwmod,
 234         .clk            = "l3_div_ck",
 235         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 236 };
 237
 238 /* dss -> l3_main_1 */
 239 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 240         .master         = &omap44xx_dss_hwmod,
 241         .slave          = &omap44xx_l3_main_1_hwmod,
 242         .clk            = "l3_div_ck",
 243         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 244 };
 245
 246 /* l3_main_2 -> l3_main_1 */
 247 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 248         .master         = &omap44xx_l3_main_2_hwmod,
 249         .slave          = &omap44xx_l3_main_1_hwmod,
 250         .clk            = "l3_div_ck",
 251         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 252 };
 253
 254 /* l4_cfg -> l3_main_1 */
 255 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 256         .master         = &omap44xx_l4_cfg_hwmod,
 257         .slave          = &omap44xx_l3_main_1_hwmod,
 258         .clk            = "l4_div_ck",
 259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 260 };
 261
 262 /* mmc1 -> l3_main_1 */
 263 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 264         .master         = &omap44xx_mmc1_hwmod,
 265         .slave          = &omap44xx_l3_main_1_hwmod,
 266         .clk            = "l3_div_ck",
 267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 268 };
 269
 270 /* mmc2 -> l3_main_1 */
 271 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 272         .master         = &omap44xx_mmc2_hwmod,
 273         .slave          = &omap44xx_l3_main_1_hwmod,
 274         .clk            = "l3_div_ck",
 275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 276 };
 277
 278 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 279         {
 280                 .pa_start       = 0x44000000,
 281                 .pa_end         = 0x44000fff,
 282                 .flags          = ADDR_TYPE_RT
 283         },
 284         { }
 285 };
 286
 287 /* mpu -> l3_main_1 */
 288 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 289         .master         = &omap44xx_mpu_hwmod,
 290         .slave          = &omap44xx_l3_main_1_hwmod,
 291         .clk            = "l3_div_ck",
 292         .addr           = omap44xx_l3_main_1_addrs,
 293         .user           = OCP_USER_MPU,
 294 };
 295
 296 /* l3_main_1 slave ports */
 297 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 298         &omap44xx_dsp__l3_main_1,
 299         &omap44xx_dss__l3_main_1,
 300         &omap44xx_l3_main_2__l3_main_1,
 301         &omap44xx_l4_cfg__l3_main_1,
 302         &omap44xx_mmc1__l3_main_1,
 303         &omap44xx_mmc2__l3_main_1,
 304         &omap44xx_mpu__l3_main_1,
 305 };
 306
 307 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 308         .name           = "l3_main_1",
 309         .class          = &omap44xx_l3_hwmod_class,
 310         .clkdm_name     = "l3_1_clkdm",
 311         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 312         .slaves         = omap44xx_l3_main_1_slaves,
 313         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 314         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 315 };
 316
 317 /* l3_main_2 */
 318 /* dma_system -> l3_main_2 */
 319 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 320         .master         = &omap44xx_dma_system_hwmod,
 321         .slave          = &omap44xx_l3_main_2_hwmod,
 322         .clk            = "l3_div_ck",
 323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 324 };
 325
 326 /* hsi -> l3_main_2 */
 327 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 328         .master         = &omap44xx_hsi_hwmod,
 329         .slave          = &omap44xx_l3_main_2_hwmod,
 330         .clk            = "l3_div_ck",
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 /* ipu -> l3_main_2 */
 335 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 336         .master         = &omap44xx_ipu_hwmod,
 337         .slave          = &omap44xx_l3_main_2_hwmod,
 338         .clk            = "l3_div_ck",
 339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 340 };
 341
 342 /* iss -> l3_main_2 */
 343 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 344         .master         = &omap44xx_iss_hwmod,
 345         .slave          = &omap44xx_l3_main_2_hwmod,
 346         .clk            = "l3_div_ck",
 347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 348 };
 349
 350 /* iva -> l3_main_2 */
 351 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 352         .master         = &omap44xx_iva_hwmod,
 353         .slave          = &omap44xx_l3_main_2_hwmod,
 354         .clk            = "l3_div_ck",
 355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 356 };
 357
 358 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 359         {
 360                 .pa_start       = 0x44800000,
 361                 .pa_end         = 0x44801fff,
 362                 .flags          = ADDR_TYPE_RT
 363         },
 364         { }
 365 };
 366
 367 /* l3_main_1 -> l3_main_2 */
 368 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 369         .master         = &omap44xx_l3_main_1_hwmod,
 370         .slave          = &omap44xx_l3_main_2_hwmod,
 371         .clk            = "l3_div_ck",
 372         .addr           = omap44xx_l3_main_2_addrs,
 373         .user           = OCP_USER_MPU,
 374 };
 375
 376 /* l4_cfg -> l3_main_2 */
 377 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 378         .master         = &omap44xx_l4_cfg_hwmod,
 379         .slave          = &omap44xx_l3_main_2_hwmod,
 380         .clk            = "l4_div_ck",
 381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 382 };
 383
 384 /* usb_otg_hs -> l3_main_2 */
 385 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 386         .master         = &omap44xx_usb_otg_hs_hwmod,
 387         .slave          = &omap44xx_l3_main_2_hwmod,
 388         .clk            = "l3_div_ck",
 389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 390 };
 391
 392 /* l3_main_2 slave ports */
 393 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 394         &omap44xx_dma_system__l3_main_2,
 395         &omap44xx_hsi__l3_main_2,
 396         &omap44xx_ipu__l3_main_2,
 397         &omap44xx_iss__l3_main_2,
 398         &omap44xx_iva__l3_main_2,
 399         &omap44xx_l3_main_1__l3_main_2,
 400         &omap44xx_l4_cfg__l3_main_2,
 401         &omap44xx_usb_otg_hs__l3_main_2,
 402 };
 403
 404 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 405         .name           = "l3_main_2",
 406         .class          = &omap44xx_l3_hwmod_class,
 407         .clkdm_name     = "l3_2_clkdm",
 408         .slaves         = omap44xx_l3_main_2_slaves,
 409         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 410         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 411 };
 412
 413 /* l3_main_3 */
 414 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 415         {
 416                 .pa_start       = 0x45000000,
 417                 .pa_end         = 0x45000fff,
 418                 .flags          = ADDR_TYPE_RT
 419         },
 420         { }
 421 };
 422
 423 /* l3_main_1 -> l3_main_3 */
 424 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 425         .master         = &omap44xx_l3_main_1_hwmod,
 426         .slave          = &omap44xx_l3_main_3_hwmod,
 427         .clk            = "l3_div_ck",
 428         .addr           = omap44xx_l3_main_3_addrs,
 429         .user           = OCP_USER_MPU,
 430 };
 431
 432 /* l3_main_2 -> l3_main_3 */
 433 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 434         .master         = &omap44xx_l3_main_2_hwmod,
 435         .slave          = &omap44xx_l3_main_3_hwmod,
 436         .clk            = "l3_div_ck",
 437         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 438 };
 439
 440 /* l4_cfg -> l3_main_3 */
 441 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 442         .master         = &omap44xx_l4_cfg_hwmod,
 443         .slave          = &omap44xx_l3_main_3_hwmod,
 444         .clk            = "l4_div_ck",
 445         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 446 };
 447
 448 /* l3_main_3 slave ports */
 449 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 450         &omap44xx_l3_main_1__l3_main_3,
 451         &omap44xx_l3_main_2__l3_main_3,
 452         &omap44xx_l4_cfg__l3_main_3,
 453 };
 454
 455 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 456         .name           = "l3_main_3",
 457         .class          = &omap44xx_l3_hwmod_class,
 458         .clkdm_name     = "l3_instr_clkdm",
 459         .slaves         = omap44xx_l3_main_3_slaves,
 460         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 461         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 462 };
 463
 464 /*
 465  * 'l4' class
 466  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 467  */
 468 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 469         .name   = "l4",
 470 };
 471
 472 /* l4_abe */
 473 /* aess -> l4_abe */
 474 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 475         .master         = &omap44xx_aess_hwmod,
 476         .slave          = &omap44xx_l4_abe_hwmod,
 477         .clk            = "ocp_abe_iclk",
 478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 479 };
 480
 481 /* dsp -> l4_abe */
 482 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 483         .master         = &omap44xx_dsp_hwmod,
 484         .slave          = &omap44xx_l4_abe_hwmod,
 485         .clk            = "ocp_abe_iclk",
 486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 487 };
 488
 489 /* l3_main_1 -> l4_abe */
 490 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 491         .master         = &omap44xx_l3_main_1_hwmod,
 492         .slave          = &omap44xx_l4_abe_hwmod,
 493         .clk            = "l3_div_ck",
 494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 495 };
 496
 497 /* mpu -> l4_abe */
 498 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 499         .master         = &omap44xx_mpu_hwmod,
 500         .slave          = &omap44xx_l4_abe_hwmod,
 501         .clk            = "ocp_abe_iclk",
 502         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 503 };
 504
 505 /* l4_abe slave ports */
 506 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 507         &omap44xx_aess__l4_abe,
 508         &omap44xx_dsp__l4_abe,
 509         &omap44xx_l3_main_1__l4_abe,
 510         &omap44xx_mpu__l4_abe,
 511 };
 512
 513 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 514         .name           = "l4_abe",
 515         .class          = &omap44xx_l4_hwmod_class,
 516         .clkdm_name     = "abe_clkdm",
 517         .slaves         = omap44xx_l4_abe_slaves,
 518         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 519         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 520 };
 521
 522 /* l4_cfg */
 523 /* l3_main_1 -> l4_cfg */
 524 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 525         .master         = &omap44xx_l3_main_1_hwmod,
 526         .slave          = &omap44xx_l4_cfg_hwmod,
 527         .clk            = "l3_div_ck",
 528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 529 };
 530
 531 /* l4_cfg slave ports */
 532 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 533         &omap44xx_l3_main_1__l4_cfg,
 534 };
 535
 536 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 537         .name           = "l4_cfg",
 538         .class          = &omap44xx_l4_hwmod_class,
 539         .clkdm_name     = "l4_cfg_clkdm",
 540         .slaves         = omap44xx_l4_cfg_slaves,
 541         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 542         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 543 };
 544
 545 /* l4_per */
 546 /* l3_main_2 -> l4_per */
 547 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 548         .master         = &omap44xx_l3_main_2_hwmod,
 549         .slave          = &omap44xx_l4_per_hwmod,
 550         .clk            = "l3_div_ck",
 551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 552 };
 553
 554 /* l4_per slave ports */
 555 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 556         &omap44xx_l3_main_2__l4_per,
 557 };
 558
 559 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 560         .name           = "l4_per",
 561         .class          = &omap44xx_l4_hwmod_class,
 562         .clkdm_name     = "l4_per_clkdm",
 563         .slaves         = omap44xx_l4_per_slaves,
 564         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 565         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 566 };
 567
 568 /* l4_wkup */
 569 /* l4_cfg -> l4_wkup */
 570 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 571         .master         = &omap44xx_l4_cfg_hwmod,
 572         .slave          = &omap44xx_l4_wkup_hwmod,
 573         .clk            = "l4_div_ck",
 574         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 575 };
 576
 577 /* l4_wkup slave ports */
 578 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 579         &omap44xx_l4_cfg__l4_wkup,
 580 };
 581
 582 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 583         .name           = "l4_wkup",
 584         .class          = &omap44xx_l4_hwmod_class,
 585         .clkdm_name     = "l4_wkup_clkdm",
 586         .slaves         = omap44xx_l4_wkup_slaves,
 587         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 588         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 589 };
 590
 591 /*
 592  * 'mpu_bus' class
 593  * instance(s): mpu_private
 594  */
 595 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 596         .name   = "mpu_bus",
 597 };
 598
 599 /* mpu_private */
 600 /* mpu -> mpu_private */
 601 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 602         .master         = &omap44xx_mpu_hwmod,
 603         .slave          = &omap44xx_mpu_private_hwmod,
 604         .clk            = "l3_div_ck",
 605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 606 };
 607
 608 /* mpu_private slave ports */
 609 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 610         &omap44xx_mpu__mpu_private,
 611 };
 612
 613 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 614         .name           = "mpu_private",
 615         .class          = &omap44xx_mpu_bus_hwmod_class,
 616         .clkdm_name     = "mpuss_clkdm",
 617         .slaves         = omap44xx_mpu_private_slaves,
 618         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 619         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 620 };
 621
 622 /*
 623  * Modules omap_hwmod structures
 624  *
 625  * The following IPs are excluded for the moment because:
 626  * - They do not need an explicit SW control using omap_hwmod API.
 627  * - They still need to be validated with the driver
 628  *   properly adapted to omap_hwmod / omap_device
 629  *
 630  *  c2c
 631  *  c2c_target_fw
 632  *  cm_core
 633  *  cm_core_aon
 634  *  ctrl_module_core
 635  *  ctrl_module_pad_core
 636  *  ctrl_module_pad_wkup
 637  *  ctrl_module_wkup
 638  *  debugss
 639  *  efuse_ctrl_cust
 640  *  efuse_ctrl_std
 641  *  elm
 642  *  emif1
 643  *  emif2
 644  *  fdif
 645  *  gpmc
 646  *  gpu
 647  *  hdq1w
 648  *  mcasp
 649  *  mpu_c0
 650  *  mpu_c1
 651  *  ocmc_ram
 652  *  ocp2scp_usb_phy
 653  *  ocp_wp_noc
 654  *  prcm_mpu
 655  *  prm
 656  *  scrm
 657  *  sl2if
 658  *  slimbus1
 659  *  slimbus2
 660  *  usb_host_fs
 661  *  usb_host_hs
 662  *  usb_phy_cm
 663  *  usb_tll_hs
 664  *  usim
 665  */
 666
 667 /*
 668  * 'aess' class
 669  * audio engine sub system
 670  */
 671
 672 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 673         .rev_offs       = 0x0000,
 674         .sysc_offs      = 0x0010,
 675         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 676         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 677                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 678                            MSTANDBY_SMART_WKUP),
 679         .sysc_fields    = &omap_hwmod_sysc_type2,
 680 };
 681
 682 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 683         .name   = "aess",
 684         .sysc   = &omap44xx_aess_sysc,
 685 };
 686
 687 /* aess */
 688 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 689         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 690         { .irq = -1 }
 691 };
 692
 693 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 694         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 695         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 696         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 697         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 698         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 699         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 700         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 701         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 702         { .dma_req = -1 }
 703 };
 704
 705 /* aess master ports */
 706 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 707         &omap44xx_aess__l4_abe,
 708 };
 709
 710 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 711         {
 712                 .pa_start       = 0x401f1000,
 713                 .pa_end         = 0x401f13ff,
 714                 .flags          = ADDR_TYPE_RT
 715         },
 716         { }
 717 };
 718
 719 /* l4_abe -> aess */
 720 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 721         .master         = &omap44xx_l4_abe_hwmod,
 722         .slave          = &omap44xx_aess_hwmod,
 723         .clk            = "ocp_abe_iclk",
 724         .addr           = omap44xx_aess_addrs,
 725         .user           = OCP_USER_MPU,
 726 };
 727
 728 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 729         {
 730                 .pa_start       = 0x490f1000,
 731                 .pa_end         = 0x490f13ff,
 732                 .flags          = ADDR_TYPE_RT
 733         },
 734         { }
 735 };
 736
 737 /* l4_abe -> aess (dma) */
 738 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 739         .master         = &omap44xx_l4_abe_hwmod,
 740         .slave          = &omap44xx_aess_hwmod,
 741         .clk            = "ocp_abe_iclk",
 742         .addr           = omap44xx_aess_dma_addrs,
 743         .user           = OCP_USER_SDMA,
 744 };
 745
 746 /* aess slave ports */
 747 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 748         &omap44xx_l4_abe__aess,
 749         &omap44xx_l4_abe__aess_dma,
 750 };
 751
 752 static struct omap_hwmod omap44xx_aess_hwmod = {
 753         .name           = "aess",
 754         .class          = &omap44xx_aess_hwmod_class,
 755         .clkdm_name     = "abe_clkdm",
 756         .mpu_irqs       = omap44xx_aess_irqs,
 757         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 758         .main_clk       = "aess_fck",
 759         .prcm = {
 760                 .omap4 = {
 761                         .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 762                 },
 763         },
 764         .slaves         = omap44xx_aess_slaves,
 765         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 766         .masters        = omap44xx_aess_masters,
 767         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 768         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 769 };
 770
 771 /*
 772  * 'bandgap' class
 773  * bangap reference for ldo regulators
 774  */
 775
 776 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 777         .name   = "bandgap",
 778 };
 779
 780 /* bandgap */
 781 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 782         { .role = "fclk", .clk = "bandgap_fclk" },
 783 };
 784
 785 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 786         .name           = "bandgap",
 787         .class          = &omap44xx_bandgap_hwmod_class,
 788         .clkdm_name     = "l4_wkup_clkdm",
 789         .prcm = {
 790                 .omap4 = {
 791                         .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 792                 },
 793         },
 794         .opt_clks       = bandgap_opt_clks,
 795         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 796         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 797 };
 798
 799 /*
 800  * 'counter' class
 801  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 802  */
 803
 804 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 805         .rev_offs       = 0x0000,
 806         .sysc_offs      = 0x0004,
 807         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 808         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 809                            SIDLE_SMART_WKUP),
 810         .sysc_fields    = &omap_hwmod_sysc_type1,
 811 };
 812
 813 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 814         .name   = "counter",
 815         .sysc   = &omap44xx_counter_sysc,
 816 };
 817
 818 /* counter_32k */
 819 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 820 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 821         {
 822                 .pa_start       = 0x4a304000,
 823                 .pa_end         = 0x4a30401f,
 824                 .flags          = ADDR_TYPE_RT
 825         },
 826         { }
 827 };
 828
 829 /* l4_wkup -> counter_32k */
 830 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 831         .master         = &omap44xx_l4_wkup_hwmod,
 832         .slave          = &omap44xx_counter_32k_hwmod,
 833         .clk            = "l4_wkup_clk_mux_ck",
 834         .addr           = omap44xx_counter_32k_addrs,
 835         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 836 };
 837
 838 /* counter_32k slave ports */
 839 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 840         &omap44xx_l4_wkup__counter_32k,
 841 };
 842
 843 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 844         .name           = "counter_32k",
 845         .class          = &omap44xx_counter_hwmod_class,
 846         .clkdm_name     = "l4_wkup_clkdm",
 847         .flags          = HWMOD_SWSUP_SIDLE,
 848         .main_clk       = "sys_32k_ck",
 849         .prcm = {
 850                 .omap4 = {
 851                         .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
 852                 },
 853         },
 854         .slaves         = omap44xx_counter_32k_slaves,
 855         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 856         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 857 };
 858
 859 /*
 860  * 'dma' class
 861  * dma controller for data exchange between memory to memory (i.e. internal or
 862  * external memory) and gp peripherals to memory or memory to gp peripherals
 863  */
 864
 865 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 866         .rev_offs       = 0x0000,
 867         .sysc_offs      = 0x002c,
 868         .syss_offs      = 0x0028,
 869         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 870                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 871                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 872                            SYSS_HAS_RESET_STATUS),
 873         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 874                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 875         .sysc_fields    = &omap_hwmod_sysc_type1,
 876 };
 877
 878 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 879         .name   = "dma",
 880         .sysc   = &omap44xx_dma_sysc,
 881 };
 882
 883 /* dma dev_attr */
 884 static struct omap_dma_dev_attr dma_dev_attr = {
 885         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 886                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 887         .lch_count      = 32,
 888 };
 889
 890 /* dma_system */
 891 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 892         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 893         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 894         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 895         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 896         { .irq = -1 }
 897 };
 898
 899 /* dma_system master ports */
 900 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 901         &omap44xx_dma_system__l3_main_2,
 902 };
 903
 904 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 905         {
 906                 .pa_start       = 0x4a056000,
 907                 .pa_end         = 0x4a056fff,
 908                 .flags          = ADDR_TYPE_RT
 909         },
 910         { }
 911 };
 912
 913 /* l4_cfg -> dma_system */
 914 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 915         .master         = &omap44xx_l4_cfg_hwmod,
 916         .slave          = &omap44xx_dma_system_hwmod,
 917         .clk            = "l4_div_ck",
 918         .addr           = omap44xx_dma_system_addrs,
 919         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 920 };
 921
 922 /* dma_system slave ports */
 923 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 924         &omap44xx_l4_cfg__dma_system,
 925 };
 926
 927 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 928         .name           = "dma_system",
 929         .class          = &omap44xx_dma_hwmod_class,
 930         .clkdm_name     = "l3_dma_clkdm",
 931         .mpu_irqs       = omap44xx_dma_system_irqs,
 932         .main_clk       = "l3_div_ck",
 933         .prcm = {
 934                 .omap4 = {
 935                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 936                 },
 937         },
 938         .dev_attr       = &dma_dev_attr,
 939         .slaves         = omap44xx_dma_system_slaves,
 940         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 941         .masters        = omap44xx_dma_system_masters,
 942         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 943         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 944 };
 945
 946 /*
 947  * 'dmic' class
 948  * digital microphone controller
 949  */
 950
 951 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 952         .rev_offs       = 0x0000,
 953         .sysc_offs      = 0x0010,
 954         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 955                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 956         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 957                            SIDLE_SMART_WKUP),
 958         .sysc_fields    = &omap_hwmod_sysc_type2,
 959 };
 960
 961 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 962         .name   = "dmic",
 963         .sysc   = &omap44xx_dmic_sysc,
 964 };
 965
 966 /* dmic */
 967 static struct omap_hwmod omap44xx_dmic_hwmod;
 968 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 969         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 970         { .irq = -1 }
 971 };
 972
 973 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 974         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 975         { .dma_req = -1 }
 976 };
 977
 978 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 979         {
 980                 .pa_start       = 0x4012e000,
 981                 .pa_end         = 0x4012e07f,
 982                 .flags          = ADDR_TYPE_RT
 983         },
 984         { }
 985 };
 986
 987 /* l4_abe -> dmic */
 988 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 989         .master         = &omap44xx_l4_abe_hwmod,
 990         .slave          = &omap44xx_dmic_hwmod,
 991         .clk            = "ocp_abe_iclk",
 992         .addr           = omap44xx_dmic_addrs,
 993         .user           = OCP_USER_MPU,
 994 };
 995
 996 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 997         {
 998                 .pa_start       = 0x4902e000,
 999                 .pa_end         = 0x4902e07f,
1000                 .flags          = ADDR_TYPE_RT
1001         },
1002         { }
1003 };
1004
1005 /* l4_abe -> dmic (dma) */
1006 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1007         .master         = &omap44xx_l4_abe_hwmod,
1008         .slave          = &omap44xx_dmic_hwmod,
1009         .clk            = "ocp_abe_iclk",
1010         .addr           = omap44xx_dmic_dma_addrs,
1011         .user           = OCP_USER_SDMA,
1012 };
1013
1014 /* dmic slave ports */
1015 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1016         &omap44xx_l4_abe__dmic,
1017         &omap44xx_l4_abe__dmic_dma,
1018 };
1019
1020 static struct omap_hwmod omap44xx_dmic_hwmod = {
1021         .name           = "dmic",
1022         .class          = &omap44xx_dmic_hwmod_class,
1023         .clkdm_name     = "abe_clkdm",
1024         .mpu_irqs       = omap44xx_dmic_irqs,
1025         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1026         .main_clk       = "dmic_fck",
1027         .prcm = {
1028                 .omap4 = {
1029                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1030                 },
1031         },
1032         .slaves         = omap44xx_dmic_slaves,
1033         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1034         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1035 };
1036
1037 /*
1038  * 'dsp' class
1039  * dsp sub-system
1040  */
1041
1042 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1043         .name   = "dsp",
1044 };
1045
1046 /* dsp */
1047 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1048         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1049         { .irq = -1 }
1050 };
1051
1052 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1053         { .name = "mmu_cache", .rst_shift = 1 },
1054 };
1055
1056 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1057         { .name = "dsp", .rst_shift = 0 },
1058 };
1059
1060 /* dsp -> iva */
1061 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1062         .master         = &omap44xx_dsp_hwmod,
1063         .slave          = &omap44xx_iva_hwmod,
1064         .clk            = "dpll_iva_m5x2_ck",
1065 };
1066
1067 /* dsp master ports */
1068 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1069         &omap44xx_dsp__l3_main_1,
1070         &omap44xx_dsp__l4_abe,
1071         &omap44xx_dsp__iva,
1072 };
1073
1074 /* l4_cfg -> dsp */
1075 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1076         .master         = &omap44xx_l4_cfg_hwmod,
1077         .slave          = &omap44xx_dsp_hwmod,
1078         .clk            = "l4_div_ck",
1079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1080 };
1081
1082 /* dsp slave ports */
1083 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1084         &omap44xx_l4_cfg__dsp,
1085 };
1086
1087 /* Pseudo hwmod for reset control purpose only */
1088 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1089         .name           = "dsp_c0",
1090         .class          = &omap44xx_dsp_hwmod_class,
1091         .clkdm_name     = "tesla_clkdm",
1092         .flags          = HWMOD_INIT_NO_RESET,
1093         .rst_lines      = omap44xx_dsp_c0_resets,
1094         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1095         .prcm = {
1096                 .omap4 = {
1097                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1098                 },
1099         },
1100         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1101 };
1102
1103 static struct omap_hwmod omap44xx_dsp_hwmod = {
1104         .name           = "dsp",
1105         .class          = &omap44xx_dsp_hwmod_class,
1106         .clkdm_name     = "tesla_clkdm",
1107         .mpu_irqs       = omap44xx_dsp_irqs,
1108         .rst_lines      = omap44xx_dsp_resets,
1109         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1110         .main_clk       = "dsp_fck",
1111         .prcm = {
1112                 .omap4 = {
1113                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1114                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1115                 },
1116         },
1117         .slaves         = omap44xx_dsp_slaves,
1118         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1119         .masters        = omap44xx_dsp_masters,
1120         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1121         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1122 };
1123
1124 /*
1125  * 'dss' class
1126  * display sub-system
1127  */
1128
1129 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1130         .rev_offs       = 0x0000,
1131         .syss_offs      = 0x0014,
1132         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1133 };
1134
1135 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1136         .name   = "dss",
1137         .sysc   = &omap44xx_dss_sysc,
1138 };
1139
1140 /* dss */
1141 /* dss master ports */
1142 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1143         &omap44xx_dss__l3_main_1,
1144 };
1145
1146 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1147         {
1148                 .pa_start       = 0x58000000,
1149                 .pa_end         = 0x5800007f,
1150                 .flags          = ADDR_TYPE_RT
1151         },
1152         { }
1153 };
1154
1155 /* l3_main_2 -> dss */
1156 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1157         .master         = &omap44xx_l3_main_2_hwmod,
1158         .slave          = &omap44xx_dss_hwmod,
1159         .clk            = "dss_fck",
1160         .addr           = omap44xx_dss_dma_addrs,
1161         .user           = OCP_USER_SDMA,
1162 };
1163
1164 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1165         {
1166                 .pa_start       = 0x48040000,
1167                 .pa_end         = 0x4804007f,
1168                 .flags          = ADDR_TYPE_RT
1169         },
1170         { }
1171 };
1172
1173 /* l4_per -> dss */
1174 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1175         .master         = &omap44xx_l4_per_hwmod,
1176         .slave          = &omap44xx_dss_hwmod,
1177         .clk            = "l4_div_ck",
1178         .addr           = omap44xx_dss_addrs,
1179         .user           = OCP_USER_MPU,
1180 };
1181
1182 /* dss slave ports */
1183 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1184         &omap44xx_l3_main_2__dss,
1185         &omap44xx_l4_per__dss,
1186 };
1187
1188 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1189         { .role = "sys_clk", .clk = "dss_sys_clk" },
1190         { .role = "tv_clk", .clk = "dss_tv_clk" },
1191         { .role = "dss_clk", .clk = "dss_dss_clk" },
1192         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1193 };
1194
1195 static struct omap_hwmod omap44xx_dss_hwmod = {
1196         .name           = "dss_core",
1197         .class          = &omap44xx_dss_hwmod_class,
1198         .clkdm_name     = "l3_dss_clkdm",
1199         .main_clk       = "dss_dss_clk",
1200         .prcm = {
1201                 .omap4 = {
1202                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1203                 },
1204         },
1205         .opt_clks       = dss_opt_clks,
1206         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1207         .slaves         = omap44xx_dss_slaves,
1208         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1209         .masters        = omap44xx_dss_masters,
1210         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1211         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1212 };
1213
1214 /*
1215  * 'dispc' class
1216  * display controller
1217  */
1218
1219 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1220         .rev_offs       = 0x0000,
1221         .sysc_offs      = 0x0010,
1222         .syss_offs      = 0x0014,
1223         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1224                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1225                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1226                            SYSS_HAS_RESET_STATUS),
1227         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1228                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1229         .sysc_fields    = &omap_hwmod_sysc_type1,
1230 };
1231
1232 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1233         .name   = "dispc",
1234         .sysc   = &omap44xx_dispc_sysc,
1235 };
1236
1237 /* dss_dispc */
1238 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1239 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1240         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1241         { .irq = -1 }
1242 };
1243
1244 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1245         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1246         { .dma_req = -1 }
1247 };
1248
1249 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1250         {
1251                 .pa_start       = 0x58001000,
1252                 .pa_end         = 0x58001fff,
1253                 .flags          = ADDR_TYPE_RT
1254         },
1255         { }
1256 };
1257
1258 /* l3_main_2 -> dss_dispc */
1259 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1260         .master         = &omap44xx_l3_main_2_hwmod,
1261         .slave          = &omap44xx_dss_dispc_hwmod,
1262         .clk            = "dss_fck",
1263         .addr           = omap44xx_dss_dispc_dma_addrs,
1264         .user           = OCP_USER_SDMA,
1265 };
1266
1267 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1268         {
1269                 .pa_start       = 0x48041000,
1270                 .pa_end         = 0x48041fff,
1271                 .flags          = ADDR_TYPE_RT
1272         },
1273         { }
1274 };
1275
1276 /* l4_per -> dss_dispc */
1277 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1278         .master         = &omap44xx_l4_per_hwmod,
1279         .slave          = &omap44xx_dss_dispc_hwmod,
1280         .clk            = "l4_div_ck",
1281         .addr           = omap44xx_dss_dispc_addrs,
1282         .user           = OCP_USER_MPU,
1283 };
1284
1285 /* dss_dispc slave ports */
1286 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1287         &omap44xx_l3_main_2__dss_dispc,
1288         &omap44xx_l4_per__dss_dispc,
1289 };
1290
1291 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1292         { .role = "sys_clk", .clk = "dss_sys_clk" },
1293         { .role = "tv_clk", .clk = "dss_tv_clk" },
1294         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1295 };
1296
1297 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1298         .name           = "dss_dispc",
1299         .class          = &omap44xx_dispc_hwmod_class,
1300         .clkdm_name     = "l3_dss_clkdm",
1301         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1302         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1303         .main_clk       = "dss_dss_clk",
1304         .prcm = {
1305                 .omap4 = {
1306                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1307                 },
1308         },
1309         .opt_clks       = dss_dispc_opt_clks,
1310         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
1311         .slaves         = omap44xx_dss_dispc_slaves,
1312         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1313         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1314 };
1315
1316 /*
1317  * 'dsi' class
1318  * display serial interface controller
1319  */
1320
1321 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1322         .rev_offs       = 0x0000,
1323         .sysc_offs      = 0x0010,
1324         .syss_offs      = 0x0014,
1325         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1326                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1327                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1328         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1329         .sysc_fields    = &omap_hwmod_sysc_type1,
1330 };
1331
1332 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1333         .name   = "dsi",
1334         .sysc   = &omap44xx_dsi_sysc,
1335 };
1336
1337 /* dss_dsi1 */
1338 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1339 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1340         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1341         { .irq = -1 }
1342 };
1343
1344 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1345         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1346         { .dma_req = -1 }
1347 };
1348
1349 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1350         {
1351                 .pa_start       = 0x58004000,
1352                 .pa_end         = 0x580041ff,
1353                 .flags          = ADDR_TYPE_RT
1354         },
1355         { }
1356 };
1357
1358 /* l3_main_2 -> dss_dsi1 */
1359 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1360         .master         = &omap44xx_l3_main_2_hwmod,
1361         .slave          = &omap44xx_dss_dsi1_hwmod,
1362         .clk            = "dss_fck",
1363         .addr           = omap44xx_dss_dsi1_dma_addrs,
1364         .user           = OCP_USER_SDMA,
1365 };
1366
1367 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1368         {
1369                 .pa_start       = 0x48044000,
1370                 .pa_end         = 0x480441ff,
1371                 .flags          = ADDR_TYPE_RT
1372         },
1373         { }
1374 };
1375
1376 /* l4_per -> dss_dsi1 */
1377 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1378         .master         = &omap44xx_l4_per_hwmod,
1379         .slave          = &omap44xx_dss_dsi1_hwmod,
1380         .clk            = "l4_div_ck",
1381         .addr           = omap44xx_dss_dsi1_addrs,
1382         .user           = OCP_USER_MPU,
1383 };
1384
1385 /* dss_dsi1 slave ports */
1386 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1387         &omap44xx_l3_main_2__dss_dsi1,
1388         &omap44xx_l4_per__dss_dsi1,
1389 };
1390
1391 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1392         { .role = "sys_clk", .clk = "dss_sys_clk" },
1393 };
1394
1395 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1396         .name           = "dss_dsi1",
1397         .class          = &omap44xx_dsi_hwmod_class,
1398         .clkdm_name     = "l3_dss_clkdm",
1399         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1400         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1401         .main_clk       = "dss_dss_clk",
1402         .prcm = {
1403                 .omap4 = {
1404                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1405                 },
1406         },
1407         .opt_clks       = dss_dsi1_opt_clks,
1408         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1409         .slaves         = omap44xx_dss_dsi1_slaves,
1410         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1411         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1412 };
1413
1414 /* dss_dsi2 */
1415 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1416 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1417         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1418         { .irq = -1 }
1419 };
1420
1421 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1422         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1423         { .dma_req = -1 }
1424 };
1425
1426 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1427         {
1428                 .pa_start       = 0x58005000,
1429                 .pa_end         = 0x580051ff,
1430                 .flags          = ADDR_TYPE_RT
1431         },
1432         { }
1433 };
1434
1435 /* l3_main_2 -> dss_dsi2 */
1436 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1437         .master         = &omap44xx_l3_main_2_hwmod,
1438         .slave          = &omap44xx_dss_dsi2_hwmod,
1439         .clk            = "dss_fck",
1440         .addr           = omap44xx_dss_dsi2_dma_addrs,
1441         .user           = OCP_USER_SDMA,
1442 };
1443
1444 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1445         {
1446                 .pa_start       = 0x48045000,
1447                 .pa_end         = 0x480451ff,
1448                 .flags          = ADDR_TYPE_RT
1449         },
1450         { }
1451 };
1452
1453 /* l4_per -> dss_dsi2 */
1454 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1455         .master         = &omap44xx_l4_per_hwmod,
1456         .slave          = &omap44xx_dss_dsi2_hwmod,
1457         .clk            = "l4_div_ck",
1458         .addr           = omap44xx_dss_dsi2_addrs,
1459         .user           = OCP_USER_MPU,
1460 };
1461
1462 /* dss_dsi2 slave ports */
1463 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1464         &omap44xx_l3_main_2__dss_dsi2,
1465         &omap44xx_l4_per__dss_dsi2,
1466 };
1467
1468 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1469         { .role = "sys_clk", .clk = "dss_sys_clk" },
1470 };
1471
1472 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1473         .name           = "dss_dsi2",
1474         .class          = &omap44xx_dsi_hwmod_class,
1475         .clkdm_name     = "l3_dss_clkdm",
1476         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1477         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1478         .main_clk       = "dss_dss_clk",
1479         .prcm = {
1480                 .omap4 = {
1481                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1482                 },
1483         },
1484         .opt_clks       = dss_dsi2_opt_clks,
1485         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1486         .slaves         = omap44xx_dss_dsi2_slaves,
1487         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1488         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1489 };
1490
1491 /*
1492  * 'hdmi' class
1493  * hdmi controller
1494  */
1495
1496 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1497         .rev_offs       = 0x0000,
1498         .sysc_offs      = 0x0010,
1499         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1500                            SYSC_HAS_SOFTRESET),
1501         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1502                            SIDLE_SMART_WKUP),
1503         .sysc_fields    = &omap_hwmod_sysc_type2,
1504 };
1505
1506 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1507         .name   = "hdmi",
1508         .sysc   = &omap44xx_hdmi_sysc,
1509 };
1510
1511 /* dss_hdmi */
1512 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1513 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1514         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1515         { .irq = -1 }
1516 };
1517
1518 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1519         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1520         { .dma_req = -1 }
1521 };
1522
1523 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1524         {
1525                 .pa_start       = 0x58006000,
1526                 .pa_end         = 0x58006fff,
1527                 .flags          = ADDR_TYPE_RT
1528         },
1529         { }
1530 };
1531
1532 /* l3_main_2 -> dss_hdmi */
1533 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1534         .master         = &omap44xx_l3_main_2_hwmod,
1535         .slave          = &omap44xx_dss_hdmi_hwmod,
1536         .clk            = "dss_fck",
1537         .addr           = omap44xx_dss_hdmi_dma_addrs,
1538         .user           = OCP_USER_SDMA,
1539 };
1540
1541 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1542         {
1543                 .pa_start       = 0x48046000,
1544                 .pa_end         = 0x48046fff,
1545                 .flags          = ADDR_TYPE_RT
1546         },
1547         { }
1548 };
1549
1550 /* l4_per -> dss_hdmi */
1551 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1552         .master         = &omap44xx_l4_per_hwmod,
1553         .slave          = &omap44xx_dss_hdmi_hwmod,
1554         .clk            = "l4_div_ck",
1555         .addr           = omap44xx_dss_hdmi_addrs,
1556         .user           = OCP_USER_MPU,
1557 };
1558
1559 /* dss_hdmi slave ports */
1560 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1561         &omap44xx_l3_main_2__dss_hdmi,
1562         &omap44xx_l4_per__dss_hdmi,
1563 };
1564
1565 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1566         { .role = "sys_clk", .clk = "dss_sys_clk" },
1567 };
1568
1569 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1570         .name           = "dss_hdmi",
1571         .class          = &omap44xx_hdmi_hwmod_class,
1572         .clkdm_name     = "l3_dss_clkdm",
1573         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1574         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1575         .main_clk       = "dss_dss_clk",
1576         .prcm = {
1577                 .omap4 = {
1578                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1579                 },
1580         },
1581         .opt_clks       = dss_hdmi_opt_clks,
1582         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1583         .slaves         = omap44xx_dss_hdmi_slaves,
1584         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1585         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1586 };
1587
1588 /*
1589  * 'rfbi' class
1590  * remote frame buffer interface
1591  */
1592
1593 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1594         .rev_offs       = 0x0000,
1595         .sysc_offs      = 0x0010,
1596         .syss_offs      = 0x0014,
1597         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1598                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1599         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1600         .sysc_fields    = &omap_hwmod_sysc_type1,
1601 };
1602
1603 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1604         .name   = "rfbi",
1605         .sysc   = &omap44xx_rfbi_sysc,
1606 };
1607
1608 /* dss_rfbi */
1609 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1610 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1611         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1612         { .dma_req = -1 }
1613 };
1614
1615 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1616         {
1617                 .pa_start       = 0x58002000,
1618                 .pa_end         = 0x580020ff,
1619                 .flags          = ADDR_TYPE_RT
1620         },
1621         { }
1622 };
1623
1624 /* l3_main_2 -> dss_rfbi */
1625 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1626         .master         = &omap44xx_l3_main_2_hwmod,
1627         .slave          = &omap44xx_dss_rfbi_hwmod,
1628         .clk            = "dss_fck",
1629         .addr           = omap44xx_dss_rfbi_dma_addrs,
1630         .user           = OCP_USER_SDMA,
1631 };
1632
1633 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1634         {
1635                 .pa_start       = 0x48042000,
1636                 .pa_end         = 0x480420ff,
1637                 .flags          = ADDR_TYPE_RT
1638         },
1639         { }
1640 };
1641
1642 /* l4_per -> dss_rfbi */
1643 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1644         .master         = &omap44xx_l4_per_hwmod,
1645         .slave          = &omap44xx_dss_rfbi_hwmod,
1646         .clk            = "l4_div_ck",
1647         .addr           = omap44xx_dss_rfbi_addrs,
1648         .user           = OCP_USER_MPU,
1649 };
1650
1651 /* dss_rfbi slave ports */
1652 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1653         &omap44xx_l3_main_2__dss_rfbi,
1654         &omap44xx_l4_per__dss_rfbi,
1655 };
1656
1657 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1658         { .role = "ick", .clk = "dss_fck" },
1659 };
1660
1661 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1662         .name           = "dss_rfbi",
1663         .class          = &omap44xx_rfbi_hwmod_class,
1664         .clkdm_name     = "l3_dss_clkdm",
1665         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1666         .main_clk       = "dss_dss_clk",
1667         .prcm = {
1668                 .omap4 = {
1669                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1670                 },
1671         },
1672         .opt_clks       = dss_rfbi_opt_clks,
1673         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1674         .slaves         = omap44xx_dss_rfbi_slaves,
1675         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1676         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1677 };
1678
1679 /*
1680  * 'venc' class
1681  * video encoder
1682  */
1683
1684 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1685         .name   = "venc",
1686 };
1687
1688 /* dss_venc */
1689 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1690 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1691         {
1692                 .pa_start       = 0x58003000,
1693                 .pa_end         = 0x580030ff,
1694                 .flags          = ADDR_TYPE_RT
1695         },
1696         { }
1697 };
1698
1699 /* l3_main_2 -> dss_venc */
1700 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1701         .master         = &omap44xx_l3_main_2_hwmod,
1702         .slave          = &omap44xx_dss_venc_hwmod,
1703         .clk            = "dss_fck",
1704         .addr           = omap44xx_dss_venc_dma_addrs,
1705         .user           = OCP_USER_SDMA,
1706 };
1707
1708 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1709         {
1710                 .pa_start       = 0x48043000,
1711                 .pa_end         = 0x480430ff,
1712                 .flags          = ADDR_TYPE_RT
1713         },
1714         { }
1715 };
1716
1717 /* l4_per -> dss_venc */
1718 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1719         .master         = &omap44xx_l4_per_hwmod,
1720         .slave          = &omap44xx_dss_venc_hwmod,
1721         .clk            = "l4_div_ck",
1722         .addr           = omap44xx_dss_venc_addrs,
1723         .user           = OCP_USER_MPU,
1724 };
1725
1726 /* dss_venc slave ports */
1727 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1728         &omap44xx_l3_main_2__dss_venc,
1729         &omap44xx_l4_per__dss_venc,
1730 };
1731
1732 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1733         .name           = "dss_venc",
1734         .class          = &omap44xx_venc_hwmod_class,
1735         .clkdm_name     = "l3_dss_clkdm",
1736         .main_clk       = "dss_dss_clk",
1737         .prcm = {
1738                 .omap4 = {
1739                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1740                 },
1741         },
1742         .slaves         = omap44xx_dss_venc_slaves,
1743         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1744         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1745 };
1746
1747 /*
1748  * 'gpio' class
1749  * general purpose io module
1750  */
1751
1752 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1753         .rev_offs       = 0x0000,
1754         .sysc_offs      = 0x0010,
1755         .syss_offs      = 0x0114,
1756         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1757                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1758                            SYSS_HAS_RESET_STATUS),
1759         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1760                            SIDLE_SMART_WKUP),
1761         .sysc_fields    = &omap_hwmod_sysc_type1,
1762 };
1763
1764 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1765         .name   = "gpio",
1766         .sysc   = &omap44xx_gpio_sysc,
1767         .rev    = 2,
1768 };
1769
1770 /* gpio dev_attr */
1771 static struct omap_gpio_dev_attr gpio_dev_attr = {
1772         .bank_width     = 32,
1773         .dbck_flag      = true,
1774 };
1775
1776 /* gpio1 */
1777 static struct omap_hwmod omap44xx_gpio1_hwmod;
1778 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1779         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1780         { .irq = -1 }
1781 };
1782
1783 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1784         {
1785                 .pa_start       = 0x4a310000,
1786                 .pa_end         = 0x4a3101ff,
1787                 .flags          = ADDR_TYPE_RT
1788         },
1789         { }
1790 };
1791
1792 /* l4_wkup -> gpio1 */
1793 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1794         .master         = &omap44xx_l4_wkup_hwmod,
1795         .slave          = &omap44xx_gpio1_hwmod,
1796         .clk            = "l4_wkup_clk_mux_ck",
1797         .addr           = omap44xx_gpio1_addrs,
1798         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1799 };
1800
1801 /* gpio1 slave ports */
1802 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1803         &omap44xx_l4_wkup__gpio1,
1804 };
1805
1806 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1807         { .role = "dbclk", .clk = "gpio1_dbclk" },
1808 };
1809
1810 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1811         .name           = "gpio1",
1812         .class          = &omap44xx_gpio_hwmod_class,
1813         .clkdm_name     = "l4_wkup_clkdm",
1814         .mpu_irqs       = omap44xx_gpio1_irqs,
1815         .main_clk       = "gpio1_ick",
1816         .prcm = {
1817                 .omap4 = {
1818                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1819                 },
1820         },
1821         .opt_clks       = gpio1_opt_clks,
1822         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1823         .dev_attr       = &gpio_dev_attr,
1824         .slaves         = omap44xx_gpio1_slaves,
1825         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1826         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1827 };
1828
1829 /* gpio2 */
1830 static struct omap_hwmod omap44xx_gpio2_hwmod;
1831 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1832         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1833         { .irq = -1 }
1834 };
1835
1836 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1837         {
1838                 .pa_start       = 0x48055000,
1839                 .pa_end         = 0x480551ff,
1840                 .flags          = ADDR_TYPE_RT
1841         },
1842         { }
1843 };
1844
1845 /* l4_per -> gpio2 */
1846 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1847         .master         = &omap44xx_l4_per_hwmod,
1848         .slave          = &omap44xx_gpio2_hwmod,
1849         .clk            = "l4_div_ck",
1850         .addr           = omap44xx_gpio2_addrs,
1851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1852 };
1853
1854 /* gpio2 slave ports */
1855 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1856         &omap44xx_l4_per__gpio2,
1857 };
1858
1859 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1860         { .role = "dbclk", .clk = "gpio2_dbclk" },
1861 };
1862
1863 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1864         .name           = "gpio2",
1865         .class          = &omap44xx_gpio_hwmod_class,
1866         .clkdm_name     = "l4_per_clkdm",
1867         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1868         .mpu_irqs       = omap44xx_gpio2_irqs,
1869         .main_clk       = "gpio2_ick",
1870         .prcm = {
1871                 .omap4 = {
1872                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1873                 },
1874         },
1875         .opt_clks       = gpio2_opt_clks,
1876         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1877         .dev_attr       = &gpio_dev_attr,
1878         .slaves         = omap44xx_gpio2_slaves,
1879         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1880         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1881 };
1882
1883 /* gpio3 */
1884 static struct omap_hwmod omap44xx_gpio3_hwmod;
1885 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1886         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1887         { .irq = -1 }
1888 };
1889
1890 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1891         {
1892                 .pa_start       = 0x48057000,
1893                 .pa_end         = 0x480571ff,
1894                 .flags          = ADDR_TYPE_RT
1895         },
1896         { }
1897 };
1898
1899 /* l4_per -> gpio3 */
1900 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1901         .master         = &omap44xx_l4_per_hwmod,
1902         .slave          = &omap44xx_gpio3_hwmod,
1903         .clk            = "l4_div_ck",
1904         .addr           = omap44xx_gpio3_addrs,
1905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1906 };
1907
1908 /* gpio3 slave ports */
1909 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1910         &omap44xx_l4_per__gpio3,
1911 };
1912
1913 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1914         { .role = "dbclk", .clk = "gpio3_dbclk" },
1915 };
1916
1917 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1918         .name           = "gpio3",
1919         .class          = &omap44xx_gpio_hwmod_class,
1920         .clkdm_name     = "l4_per_clkdm",
1921         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1922         .mpu_irqs       = omap44xx_gpio3_irqs,
1923         .main_clk       = "gpio3_ick",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1927                 },
1928         },
1929         .opt_clks       = gpio3_opt_clks,
1930         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1931         .dev_attr       = &gpio_dev_attr,
1932         .slaves         = omap44xx_gpio3_slaves,
1933         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1934         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1935 };
1936
1937 /* gpio4 */
1938 static struct omap_hwmod omap44xx_gpio4_hwmod;
1939 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1940         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1941         { .irq = -1 }
1942 };
1943
1944 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1945         {
1946                 .pa_start       = 0x48059000,
1947                 .pa_end         = 0x480591ff,
1948                 .flags          = ADDR_TYPE_RT
1949         },
1950         { }
1951 };
1952
1953 /* l4_per -> gpio4 */
1954 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1955         .master         = &omap44xx_l4_per_hwmod,
1956         .slave          = &omap44xx_gpio4_hwmod,
1957         .clk            = "l4_div_ck",
1958         .addr           = omap44xx_gpio4_addrs,
1959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1960 };
1961
1962 /* gpio4 slave ports */
1963 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1964         &omap44xx_l4_per__gpio4,
1965 };
1966
1967 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1968         { .role = "dbclk", .clk = "gpio4_dbclk" },
1969 };
1970
1971 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1972         .name           = "gpio4",
1973         .class          = &omap44xx_gpio_hwmod_class,
1974         .clkdm_name     = "l4_per_clkdm",
1975         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1976         .mpu_irqs       = omap44xx_gpio4_irqs,
1977         .main_clk       = "gpio4_ick",
1978         .prcm = {
1979                 .omap4 = {
1980                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1981                 },
1982         },
1983         .opt_clks       = gpio4_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1985         .dev_attr       = &gpio_dev_attr,
1986         .slaves         = omap44xx_gpio4_slaves,
1987         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1988         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1989 };
1990
1991 /* gpio5 */
1992 static struct omap_hwmod omap44xx_gpio5_hwmod;
1993 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1994         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1995         { .irq = -1 }
1996 };
1997
1998 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1999         {
2000                 .pa_start       = 0x4805b000,
2001                 .pa_end         = 0x4805b1ff,
2002                 .flags          = ADDR_TYPE_RT
2003         },
2004         { }
2005 };
2006
2007 /* l4_per -> gpio5 */
2008 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2009         .master         = &omap44xx_l4_per_hwmod,
2010         .slave          = &omap44xx_gpio5_hwmod,
2011         .clk            = "l4_div_ck",
2012         .addr           = omap44xx_gpio5_addrs,
2013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2014 };
2015
2016 /* gpio5 slave ports */
2017 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2018         &omap44xx_l4_per__gpio5,
2019 };
2020
2021 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2022         { .role = "dbclk", .clk = "gpio5_dbclk" },
2023 };
2024
2025 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2026         .name           = "gpio5",
2027         .class          = &omap44xx_gpio_hwmod_class,
2028         .clkdm_name     = "l4_per_clkdm",
2029         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2030         .mpu_irqs       = omap44xx_gpio5_irqs,
2031         .main_clk       = "gpio5_ick",
2032         .prcm = {
2033                 .omap4 = {
2034                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
2035                 },
2036         },
2037         .opt_clks       = gpio5_opt_clks,
2038         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2039         .dev_attr       = &gpio_dev_attr,
2040         .slaves         = omap44xx_gpio5_slaves,
2041         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2042         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2043 };
2044
2045 /* gpio6 */
2046 static struct omap_hwmod omap44xx_gpio6_hwmod;
2047 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2048         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2049         { .irq = -1 }
2050 };
2051
2052 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2053         {
2054                 .pa_start       = 0x4805d000,
2055                 .pa_end         = 0x4805d1ff,
2056                 .flags          = ADDR_TYPE_RT
2057         },
2058         { }
2059 };
2060
2061 /* l4_per -> gpio6 */
2062 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2063         .master         = &omap44xx_l4_per_hwmod,
2064         .slave          = &omap44xx_gpio6_hwmod,
2065         .clk            = "l4_div_ck",
2066         .addr           = omap44xx_gpio6_addrs,
2067         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2068 };
2069
2070 /* gpio6 slave ports */
2071 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2072         &omap44xx_l4_per__gpio6,
2073 };
2074
2075 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2076         { .role = "dbclk", .clk = "gpio6_dbclk" },
2077 };
2078
2079 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2080         .name           = "gpio6",
2081         .class          = &omap44xx_gpio_hwmod_class,
2082         .clkdm_name     = "l4_per_clkdm",
2083         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2084         .mpu_irqs       = omap44xx_gpio6_irqs,
2085         .main_clk       = "gpio6_ick",
2086         .prcm = {
2087                 .omap4 = {
2088                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2089                 },
2090         },
2091         .opt_clks       = gpio6_opt_clks,
2092         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2093         .dev_attr       = &gpio_dev_attr,
2094         .slaves         = omap44xx_gpio6_slaves,
2095         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2096         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2097 };
2098
2099 /*
2100  * 'hsi' class
2101  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2102  * serial if)
2103  */
2104
2105 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2106         .rev_offs       = 0x0000,
2107         .sysc_offs      = 0x0010,
2108         .syss_offs      = 0x0014,
2109         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2110                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2111                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2112         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2113                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2114                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2115         .sysc_fields    = &omap_hwmod_sysc_type1,
2116 };
2117
2118 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2119         .name   = "hsi",
2120         .sysc   = &omap44xx_hsi_sysc,
2121 };
2122
2123 /* hsi */
2124 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2125         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2126         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2127         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2128         { .irq = -1 }
2129 };
2130
2131 /* hsi master ports */
2132 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2133         &omap44xx_hsi__l3_main_2,
2134 };
2135
2136 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2137         {
2138                 .pa_start       = 0x4a058000,
2139                 .pa_end         = 0x4a05bfff,
2140                 .flags          = ADDR_TYPE_RT
2141         },
2142         { }
2143 };
2144
2145 /* l4_cfg -> hsi */
2146 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2147         .master         = &omap44xx_l4_cfg_hwmod,
2148         .slave          = &omap44xx_hsi_hwmod,
2149         .clk            = "l4_div_ck",
2150         .addr           = omap44xx_hsi_addrs,
2151         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2152 };
2153
2154 /* hsi slave ports */
2155 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2156         &omap44xx_l4_cfg__hsi,
2157 };
2158
2159 static struct omap_hwmod omap44xx_hsi_hwmod = {
2160         .name           = "hsi",
2161         .class          = &omap44xx_hsi_hwmod_class,
2162         .clkdm_name     = "l3_init_clkdm",
2163         .mpu_irqs       = omap44xx_hsi_irqs,
2164         .main_clk       = "hsi_fck",
2165         .prcm = {
2166                 .omap4 = {
2167                         .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2168                 },
2169         },
2170         .slaves         = omap44xx_hsi_slaves,
2171         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2172         .masters        = omap44xx_hsi_masters,
2173         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2174         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2175 };
2176
2177 /*
2178  * 'i2c' class
2179  * multimaster high-speed i2c controller
2180  */
2181
2182 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2183         .sysc_offs      = 0x0010,
2184         .syss_offs      = 0x0090,
2185         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2186                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2187                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2188         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2189                            SIDLE_SMART_WKUP),
2190         .sysc_fields    = &omap_hwmod_sysc_type1,
2191 };
2192
2193 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2194         .name   = "i2c",
2195         .sysc   = &omap44xx_i2c_sysc,
2196         .rev    = OMAP_I2C_IP_VERSION_2,
2197         .reset  = &omap_i2c_reset,
2198 };
2199
2200 static struct omap_i2c_dev_attr i2c_dev_attr = {
2201         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2202 };
2203
2204 /* i2c1 */
2205 static struct omap_hwmod omap44xx_i2c1_hwmod;
2206 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2207         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2208         { .irq = -1 }
2209 };
2210
2211 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2212         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2213         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2214         { .dma_req = -1 }
2215 };
2216
2217 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2218         {
2219                 .pa_start       = 0x48070000,
2220                 .pa_end         = 0x480700ff,
2221                 .flags          = ADDR_TYPE_RT
2222         },
2223         { }
2224 };
2225
2226 /* l4_per -> i2c1 */
2227 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2228         .master         = &omap44xx_l4_per_hwmod,
2229         .slave          = &omap44xx_i2c1_hwmod,
2230         .clk            = "l4_div_ck",
2231         .addr           = omap44xx_i2c1_addrs,
2232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2233 };
2234
2235 /* i2c1 slave ports */
2236 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2237         &omap44xx_l4_per__i2c1,
2238 };
2239
2240 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2241         .name           = "i2c1",
2242         .class          = &omap44xx_i2c_hwmod_class,
2243         .clkdm_name     = "l4_per_clkdm",
2244         .flags          = HWMOD_16BIT_REG,
2245         .mpu_irqs       = omap44xx_i2c1_irqs,
2246         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2247         .main_clk       = "i2c1_fck",
2248         .prcm = {
2249                 .omap4 = {
2250                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2251                 },
2252         },
2253         .slaves         = omap44xx_i2c1_slaves,
2254         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2255         .dev_attr       = &i2c_dev_attr,
2256         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2257 };
2258
2259 /* i2c2 */
2260 static struct omap_hwmod omap44xx_i2c2_hwmod;
2261 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2262         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2263         { .irq = -1 }
2264 };
2265
2266 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2267         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2268         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2269         { .dma_req = -1 }
2270 };
2271
2272 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2273         {
2274                 .pa_start       = 0x48072000,
2275                 .pa_end         = 0x480720ff,
2276                 .flags          = ADDR_TYPE_RT
2277         },
2278         { }
2279 };
2280
2281 /* l4_per -> i2c2 */
2282 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2283         .master         = &omap44xx_l4_per_hwmod,
2284         .slave          = &omap44xx_i2c2_hwmod,
2285         .clk            = "l4_div_ck",
2286         .addr           = omap44xx_i2c2_addrs,
2287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2288 };
2289
2290 /* i2c2 slave ports */
2291 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2292         &omap44xx_l4_per__i2c2,
2293 };
2294
2295 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2296         .name           = "i2c2",
2297         .class          = &omap44xx_i2c_hwmod_class,
2298         .clkdm_name     = "l4_per_clkdm",
2299         .flags          = HWMOD_16BIT_REG,
2300         .mpu_irqs       = omap44xx_i2c2_irqs,
2301         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2302         .main_clk       = "i2c2_fck",
2303         .prcm = {
2304                 .omap4 = {
2305                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2306                 },
2307         },
2308         .slaves         = omap44xx_i2c2_slaves,
2309         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2310         .dev_attr       = &i2c_dev_attr,
2311         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2312 };
2313
2314 /* i2c3 */
2315 static struct omap_hwmod omap44xx_i2c3_hwmod;
2316 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2317         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2318         { .irq = -1 }
2319 };
2320
2321 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2322         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2323         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2324         { .dma_req = -1 }
2325 };
2326
2327 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2328         {
2329                 .pa_start       = 0x48060000,
2330                 .pa_end         = 0x480600ff,
2331                 .flags          = ADDR_TYPE_RT
2332         },
2333         { }
2334 };
2335
2336 /* l4_per -> i2c3 */
2337 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2338         .master         = &omap44xx_l4_per_hwmod,
2339         .slave          = &omap44xx_i2c3_hwmod,
2340         .clk            = "l4_div_ck",
2341         .addr           = omap44xx_i2c3_addrs,
2342         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2343 };
2344
2345 /* i2c3 slave ports */
2346 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2347         &omap44xx_l4_per__i2c3,
2348 };
2349
2350 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2351         .name           = "i2c3",
2352         .class          = &omap44xx_i2c_hwmod_class,
2353         .clkdm_name     = "l4_per_clkdm",
2354         .flags          = HWMOD_16BIT_REG,
2355         .mpu_irqs       = omap44xx_i2c3_irqs,
2356         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2357         .main_clk       = "i2c3_fck",
2358         .prcm = {
2359                 .omap4 = {
2360                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2361                 },
2362         },
2363         .slaves         = omap44xx_i2c3_slaves,
2364         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2365         .dev_attr       = &i2c_dev_attr,
2366         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2367 };
2368
2369 /* i2c4 */
2370 static struct omap_hwmod omap44xx_i2c4_hwmod;
2371 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2372         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2373         { .irq = -1 }
2374 };
2375
2376 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2377         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2378         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2379         { .dma_req = -1 }
2380 };
2381
2382 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2383         {
2384                 .pa_start       = 0x48350000,
2385                 .pa_end         = 0x483500ff,
2386                 .flags          = ADDR_TYPE_RT
2387         },
2388         { }
2389 };
2390
2391 /* l4_per -> i2c4 */
2392 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2393         .master         = &omap44xx_l4_per_hwmod,
2394         .slave          = &omap44xx_i2c4_hwmod,
2395         .clk            = "l4_div_ck",
2396         .addr           = omap44xx_i2c4_addrs,
2397         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2398 };
2399
2400 /* i2c4 slave ports */
2401 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2402         &omap44xx_l4_per__i2c4,
2403 };
2404
2405 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2406         .name           = "i2c4",
2407         .class          = &omap44xx_i2c_hwmod_class,
2408         .clkdm_name     = "l4_per_clkdm",
2409         .flags          = HWMOD_16BIT_REG,
2410         .mpu_irqs       = omap44xx_i2c4_irqs,
2411         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2412         .main_clk       = "i2c4_fck",
2413         .prcm = {
2414                 .omap4 = {
2415                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2416                 },
2417         },
2418         .slaves         = omap44xx_i2c4_slaves,
2419         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2420         .dev_attr       = &i2c_dev_attr,
2421         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2422 };
2423
2424 /*
2425  * 'ipu' class
2426  * imaging processor unit
2427  */
2428
2429 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2430         .name   = "ipu",
2431 };
2432
2433 /* ipu */
2434 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2435         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2436         { .irq = -1 }
2437 };
2438
2439 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2440         { .name = "cpu0", .rst_shift = 0 },
2441 };
2442
2443 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2444         { .name = "cpu1", .rst_shift = 1 },
2445 };
2446
2447 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2448         { .name = "mmu_cache", .rst_shift = 2 },
2449 };
2450
2451 /* ipu master ports */
2452 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2453         &omap44xx_ipu__l3_main_2,
2454 };
2455
2456 /* l3_main_2 -> ipu */
2457 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2458         .master         = &omap44xx_l3_main_2_hwmod,
2459         .slave          = &omap44xx_ipu_hwmod,
2460         .clk            = "l3_div_ck",
2461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2462 };
2463
2464 /* ipu slave ports */
2465 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2466         &omap44xx_l3_main_2__ipu,
2467 };
2468
2469 /* Pseudo hwmod for reset control purpose only */
2470 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2471         .name           = "ipu_c0",
2472         .class          = &omap44xx_ipu_hwmod_class,
2473         .clkdm_name     = "ducati_clkdm",
2474         .flags          = HWMOD_INIT_NO_RESET,
2475         .rst_lines      = omap44xx_ipu_c0_resets,
2476         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2477         .prcm = {
2478                 .omap4 = {
2479                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2480                 },
2481         },
2482         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2483 };
2484
2485 /* Pseudo hwmod for reset control purpose only */
2486 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2487         .name           = "ipu_c1",
2488         .class          = &omap44xx_ipu_hwmod_class,
2489         .clkdm_name     = "ducati_clkdm",
2490         .flags          = HWMOD_INIT_NO_RESET,
2491         .rst_lines      = omap44xx_ipu_c1_resets,
2492         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2493         .prcm = {
2494                 .omap4 = {
2495                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2496                 },
2497         },
2498         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2499 };
2500
2501 static struct omap_hwmod omap44xx_ipu_hwmod = {
2502         .name           = "ipu",
2503         .class          = &omap44xx_ipu_hwmod_class,
2504         .clkdm_name     = "ducati_clkdm",
2505         .mpu_irqs       = omap44xx_ipu_irqs,
2506         .rst_lines      = omap44xx_ipu_resets,
2507         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2508         .main_clk       = "ipu_fck",
2509         .prcm = {
2510                 .omap4 = {
2511                         .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2512                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2513                 },
2514         },
2515         .slaves         = omap44xx_ipu_slaves,
2516         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2517         .masters        = omap44xx_ipu_masters,
2518         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2519         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2520 };
2521
2522 /*
2523  * 'iss' class
2524  * external images sensor pixel data processor
2525  */
2526
2527 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2528         .rev_offs       = 0x0000,
2529         .sysc_offs      = 0x0010,
2530         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2531                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2532         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2533                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2534                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2535         .sysc_fields    = &omap_hwmod_sysc_type2,
2536 };
2537
2538 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2539         .name   = "iss",
2540         .sysc   = &omap44xx_iss_sysc,
2541 };
2542
2543 /* iss */
2544 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2545         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2546         { .irq = -1 }
2547 };
2548
2549 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2550         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2551         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2552         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2553         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2554         { .dma_req = -1 }
2555 };
2556
2557 /* iss master ports */
2558 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2559         &omap44xx_iss__l3_main_2,
2560 };
2561
2562 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2563         {
2564                 .pa_start       = 0x52000000,
2565                 .pa_end         = 0x520000ff,
2566                 .flags          = ADDR_TYPE_RT
2567         },
2568         { }
2569 };
2570
2571 /* l3_main_2 -> iss */
2572 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2573         .master         = &omap44xx_l3_main_2_hwmod,
2574         .slave          = &omap44xx_iss_hwmod,
2575         .clk            = "l3_div_ck",
2576         .addr           = omap44xx_iss_addrs,
2577         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2578 };
2579
2580 /* iss slave ports */
2581 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2582         &omap44xx_l3_main_2__iss,
2583 };
2584
2585 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2586         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2587 };
2588
2589 static struct omap_hwmod omap44xx_iss_hwmod = {
2590         .name           = "iss",
2591         .class          = &omap44xx_iss_hwmod_class,
2592         .clkdm_name     = "iss_clkdm",
2593         .mpu_irqs       = omap44xx_iss_irqs,
2594         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2595         .main_clk       = "iss_fck",
2596         .prcm = {
2597                 .omap4 = {
2598                         .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2599                 },
2600         },
2601         .opt_clks       = iss_opt_clks,
2602         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2603         .slaves         = omap44xx_iss_slaves,
2604         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2605         .masters        = omap44xx_iss_masters,
2606         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2607         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2608 };
2609
2610 /*
2611  * 'iva' class
2612  * multi-standard video encoder/decoder hardware accelerator
2613  */
2614
2615 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2616         .name   = "iva",
2617 };
2618
2619 /* iva */
2620 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2621         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2622         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2623         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2624         { .irq = -1 }
2625 };
2626
2627 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2628         { .name = "logic", .rst_shift = 2 },
2629 };
2630
2631 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2632         { .name = "seq0", .rst_shift = 0 },
2633 };
2634
2635 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2636         { .name = "seq1", .rst_shift = 1 },
2637 };
2638
2639 /* iva master ports */
2640 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2641         &omap44xx_iva__l3_main_2,
2642         &omap44xx_iva__l3_instr,
2643 };
2644
2645 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2646         {
2647                 .pa_start       = 0x5a000000,
2648                 .pa_end         = 0x5a07ffff,
2649                 .flags          = ADDR_TYPE_RT
2650         },
2651         { }
2652 };
2653
2654 /* l3_main_2 -> iva */
2655 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2656         .master         = &omap44xx_l3_main_2_hwmod,
2657         .slave          = &omap44xx_iva_hwmod,
2658         .clk            = "l3_div_ck",
2659         .addr           = omap44xx_iva_addrs,
2660         .user           = OCP_USER_MPU,
2661 };
2662
2663 /* iva slave ports */
2664 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2665         &omap44xx_dsp__iva,
2666         &omap44xx_l3_main_2__iva,
2667 };
2668
2669 /* Pseudo hwmod for reset control purpose only */
2670 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2671         .name           = "iva_seq0",
2672         .class          = &omap44xx_iva_hwmod_class,
2673         .clkdm_name     = "ivahd_clkdm",
2674         .flags          = HWMOD_INIT_NO_RESET,
2675         .rst_lines      = omap44xx_iva_seq0_resets,
2676         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2677         .prcm = {
2678                 .omap4 = {
2679                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2680                 },
2681         },
2682         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2683 };
2684
2685 /* Pseudo hwmod for reset control purpose only */
2686 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2687         .name           = "iva_seq1",
2688         .class          = &omap44xx_iva_hwmod_class,
2689         .clkdm_name     = "ivahd_clkdm",
2690         .flags          = HWMOD_INIT_NO_RESET,
2691         .rst_lines      = omap44xx_iva_seq1_resets,
2692         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2693         .prcm = {
2694                 .omap4 = {
2695                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2696                 },
2697         },
2698         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2699 };
2700
2701 static struct omap_hwmod omap44xx_iva_hwmod = {
2702         .name           = "iva",
2703         .class          = &omap44xx_iva_hwmod_class,
2704         .clkdm_name     = "ivahd_clkdm",
2705         .mpu_irqs       = omap44xx_iva_irqs,
2706         .rst_lines      = omap44xx_iva_resets,
2707         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2708         .main_clk       = "iva_fck",
2709         .prcm = {
2710                 .omap4 = {
2711                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2712                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2713                 },
2714         },
2715         .slaves         = omap44xx_iva_slaves,
2716         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2717         .masters        = omap44xx_iva_masters,
2718         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2719         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2720 };
2721
2722 /*
2723  * 'kbd' class
2724  * keyboard controller
2725  */
2726
2727 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2728         .rev_offs       = 0x0000,
2729         .sysc_offs      = 0x0010,
2730         .syss_offs      = 0x0014,
2731         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2732                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2733                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2734                            SYSS_HAS_RESET_STATUS),
2735         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2736         .sysc_fields    = &omap_hwmod_sysc_type1,
2737 };
2738
2739 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2740         .name   = "kbd",
2741         .sysc   = &omap44xx_kbd_sysc,
2742 };
2743
2744 /* kbd */
2745 static struct omap_hwmod omap44xx_kbd_hwmod;
2746 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2747         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2748         { .irq = -1 }
2749 };
2750
2751 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2752         {
2753                 .pa_start       = 0x4a31c000,
2754                 .pa_end         = 0x4a31c07f,
2755                 .flags          = ADDR_TYPE_RT
2756         },
2757         { }
2758 };
2759
2760 /* l4_wkup -> kbd */
2761 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2762         .master         = &omap44xx_l4_wkup_hwmod,
2763         .slave          = &omap44xx_kbd_hwmod,
2764         .clk            = "l4_wkup_clk_mux_ck",
2765         .addr           = omap44xx_kbd_addrs,
2766         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2767 };
2768
2769 /* kbd slave ports */
2770 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2771         &omap44xx_l4_wkup__kbd,
2772 };
2773
2774 static struct omap_hwmod omap44xx_kbd_hwmod = {
2775         .name           = "kbd",
2776         .class          = &omap44xx_kbd_hwmod_class,
2777         .clkdm_name     = "l4_wkup_clkdm",
2778         .mpu_irqs       = omap44xx_kbd_irqs,
2779         .main_clk       = "kbd_fck",
2780         .prcm = {
2781                 .omap4 = {
2782                         .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2783                 },
2784         },
2785         .slaves         = omap44xx_kbd_slaves,
2786         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2787         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2788 };
2789
2790 /*
2791  * 'mailbox' class
2792  * mailbox module allowing communication between the on-chip processors using a
2793  * queued mailbox-interrupt mechanism.
2794  */
2795
2796 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2797         .rev_offs       = 0x0000,
2798         .sysc_offs      = 0x0010,
2799         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2800                            SYSC_HAS_SOFTRESET),
2801         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2802         .sysc_fields    = &omap_hwmod_sysc_type2,
2803 };
2804
2805 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2806         .name   = "mailbox",
2807         .sysc   = &omap44xx_mailbox_sysc,
2808 };
2809
2810 /* mailbox */
2811 static struct omap_hwmod omap44xx_mailbox_hwmod;
2812 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2813         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2814         { .irq = -1 }
2815 };
2816
2817 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2818         {
2819                 .pa_start       = 0x4a0f4000,
2820                 .pa_end         = 0x4a0f41ff,
2821                 .flags          = ADDR_TYPE_RT
2822         },
2823         { }
2824 };
2825
2826 /* l4_cfg -> mailbox */
2827 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2828         .master         = &omap44xx_l4_cfg_hwmod,
2829         .slave          = &omap44xx_mailbox_hwmod,
2830         .clk            = "l4_div_ck",
2831         .addr           = omap44xx_mailbox_addrs,
2832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2833 };
2834
2835 /* mailbox slave ports */
2836 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2837         &omap44xx_l4_cfg__mailbox,
2838 };
2839
2840 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2841         .name           = "mailbox",
2842         .class          = &omap44xx_mailbox_hwmod_class,
2843         .clkdm_name     = "l4_cfg_clkdm",
2844         .mpu_irqs       = omap44xx_mailbox_irqs,
2845         .prcm = {
2846                 .omap4 = {
2847                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2848                 },
2849         },
2850         .slaves         = omap44xx_mailbox_slaves,
2851         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2852         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2853 };
2854
2855 /*
2856  * 'mcbsp' class
2857  * multi channel buffered serial port controller
2858  */
2859
2860 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2861         .sysc_offs      = 0x008c,
2862         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2863                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2864         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2865         .sysc_fields    = &omap_hwmod_sysc_type1,
2866 };
2867
2868 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2869         .name   = "mcbsp",
2870         .sysc   = &omap44xx_mcbsp_sysc,
2871         .rev    = MCBSP_CONFIG_TYPE4,
2872 };
2873
2874 /* mcbsp1 */
2875 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2876 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2877         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2878         { .irq = -1 }
2879 };
2880
2881 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2882         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2883         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2884         { .dma_req = -1 }
2885 };
2886
2887 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2888         {
2889                 .name           = "mpu",
2890                 .pa_start       = 0x40122000,
2891                 .pa_end         = 0x401220ff,
2892                 .flags          = ADDR_TYPE_RT
2893         },
2894         { }
2895 };
2896
2897 /* l4_abe -> mcbsp1 */
2898 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2899         .master         = &omap44xx_l4_abe_hwmod,
2900         .slave          = &omap44xx_mcbsp1_hwmod,
2901         .clk            = "ocp_abe_iclk",
2902         .addr           = omap44xx_mcbsp1_addrs,
2903         .user           = OCP_USER_MPU,
2904 };
2905
2906 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2907         {
2908                 .name           = "dma",
2909                 .pa_start       = 0x49022000,
2910                 .pa_end         = 0x490220ff,
2911                 .flags          = ADDR_TYPE_RT
2912         },
2913         { }
2914 };
2915
2916 /* l4_abe -> mcbsp1 (dma) */
2917 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2918         .master         = &omap44xx_l4_abe_hwmod,
2919         .slave          = &omap44xx_mcbsp1_hwmod,
2920         .clk            = "ocp_abe_iclk",
2921         .addr           = omap44xx_mcbsp1_dma_addrs,
2922         .user           = OCP_USER_SDMA,
2923 };
2924
2925 /* mcbsp1 slave ports */
2926 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2927         &omap44xx_l4_abe__mcbsp1,
2928         &omap44xx_l4_abe__mcbsp1_dma,
2929 };
2930
2931 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2932         .name           = "mcbsp1",
2933         .class          = &omap44xx_mcbsp_hwmod_class,
2934         .clkdm_name     = "abe_clkdm",
2935         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2936         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2937         .main_clk       = "mcbsp1_fck",
2938         .prcm = {
2939                 .omap4 = {
2940                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2941                 },
2942         },
2943         .slaves         = omap44xx_mcbsp1_slaves,
2944         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2945         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2946 };
2947
2948 /* mcbsp2 */
2949 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2950 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2951         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2952         { .irq = -1 }
2953 };
2954
2955 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2956         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2957         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2958         { .dma_req = -1 }
2959 };
2960
2961 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2962         {
2963                 .name           = "mpu",
2964                 .pa_start       = 0x40124000,
2965                 .pa_end         = 0x401240ff,
2966                 .flags          = ADDR_TYPE_RT
2967         },
2968         { }
2969 };
2970
2971 /* l4_abe -> mcbsp2 */
2972 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2973         .master         = &omap44xx_l4_abe_hwmod,
2974         .slave          = &omap44xx_mcbsp2_hwmod,
2975         .clk            = "ocp_abe_iclk",
2976         .addr           = omap44xx_mcbsp2_addrs,
2977         .user           = OCP_USER_MPU,
2978 };
2979
2980 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2981         {
2982                 .name           = "dma",
2983                 .pa_start       = 0x49024000,
2984                 .pa_end         = 0x490240ff,
2985                 .flags          = ADDR_TYPE_RT
2986         },
2987         { }
2988 };
2989
2990 /* l4_abe -> mcbsp2 (dma) */
2991 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2992         .master         = &omap44xx_l4_abe_hwmod,
2993         .slave          = &omap44xx_mcbsp2_hwmod,
2994         .clk            = "ocp_abe_iclk",
2995         .addr           = omap44xx_mcbsp2_dma_addrs,
2996         .user           = OCP_USER_SDMA,
2997 };
2998
2999 /* mcbsp2 slave ports */
3000 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3001         &omap44xx_l4_abe__mcbsp2,
3002         &omap44xx_l4_abe__mcbsp2_dma,
3003 };
3004
3005 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3006         .name           = "mcbsp2",
3007         .class          = &omap44xx_mcbsp_hwmod_class,
3008         .clkdm_name     = "abe_clkdm",
3009         .mpu_irqs       = omap44xx_mcbsp2_irqs,
3010         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
3011         .main_clk       = "mcbsp2_fck",
3012         .prcm = {
3013                 .omap4 = {
3014                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
3015                 },
3016         },
3017         .slaves         = omap44xx_mcbsp2_slaves,
3018         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3019         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3020 };
3021
3022 /* mcbsp3 */
3023 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3024 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3025         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3026         { .irq = -1 }
3027 };
3028
3029 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3030         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3031         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3032         { .dma_req = -1 }
3033 };
3034
3035 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3036         {
3037                 .name           = "mpu",
3038                 .pa_start       = 0x40126000,
3039                 .pa_end         = 0x401260ff,
3040                 .flags          = ADDR_TYPE_RT
3041         },
3042         { }
3043 };
3044
3045 /* l4_abe -> mcbsp3 */
3046 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3047         .master         = &omap44xx_l4_abe_hwmod,
3048         .slave          = &omap44xx_mcbsp3_hwmod,
3049         .clk            = "ocp_abe_iclk",
3050         .addr           = omap44xx_mcbsp3_addrs,
3051         .user           = OCP_USER_MPU,
3052 };
3053
3054 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3055         {
3056                 .name           = "dma",
3057                 .pa_start       = 0x49026000,
3058                 .pa_end         = 0x490260ff,
3059                 .flags          = ADDR_TYPE_RT
3060         },
3061         { }
3062 };
3063
3064 /* l4_abe -> mcbsp3 (dma) */
3065 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3066         .master         = &omap44xx_l4_abe_hwmod,
3067         .slave          = &omap44xx_mcbsp3_hwmod,
3068         .clk            = "ocp_abe_iclk",
3069         .addr           = omap44xx_mcbsp3_dma_addrs,
3070         .user           = OCP_USER_SDMA,
3071 };
3072
3073 /* mcbsp3 slave ports */
3074 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3075         &omap44xx_l4_abe__mcbsp3,
3076         &omap44xx_l4_abe__mcbsp3_dma,
3077 };
3078
3079 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3080         .name           = "mcbsp3",
3081         .class          = &omap44xx_mcbsp_hwmod_class,
3082         .clkdm_name     = "abe_clkdm",
3083         .mpu_irqs       = omap44xx_mcbsp3_irqs,
3084         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
3085         .main_clk       = "mcbsp3_fck",
3086         .prcm = {
3087                 .omap4 = {
3088                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
3089                 },
3090         },
3091         .slaves         = omap44xx_mcbsp3_slaves,
3092         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3093         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3094 };
3095
3096 /* mcbsp4 */
3097 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3098 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3099         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3100         { .irq = -1 }
3101 };
3102
3103 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3104         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3105         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3106         { .dma_req = -1 }
3107 };
3108
3109 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3110         {
3111                 .pa_start       = 0x48096000,
3112                 .pa_end         = 0x480960ff,
3113                 .flags          = ADDR_TYPE_RT
3114         },
3115         { }
3116 };
3117
3118 /* l4_per -> mcbsp4 */
3119 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3120         .master         = &omap44xx_l4_per_hwmod,
3121         .slave          = &omap44xx_mcbsp4_hwmod,
3122         .clk            = "l4_div_ck",
3123         .addr           = omap44xx_mcbsp4_addrs,
3124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3125 };
3126
3127 /* mcbsp4 slave ports */
3128 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3129         &omap44xx_l4_per__mcbsp4,
3130 };
3131
3132 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3133         .name           = "mcbsp4",
3134         .class          = &omap44xx_mcbsp_hwmod_class,
3135         .clkdm_name     = "l4_per_clkdm",
3136         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3137         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3138         .main_clk       = "mcbsp4_fck",
3139         .prcm = {
3140                 .omap4 = {
3141                         .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3142                 },
3143         },
3144         .slaves         = omap44xx_mcbsp4_slaves,
3145         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3146         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3147 };
3148
3149 /*
3150  * 'mcpdm' class
3151  * multi channel pdm controller (proprietary interface with phoenix power
3152  * ic)
3153  */
3154
3155 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3156         .rev_offs       = 0x0000,
3157         .sysc_offs      = 0x0010,
3158         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3159                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3160         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3161                            SIDLE_SMART_WKUP),
3162         .sysc_fields    = &omap_hwmod_sysc_type2,
3163 };
3164
3165 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3166         .name   = "mcpdm",
3167         .sysc   = &omap44xx_mcpdm_sysc,
3168 };
3169
3170 /* mcpdm */
3171 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3172 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3173         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3174         { .irq = -1 }
3175 };
3176
3177 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3178         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3179         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3180         { .dma_req = -1 }
3181 };
3182
3183 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3184         {
3185                 .pa_start       = 0x40132000,
3186                 .pa_end         = 0x4013207f,
3187                 .flags          = ADDR_TYPE_RT
3188         },
3189         { }
3190 };
3191
3192 /* l4_abe -> mcpdm */
3193 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3194         .master         = &omap44xx_l4_abe_hwmod,
3195         .slave          = &omap44xx_mcpdm_hwmod,
3196         .clk            = "ocp_abe_iclk",
3197         .addr           = omap44xx_mcpdm_addrs,
3198         .user           = OCP_USER_MPU,
3199 };
3200
3201 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3202         {
3203                 .pa_start       = 0x49032000,
3204                 .pa_end         = 0x4903207f,
3205                 .flags          = ADDR_TYPE_RT
3206         },
3207         { }
3208 };
3209
3210 /* l4_abe -> mcpdm (dma) */
3211 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3212         .master         = &omap44xx_l4_abe_hwmod,
3213         .slave          = &omap44xx_mcpdm_hwmod,
3214         .clk            = "ocp_abe_iclk",
3215         .addr           = omap44xx_mcpdm_dma_addrs,
3216         .user           = OCP_USER_SDMA,
3217 };
3218
3219 /* mcpdm slave ports */
3220 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3221         &omap44xx_l4_abe__mcpdm,
3222         &omap44xx_l4_abe__mcpdm_dma,
3223 };
3224
3225 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3226         .name           = "mcpdm",
3227         .class          = &omap44xx_mcpdm_hwmod_class,
3228         .clkdm_name     = "abe_clkdm",
3229         .mpu_irqs       = omap44xx_mcpdm_irqs,
3230         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3231         .main_clk       = "mcpdm_fck",
3232         .prcm = {
3233                 .omap4 = {
3234                         .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3235                 },
3236         },
3237         .slaves         = omap44xx_mcpdm_slaves,
3238         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3239         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3240 };
3241
3242 /*
3243  * 'mcspi' class
3244  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3245  * bus
3246  */
3247
3248 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3249         .rev_offs       = 0x0000,
3250         .sysc_offs      = 0x0010,
3251         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3252                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3253         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3254                            SIDLE_SMART_WKUP),
3255         .sysc_fields    = &omap_hwmod_sysc_type2,
3256 };
3257
3258 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3259         .name   = "mcspi",
3260         .sysc   = &omap44xx_mcspi_sysc,
3261         .rev    = OMAP4_MCSPI_REV,
3262 };
3263
3264 /* mcspi1 */
3265 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3266 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3267         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3268         { .irq = -1 }
3269 };
3270
3271 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3272         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3273         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3274         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3275         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3276         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3277         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3278         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3279         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3280         { .dma_req = -1 }
3281 };
3282
3283 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3284         {
3285                 .pa_start       = 0x48098000,
3286                 .pa_end         = 0x480981ff,
3287                 .flags          = ADDR_TYPE_RT
3288         },
3289         { }
3290 };
3291
3292 /* l4_per -> mcspi1 */
3293 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3294         .master         = &omap44xx_l4_per_hwmod,
3295         .slave          = &omap44xx_mcspi1_hwmod,
3296         .clk            = "l4_div_ck",
3297         .addr           = omap44xx_mcspi1_addrs,
3298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3299 };
3300
3301 /* mcspi1 slave ports */
3302 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3303         &omap44xx_l4_per__mcspi1,
3304 };
3305
3306 /* mcspi1 dev_attr */
3307 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3308         .num_chipselect = 4,
3309 };
3310
3311 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3312         .name           = "mcspi1",
3313         .class          = &omap44xx_mcspi_hwmod_class,
3314         .clkdm_name     = "l4_per_clkdm",
3315         .mpu_irqs       = omap44xx_mcspi1_irqs,
3316         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3317         .main_clk       = "mcspi1_fck",
3318         .prcm = {
3319                 .omap4 = {
3320                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3321                 },
3322         },
3323         .dev_attr       = &mcspi1_dev_attr,
3324         .slaves         = omap44xx_mcspi1_slaves,
3325         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3326         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3327 };
3328
3329 /* mcspi2 */
3330 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3331 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3332         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3333         { .irq = -1 }
3334 };
3335
3336 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3337         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3338         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3339         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3340         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3341         { .dma_req = -1 }
3342 };
3343
3344 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3345         {
3346                 .pa_start       = 0x4809a000,
3347                 .pa_end         = 0x4809a1ff,
3348                 .flags          = ADDR_TYPE_RT
3349         },
3350         { }
3351 };
3352
3353 /* l4_per -> mcspi2 */
3354 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3355         .master         = &omap44xx_l4_per_hwmod,
3356         .slave          = &omap44xx_mcspi2_hwmod,
3357         .clk            = "l4_div_ck",
3358         .addr           = omap44xx_mcspi2_addrs,
3359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3360 };
3361
3362 /* mcspi2 slave ports */
3363 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3364         &omap44xx_l4_per__mcspi2,
3365 };
3366
3367 /* mcspi2 dev_attr */
3368 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3369         .num_chipselect = 2,
3370 };
3371
3372 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3373         .name           = "mcspi2",
3374         .class          = &omap44xx_mcspi_hwmod_class,
3375         .clkdm_name     = "l4_per_clkdm",
3376         .mpu_irqs       = omap44xx_mcspi2_irqs,
3377         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3378         .main_clk       = "mcspi2_fck",
3379         .prcm = {
3380                 .omap4 = {
3381                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3382                 },
3383         },
3384         .dev_attr       = &mcspi2_dev_attr,
3385         .slaves         = omap44xx_mcspi2_slaves,
3386         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3387         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3388 };
3389
3390 /* mcspi3 */
3391 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3392 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3393         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3394         { .irq = -1 }
3395 };
3396
3397 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3398         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3399         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3400         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3401         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3402         { .dma_req = -1 }
3403 };
3404
3405 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3406         {
3407                 .pa_start       = 0x480b8000,
3408                 .pa_end         = 0x480b81ff,
3409                 .flags          = ADDR_TYPE_RT
3410         },
3411         { }
3412 };
3413
3414 /* l4_per -> mcspi3 */
3415 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3416         .master         = &omap44xx_l4_per_hwmod,
3417         .slave          = &omap44xx_mcspi3_hwmod,
3418         .clk            = "l4_div_ck",
3419         .addr           = omap44xx_mcspi3_addrs,
3420         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3421 };
3422
3423 /* mcspi3 slave ports */
3424 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3425         &omap44xx_l4_per__mcspi3,
3426 };
3427
3428 /* mcspi3 dev_attr */
3429 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3430         .num_chipselect = 2,
3431 };
3432
3433 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3434         .name           = "mcspi3",
3435         .class          = &omap44xx_mcspi_hwmod_class,
3436         .clkdm_name     = "l4_per_clkdm",
3437         .mpu_irqs       = omap44xx_mcspi3_irqs,
3438         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3439         .main_clk       = "mcspi3_fck",
3440         .prcm = {
3441                 .omap4 = {
3442                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3443                 },
3444         },
3445         .dev_attr       = &mcspi3_dev_attr,
3446         .slaves         = omap44xx_mcspi3_slaves,
3447         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3448         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3449 };
3450
3451 /* mcspi4 */
3452 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3453 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3454         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3455         { .irq = -1 }
3456 };
3457
3458 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3459         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3460         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3461         { .dma_req = -1 }
3462 };
3463
3464 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3465         {
3466                 .pa_start       = 0x480ba000,
3467                 .pa_end         = 0x480ba1ff,
3468                 .flags          = ADDR_TYPE_RT
3469         },
3470         { }
3471 };
3472
3473 /* l4_per -> mcspi4 */
3474 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3475         .master         = &omap44xx_l4_per_hwmod,
3476         .slave          = &omap44xx_mcspi4_hwmod,
3477         .clk            = "l4_div_ck",
3478         .addr           = omap44xx_mcspi4_addrs,
3479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3480 };
3481
3482 /* mcspi4 slave ports */
3483 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3484         &omap44xx_l4_per__mcspi4,
3485 };
3486
3487 /* mcspi4 dev_attr */
3488 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3489         .num_chipselect = 1,
3490 };
3491
3492 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3493         .name           = "mcspi4",
3494         .class          = &omap44xx_mcspi_hwmod_class,
3495         .clkdm_name     = "l4_per_clkdm",
3496         .mpu_irqs       = omap44xx_mcspi4_irqs,
3497         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3498         .main_clk       = "mcspi4_fck",
3499         .prcm = {
3500                 .omap4 = {
3501                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3502                 },
3503         },
3504         .dev_attr       = &mcspi4_dev_attr,
3505         .slaves         = omap44xx_mcspi4_slaves,
3506         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3507         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3508 };
3509
3510 /*
3511  * 'mmc' class
3512  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3513  */
3514
3515 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3516         .rev_offs       = 0x0000,
3517         .sysc_offs      = 0x0010,
3518         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3519                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3520                            SYSC_HAS_SOFTRESET),
3521         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3522                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3523                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3524         .sysc_fields    = &omap_hwmod_sysc_type2,
3525 };
3526
3527 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3528         .name   = "mmc",
3529         .sysc   = &omap44xx_mmc_sysc,
3530 };
3531
3532 /* mmc1 */
3533 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3534         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3535         { .irq = -1 }
3536 };
3537
3538 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3539         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3540         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3541         { .dma_req = -1 }
3542 };
3543
3544 /* mmc1 master ports */
3545 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3546         &omap44xx_mmc1__l3_main_1,
3547 };
3548
3549 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3550         {
3551                 .pa_start       = 0x4809c000,
3552                 .pa_end         = 0x4809c3ff,
3553                 .flags          = ADDR_TYPE_RT
3554         },
3555         { }
3556 };
3557
3558 /* l4_per -> mmc1 */
3559 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3560         .master         = &omap44xx_l4_per_hwmod,
3561         .slave          = &omap44xx_mmc1_hwmod,
3562         .clk            = "l4_div_ck",
3563         .addr           = omap44xx_mmc1_addrs,
3564         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3565 };
3566
3567 /* mmc1 slave ports */
3568 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3569         &omap44xx_l4_per__mmc1,
3570 };
3571
3572 /* mmc1 dev_attr */
3573 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3574         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3575 };
3576
3577 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3578         .name           = "mmc1",
3579         .class          = &omap44xx_mmc_hwmod_class,
3580         .clkdm_name     = "l3_init_clkdm",
3581         .mpu_irqs       = omap44xx_mmc1_irqs,
3582         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3583         .main_clk       = "mmc1_fck",
3584         .prcm = {
3585                 .omap4 = {
3586                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3587                 },
3588         },
3589         .dev_attr       = &mmc1_dev_attr,
3590         .slaves         = omap44xx_mmc1_slaves,
3591         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3592         .masters        = omap44xx_mmc1_masters,
3593         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3594         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3595 };
3596
3597 /* mmc2 */
3598 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3599         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3600         { .irq = -1 }
3601 };
3602
3603 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3604         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3605         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3606         { .dma_req = -1 }
3607 };
3608
3609 /* mmc2 master ports */
3610 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3611         &omap44xx_mmc2__l3_main_1,
3612 };
3613
3614 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3615         {
3616                 .pa_start       = 0x480b4000,
3617                 .pa_end         = 0x480b43ff,
3618                 .flags          = ADDR_TYPE_RT
3619         },
3620         { }
3621 };
3622
3623 /* l4_per -> mmc2 */
3624 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3625         .master         = &omap44xx_l4_per_hwmod,
3626         .slave          = &omap44xx_mmc2_hwmod,
3627         .clk            = "l4_div_ck",
3628         .addr           = omap44xx_mmc2_addrs,
3629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3630 };
3631
3632 /* mmc2 slave ports */
3633 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3634         &omap44xx_l4_per__mmc2,
3635 };
3636
3637 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3638         .name           = "mmc2",
3639         .class          = &omap44xx_mmc_hwmod_class,
3640         .clkdm_name     = "l3_init_clkdm",
3641         .mpu_irqs       = omap44xx_mmc2_irqs,
3642         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3643         .main_clk       = "mmc2_fck",
3644         .prcm = {
3645                 .omap4 = {
3646                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3647                 },
3648         },
3649         .slaves         = omap44xx_mmc2_slaves,
3650         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3651         .masters        = omap44xx_mmc2_masters,
3652         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3653         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3654 };
3655
3656 /* mmc3 */
3657 static struct omap_hwmod omap44xx_mmc3_hwmod;
3658 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3659         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3660         { .irq = -1 }
3661 };
3662
3663 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3664         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3665         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3666         { .dma_req = -1 }
3667 };
3668
3669 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3670         {
3671                 .pa_start       = 0x480ad000,
3672                 .pa_end         = 0x480ad3ff,
3673                 .flags          = ADDR_TYPE_RT
3674         },
3675         { }
3676 };
3677
3678 /* l4_per -> mmc3 */
3679 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3680         .master         = &omap44xx_l4_per_hwmod,
3681         .slave          = &omap44xx_mmc3_hwmod,
3682         .clk            = "l4_div_ck",
3683         .addr           = omap44xx_mmc3_addrs,
3684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3685 };
3686
3687 /* mmc3 slave ports */
3688 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3689         &omap44xx_l4_per__mmc3,
3690 };
3691
3692 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3693         .name           = "mmc3",
3694         .class          = &omap44xx_mmc_hwmod_class,
3695         .clkdm_name     = "l4_per_clkdm",
3696         .mpu_irqs       = omap44xx_mmc3_irqs,
3697         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3698         .main_clk       = "mmc3_fck",
3699         .prcm = {
3700                 .omap4 = {
3701                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3702                 },
3703         },
3704         .slaves         = omap44xx_mmc3_slaves,
3705         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3706         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3707 };
3708
3709 /* mmc4 */
3710 static struct omap_hwmod omap44xx_mmc4_hwmod;
3711 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3712         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3713         { .irq = -1 }
3714 };
3715
3716 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3717         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3718         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3719         { .dma_req = -1 }
3720 };
3721
3722 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3723         {
3724                 .pa_start       = 0x480d1000,
3725                 .pa_end         = 0x480d13ff,
3726                 .flags          = ADDR_TYPE_RT
3727         },
3728         { }
3729 };
3730
3731 /* l4_per -> mmc4 */
3732 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3733         .master         = &omap44xx_l4_per_hwmod,
3734         .slave          = &omap44xx_mmc4_hwmod,
3735         .clk            = "l4_div_ck",
3736         .addr           = omap44xx_mmc4_addrs,
3737         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3738 };
3739
3740 /* mmc4 slave ports */
3741 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3742         &omap44xx_l4_per__mmc4,
3743 };
3744
3745 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3746         .name           = "mmc4",
3747         .class          = &omap44xx_mmc_hwmod_class,
3748         .clkdm_name     = "l4_per_clkdm",
3749         .mpu_irqs       = omap44xx_mmc4_irqs,
3750
3751         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3752         .main_clk       = "mmc4_fck",
3753         .prcm = {
3754                 .omap4 = {
3755                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3756                 },
3757         },
3758         .slaves         = omap44xx_mmc4_slaves,
3759         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3760         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3761 };
3762
3763 /* mmc5 */
3764 static struct omap_hwmod omap44xx_mmc5_hwmod;
3765 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3766         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3767         { .irq = -1 }
3768 };
3769
3770 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3771         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3772         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3773         { .dma_req = -1 }
3774 };
3775
3776 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3777         {
3778                 .pa_start       = 0x480d5000,
3779                 .pa_end         = 0x480d53ff,
3780                 .flags          = ADDR_TYPE_RT
3781         },
3782         { }
3783 };
3784
3785 /* l4_per -> mmc5 */
3786 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3787         .master         = &omap44xx_l4_per_hwmod,
3788         .slave          = &omap44xx_mmc5_hwmod,
3789         .clk            = "l4_div_ck",
3790         .addr           = omap44xx_mmc5_addrs,
3791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3792 };
3793
3794 /* mmc5 slave ports */
3795 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3796         &omap44xx_l4_per__mmc5,
3797 };
3798
3799 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3800         .name           = "mmc5",
3801         .class          = &omap44xx_mmc_hwmod_class,
3802         .clkdm_name     = "l4_per_clkdm",
3803         .mpu_irqs       = omap44xx_mmc5_irqs,
3804         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3805         .main_clk       = "mmc5_fck",
3806         .prcm = {
3807                 .omap4 = {
3808                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3809                 },
3810         },
3811         .slaves         = omap44xx_mmc5_slaves,
3812         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3813         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3814 };
3815
3816 /*
3817  * 'mpu' class
3818  * mpu sub-system
3819  */
3820
3821 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3822         .name   = "mpu",
3823 };
3824
3825 /* mpu */
3826 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3827         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3828         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3829         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3830         { .irq = -1 }
3831 };
3832
3833 /* mpu master ports */
3834 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3835         &omap44xx_mpu__l3_main_1,
3836         &omap44xx_mpu__l4_abe,
3837         &omap44xx_mpu__dmm,
3838 };
3839
3840 static struct omap_hwmod omap44xx_mpu_hwmod = {
3841         .name           = "mpu",
3842         .class          = &omap44xx_mpu_hwmod_class,
3843         .clkdm_name     = "mpuss_clkdm",
3844         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3845         .mpu_irqs       = omap44xx_mpu_irqs,
3846         .main_clk       = "dpll_mpu_m2_ck",
3847         .prcm = {
3848                 .omap4 = {
3849                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3850                 },
3851         },
3852         .masters        = omap44xx_mpu_masters,
3853         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3854         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3855 };
3856
3857 /*
3858  * 'smartreflex' class
3859  * smartreflex module (monitor silicon performance and outputs a measure of
3860  * performance error)
3861  */
3862
3863 /* The IP is not compliant to type1 / type2 scheme */
3864 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3865         .sidle_shift    = 24,
3866         .enwkup_shift   = 26,
3867 };
3868
3869 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3870         .sysc_offs      = 0x0038,
3871         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3872         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3873                            SIDLE_SMART_WKUP),
3874         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3875 };
3876
3877 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3878         .name   = "smartreflex",
3879         .sysc   = &omap44xx_smartreflex_sysc,
3880         .rev    = 2,
3881 };
3882
3883 /* smartreflex_core */
3884 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3885 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3886         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3887         { .irq = -1 }
3888 };
3889
3890 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3891         {
3892                 .pa_start       = 0x4a0dd000,
3893                 .pa_end         = 0x4a0dd03f,
3894                 .flags          = ADDR_TYPE_RT
3895         },
3896         { }
3897 };
3898
3899 /* l4_cfg -> smartreflex_core */
3900 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3901         .master         = &omap44xx_l4_cfg_hwmod,
3902         .slave          = &omap44xx_smartreflex_core_hwmod,
3903         .clk            = "l4_div_ck",
3904         .addr           = omap44xx_smartreflex_core_addrs,
3905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3906 };
3907
3908 /* smartreflex_core slave ports */
3909 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3910         &omap44xx_l4_cfg__smartreflex_core,
3911 };
3912
3913 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3914         .name           = "smartreflex_core",
3915         .class          = &omap44xx_smartreflex_hwmod_class,
3916         .clkdm_name     = "l4_ao_clkdm",
3917         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3918
3919         .main_clk       = "smartreflex_core_fck",
3920         .vdd_name       = "core",
3921         .prcm = {
3922                 .omap4 = {
3923                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3924                 },
3925         },
3926         .slaves         = omap44xx_smartreflex_core_slaves,
3927         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3928         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3929 };
3930
3931 /* smartreflex_iva */
3932 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3933 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3934         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3935         { .irq = -1 }
3936 };
3937
3938 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3939         {
3940                 .pa_start       = 0x4a0db000,
3941                 .pa_end         = 0x4a0db03f,
3942                 .flags          = ADDR_TYPE_RT
3943         },
3944         { }
3945 };
3946
3947 /* l4_cfg -> smartreflex_iva */
3948 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3949         .master         = &omap44xx_l4_cfg_hwmod,
3950         .slave          = &omap44xx_smartreflex_iva_hwmod,
3951         .clk            = "l4_div_ck",
3952         .addr           = omap44xx_smartreflex_iva_addrs,
3953         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3954 };
3955
3956 /* smartreflex_iva slave ports */
3957 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3958         &omap44xx_l4_cfg__smartreflex_iva,
3959 };
3960
3961 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3962         .name           = "smartreflex_iva",
3963         .class          = &omap44xx_smartreflex_hwmod_class,
3964         .clkdm_name     = "l4_ao_clkdm",
3965         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3966         .main_clk       = "smartreflex_iva_fck",
3967         .vdd_name       = "iva",
3968         .prcm = {
3969                 .omap4 = {
3970                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3971                 },
3972         },
3973         .slaves         = omap44xx_smartreflex_iva_slaves,
3974         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3975         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3976 };
3977
3978 /* smartreflex_mpu */
3979 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3980 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3981         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3982         { .irq = -1 }
3983 };
3984
3985 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3986         {
3987                 .pa_start       = 0x4a0d9000,
3988                 .pa_end         = 0x4a0d903f,
3989                 .flags          = ADDR_TYPE_RT
3990         },
3991         { }
3992 };
3993
3994 /* l4_cfg -> smartreflex_mpu */
3995 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3996         .master         = &omap44xx_l4_cfg_hwmod,
3997         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3998         .clk            = "l4_div_ck",
3999         .addr           = omap44xx_smartreflex_mpu_addrs,
4000         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4001 };
4002
4003 /* smartreflex_mpu slave ports */
4004 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4005         &omap44xx_l4_cfg__smartreflex_mpu,
4006 };
4007
4008 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4009         .name           = "smartreflex_mpu",
4010         .class          = &omap44xx_smartreflex_hwmod_class,
4011         .clkdm_name     = "l4_ao_clkdm",
4012         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
4013         .main_clk       = "smartreflex_mpu_fck",
4014         .vdd_name       = "mpu",
4015         .prcm = {
4016                 .omap4 = {
4017                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
4018                 },
4019         },
4020         .slaves         = omap44xx_smartreflex_mpu_slaves,
4021         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4022         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4023 };
4024
4025 /*
4026  * 'spinlock' class
4027  * spinlock provides hardware assistance for synchronizing the processes
4028  * running on multiple processors
4029  */
4030
4031 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4032         .rev_offs       = 0x0000,
4033         .sysc_offs      = 0x0010,
4034         .syss_offs      = 0x0014,
4035         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4036                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4037                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4038         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4039                            SIDLE_SMART_WKUP),
4040         .sysc_fields    = &omap_hwmod_sysc_type1,
4041 };
4042
4043 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4044         .name   = "spinlock",
4045         .sysc   = &omap44xx_spinlock_sysc,
4046 };
4047
4048 /* spinlock */
4049 static struct omap_hwmod omap44xx_spinlock_hwmod;
4050 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4051         {
4052                 .pa_start       = 0x4a0f6000,
4053                 .pa_end         = 0x4a0f6fff,
4054                 .flags          = ADDR_TYPE_RT
4055         },
4056         { }
4057 };
4058
4059 /* l4_cfg -> spinlock */
4060 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4061         .master         = &omap44xx_l4_cfg_hwmod,
4062         .slave          = &omap44xx_spinlock_hwmod,
4063         .clk            = "l4_div_ck",
4064         .addr           = omap44xx_spinlock_addrs,
4065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4066 };
4067
4068 /* spinlock slave ports */
4069 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4070         &omap44xx_l4_cfg__spinlock,
4071 };
4072
4073 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4074         .name           = "spinlock",
4075         .class          = &omap44xx_spinlock_hwmod_class,
4076         .clkdm_name     = "l4_cfg_clkdm",
4077         .prcm = {
4078                 .omap4 = {
4079                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
4080                 },
4081         },
4082         .slaves         = omap44xx_spinlock_slaves,
4083         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
4084         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4085 };
4086
4087 /*
4088  * 'timer' class
4089  * general purpose timer module with accurate 1ms tick
4090  * This class contains several variants: ['timer_1ms', 'timer']
4091  */
4092
4093 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4094         .rev_offs       = 0x0000,
4095         .sysc_offs      = 0x0010,
4096         .syss_offs      = 0x0014,
4097         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4098                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4099                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4100                            SYSS_HAS_RESET_STATUS),
4101         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4102         .sysc_fields    = &omap_hwmod_sysc_type1,
4103 };
4104
4105 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4106         .name   = "timer",
4107         .sysc   = &omap44xx_timer_1ms_sysc,
4108 };
4109
4110 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4111         .rev_offs       = 0x0000,
4112         .sysc_offs      = 0x0010,
4113         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4114                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4115         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4116                            SIDLE_SMART_WKUP),
4117         .sysc_fields    = &omap_hwmod_sysc_type2,
4118 };
4119
4120 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4121         .name   = "timer",
4122         .sysc   = &omap44xx_timer_sysc,
4123 };
4124
4125 /* timer1 */
4126 static struct omap_hwmod omap44xx_timer1_hwmod;
4127 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4128         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4129         { .irq = -1 }
4130 };
4131
4132 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4133         {
4134                 .pa_start       = 0x4a318000,
4135                 .pa_end         = 0x4a31807f,
4136                 .flags          = ADDR_TYPE_RT
4137         },
4138         { }
4139 };
4140
4141 /* l4_wkup -> timer1 */
4142 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4143         .master         = &omap44xx_l4_wkup_hwmod,
4144         .slave          = &omap44xx_timer1_hwmod,
4145         .clk            = "l4_wkup_clk_mux_ck",
4146         .addr           = omap44xx_timer1_addrs,
4147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4148 };
4149
4150 /* timer1 slave ports */
4151 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4152         &omap44xx_l4_wkup__timer1,
4153 };
4154
4155 static struct omap_hwmod omap44xx_timer1_hwmod = {
4156         .name           = "timer1",
4157         .class          = &omap44xx_timer_1ms_hwmod_class,
4158         .clkdm_name     = "l4_wkup_clkdm",
4159         .mpu_irqs       = omap44xx_timer1_irqs,
4160         .main_clk       = "timer1_fck",
4161         .prcm = {
4162                 .omap4 = {
4163                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4164                 },
4165         },
4166         .slaves         = omap44xx_timer1_slaves,
4167         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4168         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4169 };
4170
4171 /* timer2 */
4172 static struct omap_hwmod omap44xx_timer2_hwmod;
4173 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4174         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4175         { .irq = -1 }
4176 };
4177
4178 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4179         {
4180                 .pa_start       = 0x48032000,
4181                 .pa_end         = 0x4803207f,
4182                 .flags          = ADDR_TYPE_RT
4183         },
4184         { }
4185 };
4186
4187 /* l4_per -> timer2 */
4188 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4189         .master         = &omap44xx_l4_per_hwmod,
4190         .slave          = &omap44xx_timer2_hwmod,
4191         .clk            = "l4_div_ck",
4192         .addr           = omap44xx_timer2_addrs,
4193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4194 };
4195
4196 /* timer2 slave ports */
4197 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4198         &omap44xx_l4_per__timer2,
4199 };
4200
4201 static struct omap_hwmod omap44xx_timer2_hwmod = {
4202         .name           = "timer2",
4203         .class          = &omap44xx_timer_1ms_hwmod_class,
4204         .clkdm_name     = "l4_per_clkdm",
4205         .mpu_irqs       = omap44xx_timer2_irqs,
4206         .main_clk       = "timer2_fck",
4207         .prcm = {
4208                 .omap4 = {
4209                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4210                 },
4211         },
4212         .slaves         = omap44xx_timer2_slaves,
4213         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4214         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4215 };
4216
4217 /* timer3 */
4218 static struct omap_hwmod omap44xx_timer3_hwmod;
4219 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4220         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4221         { .irq = -1 }
4222 };
4223
4224 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4225         {
4226                 .pa_start       = 0x48034000,
4227                 .pa_end         = 0x4803407f,
4228                 .flags          = ADDR_TYPE_RT
4229         },
4230         { }
4231 };
4232
4233 /* l4_per -> timer3 */
4234 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4235         .master         = &omap44xx_l4_per_hwmod,
4236         .slave          = &omap44xx_timer3_hwmod,
4237         .clk            = "l4_div_ck",
4238         .addr           = omap44xx_timer3_addrs,
4239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4240 };
4241
4242 /* timer3 slave ports */
4243 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4244         &omap44xx_l4_per__timer3,
4245 };
4246
4247 static struct omap_hwmod omap44xx_timer3_hwmod = {
4248         .name           = "timer3",
4249         .class          = &omap44xx_timer_hwmod_class,
4250         .clkdm_name     = "l4_per_clkdm",
4251         .mpu_irqs       = omap44xx_timer3_irqs,
4252         .main_clk       = "timer3_fck",
4253         .prcm = {
4254                 .omap4 = {
4255                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4256                 },
4257         },
4258         .slaves         = omap44xx_timer3_slaves,
4259         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4260         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4261 };
4262
4263 /* timer4 */
4264 static struct omap_hwmod omap44xx_timer4_hwmod;
4265 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4266         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4267         { .irq = -1 }
4268 };
4269
4270 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4271         {
4272                 .pa_start       = 0x48036000,
4273                 .pa_end         = 0x4803607f,
4274                 .flags          = ADDR_TYPE_RT
4275         },
4276         { }
4277 };
4278
4279 /* l4_per -> timer4 */
4280 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4281         .master         = &omap44xx_l4_per_hwmod,
4282         .slave          = &omap44xx_timer4_hwmod,
4283         .clk            = "l4_div_ck",
4284         .addr           = omap44xx_timer4_addrs,
4285         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4286 };
4287
4288 /* timer4 slave ports */
4289 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4290         &omap44xx_l4_per__timer4,
4291 };
4292
4293 static struct omap_hwmod omap44xx_timer4_hwmod = {
4294         .name           = "timer4",
4295         .class          = &omap44xx_timer_hwmod_class,
4296         .clkdm_name     = "l4_per_clkdm",
4297         .mpu_irqs       = omap44xx_timer4_irqs,
4298         .main_clk       = "timer4_fck",
4299         .prcm = {
4300                 .omap4 = {
4301                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4302                 },
4303         },
4304         .slaves         = omap44xx_timer4_slaves,
4305         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4306         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4307 };
4308
4309 /* timer5 */
4310 static struct omap_hwmod omap44xx_timer5_hwmod;
4311 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4312         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4313         { .irq = -1 }
4314 };
4315
4316 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4317         {
4318                 .pa_start       = 0x40138000,
4319                 .pa_end         = 0x4013807f,
4320                 .flags          = ADDR_TYPE_RT
4321         },
4322         { }
4323 };
4324
4325 /* l4_abe -> timer5 */
4326 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4327         .master         = &omap44xx_l4_abe_hwmod,
4328         .slave          = &omap44xx_timer5_hwmod,
4329         .clk            = "ocp_abe_iclk",
4330         .addr           = omap44xx_timer5_addrs,
4331         .user           = OCP_USER_MPU,
4332 };
4333
4334 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4335         {
4336                 .pa_start       = 0x49038000,
4337                 .pa_end         = 0x4903807f,
4338                 .flags          = ADDR_TYPE_RT
4339         },
4340         { }
4341 };
4342
4343 /* l4_abe -> timer5 (dma) */
4344 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4345         .master         = &omap44xx_l4_abe_hwmod,
4346         .slave          = &omap44xx_timer5_hwmod,
4347         .clk            = "ocp_abe_iclk",
4348         .addr           = omap44xx_timer5_dma_addrs,
4349         .user           = OCP_USER_SDMA,
4350 };
4351
4352 /* timer5 slave ports */
4353 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4354         &omap44xx_l4_abe__timer5,
4355         &omap44xx_l4_abe__timer5_dma,
4356 };
4357
4358 static struct omap_hwmod omap44xx_timer5_hwmod = {
4359         .name           = "timer5",
4360         .class          = &omap44xx_timer_hwmod_class,
4361         .clkdm_name     = "abe_clkdm",
4362         .mpu_irqs       = omap44xx_timer5_irqs,
4363         .main_clk       = "timer5_fck",
4364         .prcm = {
4365                 .omap4 = {
4366                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4367                 },
4368         },
4369         .slaves         = omap44xx_timer5_slaves,
4370         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4371         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4372 };
4373
4374 /* timer6 */
4375 static struct omap_hwmod omap44xx_timer6_hwmod;
4376 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4377         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4378         { .irq = -1 }
4379 };
4380
4381 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4382         {
4383                 .pa_start       = 0x4013a000,
4384                 .pa_end         = 0x4013a07f,
4385                 .flags          = ADDR_TYPE_RT
4386         },
4387         { }
4388 };
4389
4390 /* l4_abe -> timer6 */
4391 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4392         .master         = &omap44xx_l4_abe_hwmod,
4393         .slave          = &omap44xx_timer6_hwmod,
4394         .clk            = "ocp_abe_iclk",
4395         .addr           = omap44xx_timer6_addrs,
4396         .user           = OCP_USER_MPU,
4397 };
4398
4399 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4400         {
4401                 .pa_start       = 0x4903a000,
4402                 .pa_end         = 0x4903a07f,
4403                 .flags          = ADDR_TYPE_RT
4404         },
4405         { }
4406 };
4407
4408 /* l4_abe -> timer6 (dma) */
4409 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4410         .master         = &omap44xx_l4_abe_hwmod,
4411         .slave          = &omap44xx_timer6_hwmod,
4412         .clk            = "ocp_abe_iclk",
4413         .addr           = omap44xx_timer6_dma_addrs,
4414         .user           = OCP_USER_SDMA,
4415 };
4416
4417 /* timer6 slave ports */
4418 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4419         &omap44xx_l4_abe__timer6,
4420         &omap44xx_l4_abe__timer6_dma,
4421 };
4422
4423 static struct omap_hwmod omap44xx_timer6_hwmod = {
4424         .name           = "timer6",
4425         .class          = &omap44xx_timer_hwmod_class,
4426         .clkdm_name     = "abe_clkdm",
4427         .mpu_irqs       = omap44xx_timer6_irqs,
4428
4429         .main_clk       = "timer6_fck",
4430         .prcm = {
4431                 .omap4 = {
4432                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4433                 },
4434         },
4435         .slaves         = omap44xx_timer6_slaves,
4436         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4437         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4438 };
4439
4440 /* timer7 */
4441 static struct omap_hwmod omap44xx_timer7_hwmod;
4442 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4443         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4444         { .irq = -1 }
4445 };
4446
4447 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4448         {
4449                 .pa_start       = 0x4013c000,
4450                 .pa_end         = 0x4013c07f,
4451                 .flags          = ADDR_TYPE_RT
4452         },
4453         { }
4454 };
4455
4456 /* l4_abe -> timer7 */
4457 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4458         .master         = &omap44xx_l4_abe_hwmod,
4459         .slave          = &omap44xx_timer7_hwmod,
4460         .clk            = "ocp_abe_iclk",
4461         .addr           = omap44xx_timer7_addrs,
4462         .user           = OCP_USER_MPU,
4463 };
4464
4465 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4466         {
4467                 .pa_start       = 0x4903c000,
4468                 .pa_end         = 0x4903c07f,
4469                 .flags          = ADDR_TYPE_RT
4470         },
4471         { }
4472 };
4473
4474 /* l4_abe -> timer7 (dma) */
4475 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4476         .master         = &omap44xx_l4_abe_hwmod,
4477         .slave          = &omap44xx_timer7_hwmod,
4478         .clk            = "ocp_abe_iclk",
4479         .addr           = omap44xx_timer7_dma_addrs,
4480         .user           = OCP_USER_SDMA,
4481 };
4482
4483 /* timer7 slave ports */
4484 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4485         &omap44xx_l4_abe__timer7,
4486         &omap44xx_l4_abe__timer7_dma,
4487 };
4488
4489 static struct omap_hwmod omap44xx_timer7_hwmod = {
4490         .name           = "timer7",
4491         .class          = &omap44xx_timer_hwmod_class,
4492         .clkdm_name     = "abe_clkdm",
4493         .mpu_irqs       = omap44xx_timer7_irqs,
4494         .main_clk       = "timer7_fck",
4495         .prcm = {
4496                 .omap4 = {
4497                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4498                 },
4499         },
4500         .slaves         = omap44xx_timer7_slaves,
4501         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4502         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4503 };
4504
4505 /* timer8 */
4506 static struct omap_hwmod omap44xx_timer8_hwmod;
4507 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4508         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4509         { .irq = -1 }
4510 };
4511
4512 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4513         {
4514                 .pa_start       = 0x4013e000,
4515                 .pa_end         = 0x4013e07f,
4516                 .flags          = ADDR_TYPE_RT
4517         },
4518         { }
4519 };
4520
4521 /* l4_abe -> timer8 */
4522 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4523         .master         = &omap44xx_l4_abe_hwmod,
4524         .slave          = &omap44xx_timer8_hwmod,
4525         .clk            = "ocp_abe_iclk",
4526         .addr           = omap44xx_timer8_addrs,
4527         .user           = OCP_USER_MPU,
4528 };
4529
4530 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4531         {
4532                 .pa_start       = 0x4903e000,
4533                 .pa_end         = 0x4903e07f,
4534                 .flags          = ADDR_TYPE_RT
4535         },
4536         { }
4537 };
4538
4539 /* l4_abe -> timer8 (dma) */
4540 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4541         .master         = &omap44xx_l4_abe_hwmod,
4542         .slave          = &omap44xx_timer8_hwmod,
4543         .clk            = "ocp_abe_iclk",
4544         .addr           = omap44xx_timer8_dma_addrs,
4545         .user           = OCP_USER_SDMA,
4546 };
4547
4548 /* timer8 slave ports */
4549 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4550         &omap44xx_l4_abe__timer8,
4551         &omap44xx_l4_abe__timer8_dma,
4552 };
4553
4554 static struct omap_hwmod omap44xx_timer8_hwmod = {
4555         .name           = "timer8",
4556         .class          = &omap44xx_timer_hwmod_class,
4557         .clkdm_name     = "abe_clkdm",
4558         .mpu_irqs       = omap44xx_timer8_irqs,
4559         .main_clk       = "timer8_fck",
4560         .prcm = {
4561                 .omap4 = {
4562                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4563                 },
4564         },
4565         .slaves         = omap44xx_timer8_slaves,
4566         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4567         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4568 };
4569
4570 /* timer9 */
4571 static struct omap_hwmod omap44xx_timer9_hwmod;
4572 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4573         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4574         { .irq = -1 }
4575 };
4576
4577 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4578         {
4579                 .pa_start       = 0x4803e000,
4580                 .pa_end         = 0x4803e07f,
4581                 .flags          = ADDR_TYPE_RT
4582         },
4583         { }
4584 };
4585
4586 /* l4_per -> timer9 */
4587 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4588         .master         = &omap44xx_l4_per_hwmod,
4589         .slave          = &omap44xx_timer9_hwmod,
4590         .clk            = "l4_div_ck",
4591         .addr           = omap44xx_timer9_addrs,
4592         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4593 };
4594
4595 /* timer9 slave ports */
4596 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4597         &omap44xx_l4_per__timer9,
4598 };
4599
4600 static struct omap_hwmod omap44xx_timer9_hwmod = {
4601         .name           = "timer9",
4602         .class          = &omap44xx_timer_hwmod_class,
4603         .clkdm_name     = "l4_per_clkdm",
4604         .mpu_irqs       = omap44xx_timer9_irqs,
4605         .main_clk       = "timer9_fck",
4606         .prcm = {
4607                 .omap4 = {
4608                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4609                 },
4610         },
4611         .slaves         = omap44xx_timer9_slaves,
4612         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4613         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4614 };
4615
4616 /* timer10 */
4617 static struct omap_hwmod omap44xx_timer10_hwmod;
4618 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4619         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4620         { .irq = -1 }
4621 };
4622
4623 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4624         {
4625                 .pa_start       = 0x48086000,
4626                 .pa_end         = 0x4808607f,
4627                 .flags          = ADDR_TYPE_RT
4628         },
4629         { }
4630 };
4631
4632 /* l4_per -> timer10 */
4633 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4634         .master         = &omap44xx_l4_per_hwmod,
4635         .slave          = &omap44xx_timer10_hwmod,
4636         .clk            = "l4_div_ck",
4637         .addr           = omap44xx_timer10_addrs,
4638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4639 };
4640
4641 /* timer10 slave ports */
4642 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4643         &omap44xx_l4_per__timer10,
4644 };
4645
4646 static struct omap_hwmod omap44xx_timer10_hwmod = {
4647         .name           = "timer10",
4648         .class          = &omap44xx_timer_1ms_hwmod_class,
4649         .clkdm_name     = "l4_per_clkdm",
4650         .mpu_irqs       = omap44xx_timer10_irqs,
4651         .main_clk       = "timer10_fck",
4652         .prcm = {
4653                 .omap4 = {
4654                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4655                 },
4656         },
4657         .slaves         = omap44xx_timer10_slaves,
4658         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4660 };
4661
4662 /* timer11 */
4663 static struct omap_hwmod omap44xx_timer11_hwmod;
4664 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4665         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4666         { .irq = -1 }
4667 };
4668
4669 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4670         {
4671                 .pa_start       = 0x48088000,
4672                 .pa_end         = 0x4808807f,
4673                 .flags          = ADDR_TYPE_RT
4674         },
4675         { }
4676 };
4677
4678 /* l4_per -> timer11 */
4679 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4680         .master         = &omap44xx_l4_per_hwmod,
4681         .slave          = &omap44xx_timer11_hwmod,
4682         .clk            = "l4_div_ck",
4683         .addr           = omap44xx_timer11_addrs,
4684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4685 };
4686
4687 /* timer11 slave ports */
4688 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4689         &omap44xx_l4_per__timer11,
4690 };
4691
4692 static struct omap_hwmod omap44xx_timer11_hwmod = {
4693         .name           = "timer11",
4694         .class          = &omap44xx_timer_hwmod_class,
4695         .clkdm_name     = "l4_per_clkdm",
4696         .mpu_irqs       = omap44xx_timer11_irqs,
4697         .main_clk       = "timer11_fck",
4698         .prcm = {
4699                 .omap4 = {
4700                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4701                 },
4702         },
4703         .slaves         = omap44xx_timer11_slaves,
4704         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4705         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4706 };
4707
4708 /*
4709  * 'uart' class
4710  * universal asynchronous receiver/transmitter (uart)
4711  */
4712
4713 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4714         .rev_offs       = 0x0050,
4715         .sysc_offs      = 0x0054,
4716         .syss_offs      = 0x0058,
4717         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4718                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4719                            SYSS_HAS_RESET_STATUS),
4720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4721                            SIDLE_SMART_WKUP),
4722         .sysc_fields    = &omap_hwmod_sysc_type1,
4723 };
4724
4725 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4726         .name   = "uart",
4727         .sysc   = &omap44xx_uart_sysc,
4728 };
4729
4730 /* uart1 */
4731 static struct omap_hwmod omap44xx_uart1_hwmod;
4732 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4733         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4734         { .irq = -1 }
4735 };
4736
4737 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4738         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4739         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4740         { .dma_req = -1 }
4741 };
4742
4743 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4744         {
4745                 .pa_start       = 0x4806a000,
4746                 .pa_end         = 0x4806a0ff,
4747                 .flags          = ADDR_TYPE_RT
4748         },
4749         { }
4750 };
4751
4752 /* l4_per -> uart1 */
4753 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4754         .master         = &omap44xx_l4_per_hwmod,
4755         .slave          = &omap44xx_uart1_hwmod,
4756         .clk            = "l4_div_ck",
4757         .addr           = omap44xx_uart1_addrs,
4758         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4759 };
4760
4761 /* uart1 slave ports */
4762 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4763         &omap44xx_l4_per__uart1,
4764 };
4765
4766 static struct omap_hwmod omap44xx_uart1_hwmod = {
4767         .name           = "uart1",
4768         .class          = &omap44xx_uart_hwmod_class,
4769         .clkdm_name     = "l4_per_clkdm",
4770         .mpu_irqs       = omap44xx_uart1_irqs,
4771         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4772         .main_clk       = "uart1_fck",
4773         .prcm = {
4774                 .omap4 = {
4775                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4776                 },
4777         },
4778         .slaves         = omap44xx_uart1_slaves,
4779         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4780         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4781 };
4782
4783 /* uart2 */
4784 static struct omap_hwmod omap44xx_uart2_hwmod;
4785 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4786         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4787         { .irq = -1 }
4788 };
4789
4790 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4791         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4792         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4793         { .dma_req = -1 }
4794 };
4795
4796 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4797         {
4798                 .pa_start       = 0x4806c000,
4799                 .pa_end         = 0x4806c0ff,
4800                 .flags          = ADDR_TYPE_RT
4801         },
4802         { }
4803 };
4804
4805 /* l4_per -> uart2 */
4806 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4807         .master         = &omap44xx_l4_per_hwmod,
4808         .slave          = &omap44xx_uart2_hwmod,
4809         .clk            = "l4_div_ck",
4810         .addr           = omap44xx_uart2_addrs,
4811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4812 };
4813
4814 /* uart2 slave ports */
4815 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4816         &omap44xx_l4_per__uart2,
4817 };
4818
4819 static struct omap_hwmod omap44xx_uart2_hwmod = {
4820         .name           = "uart2",
4821         .class          = &omap44xx_uart_hwmod_class,
4822         .clkdm_name     = "l4_per_clkdm",
4823         .mpu_irqs       = omap44xx_uart2_irqs,
4824         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4825         .main_clk       = "uart2_fck",
4826         .prcm = {
4827                 .omap4 = {
4828                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4829                 },
4830         },
4831         .slaves         = omap44xx_uart2_slaves,
4832         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4833         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4834 };
4835
4836 /* uart3 */
4837 static struct omap_hwmod omap44xx_uart3_hwmod;
4838 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4839         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4840         { .irq = -1 }
4841 };
4842
4843 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4844         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4845         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4846         { .dma_req = -1 }
4847 };
4848
4849 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4850         {
4851                 .pa_start       = 0x48020000,
4852                 .pa_end         = 0x480200ff,
4853                 .flags          = ADDR_TYPE_RT
4854         },
4855         { }
4856 };
4857
4858 /* l4_per -> uart3 */
4859 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4860         .master         = &omap44xx_l4_per_hwmod,
4861         .slave          = &omap44xx_uart3_hwmod,
4862         .clk            = "l4_div_ck",
4863         .addr           = omap44xx_uart3_addrs,
4864         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4865 };
4866
4867 /* uart3 slave ports */
4868 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4869         &omap44xx_l4_per__uart3,
4870 };
4871
4872 static struct omap_hwmod omap44xx_uart3_hwmod = {
4873         .name           = "uart3",
4874         .class          = &omap44xx_uart_hwmod_class,
4875         .clkdm_name     = "l4_per_clkdm",
4876         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4877         .mpu_irqs       = omap44xx_uart3_irqs,
4878         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4879         .main_clk       = "uart3_fck",
4880         .prcm = {
4881                 .omap4 = {
4882                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4883                 },
4884         },
4885         .slaves         = omap44xx_uart3_slaves,
4886         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4887         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4888 };
4889
4890 /* uart4 */
4891 static struct omap_hwmod omap44xx_uart4_hwmod;
4892 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4893         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4894         { .irq = -1 }
4895 };
4896
4897 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4898         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4899         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4900         { .dma_req = -1 }
4901 };
4902
4903 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4904         {
4905                 .pa_start       = 0x4806e000,
4906                 .pa_end         = 0x4806e0ff,
4907                 .flags          = ADDR_TYPE_RT
4908         },
4909         { }
4910 };
4911
4912 /* l4_per -> uart4 */
4913 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4914         .master         = &omap44xx_l4_per_hwmod,
4915         .slave          = &omap44xx_uart4_hwmod,
4916         .clk            = "l4_div_ck",
4917         .addr           = omap44xx_uart4_addrs,
4918         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4919 };
4920
4921 /* uart4 slave ports */
4922 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4923         &omap44xx_l4_per__uart4,
4924 };
4925
4926 static struct omap_hwmod omap44xx_uart4_hwmod = {
4927         .name           = "uart4",
4928         .class          = &omap44xx_uart_hwmod_class,
4929         .clkdm_name     = "l4_per_clkdm",
4930         .mpu_irqs       = omap44xx_uart4_irqs,
4931         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4932         .main_clk       = "uart4_fck",
4933         .prcm = {
4934                 .omap4 = {
4935                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4936                 },
4937         },
4938         .slaves         = omap44xx_uart4_slaves,
4939         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
4940         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4941 };
4942
4943 /*
4944  * 'usb_otg_hs' class
4945  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4946  */
4947
4948 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4949         .rev_offs       = 0x0400,
4950         .sysc_offs      = 0x0404,
4951         .syss_offs      = 0x0408,
4952         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4953                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4954                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4955         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4956                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4957                            MSTANDBY_SMART),
4958         .sysc_fields    = &omap_hwmod_sysc_type1,
4959 };
4960
4961 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4962         .name   = "usb_otg_hs",
4963         .sysc   = &omap44xx_usb_otg_hs_sysc,
4964 };
4965
4966 /* usb_otg_hs */
4967 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4968         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4969         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4970         { .irq = -1 }
4971 };
4972
4973 /* usb_otg_hs master ports */
4974 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4975         &omap44xx_usb_otg_hs__l3_main_2,
4976 };
4977
4978 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4979         {
4980                 .pa_start       = 0x4a0ab000,
4981                 .pa_end         = 0x4a0ab003,
4982                 .flags          = ADDR_TYPE_RT
4983         },
4984         { }
4985 };
4986
4987 /* l4_cfg -> usb_otg_hs */
4988 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4989         .master         = &omap44xx_l4_cfg_hwmod,
4990         .slave          = &omap44xx_usb_otg_hs_hwmod,
4991         .clk            = "l4_div_ck",
4992         .addr           = omap44xx_usb_otg_hs_addrs,
4993         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4994 };
4995
4996 /* usb_otg_hs slave ports */
4997 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4998         &omap44xx_l4_cfg__usb_otg_hs,
4999 };
5000
5001 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5002         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5003 };
5004
5005 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5006         .name           = "usb_otg_hs",
5007         .class          = &omap44xx_usb_otg_hs_hwmod_class,
5008         .clkdm_name     = "l3_init_clkdm",
5009         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5010         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
5011         .main_clk       = "usb_otg_hs_ick",
5012         .prcm = {
5013                 .omap4 = {
5014                         .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
5015                 },
5016         },
5017         .opt_clks       = usb_otg_hs_opt_clks,
5018         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
5019         .slaves         = omap44xx_usb_otg_hs_slaves,
5020         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5021         .masters        = omap44xx_usb_otg_hs_masters,
5022         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5023         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5024 };
5025
5026 /*
5027  * 'wd_timer' class
5028  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5029  * overflow condition
5030  */
5031
5032 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5033         .rev_offs       = 0x0000,
5034         .sysc_offs      = 0x0010,
5035         .syss_offs      = 0x0014,
5036         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5037                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5038         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5039                            SIDLE_SMART_WKUP),
5040         .sysc_fields    = &omap_hwmod_sysc_type1,
5041 };
5042
5043 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5044         .name           = "wd_timer",
5045         .sysc           = &omap44xx_wd_timer_sysc,
5046         .pre_shutdown   = &omap2_wd_timer_disable,
5047 };
5048
5049 /* wd_timer2 */
5050 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5051 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5052         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5053         { .irq = -1 }
5054 };
5055
5056 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5057         {
5058                 .pa_start       = 0x4a314000,
5059                 .pa_end         = 0x4a31407f,
5060                 .flags          = ADDR_TYPE_RT
5061         },
5062         { }
5063 };
5064
5065 /* l4_wkup -> wd_timer2 */
5066 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5067         .master         = &omap44xx_l4_wkup_hwmod,
5068         .slave          = &omap44xx_wd_timer2_hwmod,
5069         .clk            = "l4_wkup_clk_mux_ck",
5070         .addr           = omap44xx_wd_timer2_addrs,
5071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5072 };
5073
5074 /* wd_timer2 slave ports */
5075 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5076         &omap44xx_l4_wkup__wd_timer2,
5077 };
5078
5079 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5080         .name           = "wd_timer2",
5081         .class          = &omap44xx_wd_timer_hwmod_class,
5082         .clkdm_name     = "l4_wkup_clkdm",
5083         .mpu_irqs       = omap44xx_wd_timer2_irqs,
5084         .main_clk       = "wd_timer2_fck",
5085         .prcm = {
5086                 .omap4 = {
5087                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
5088                 },
5089         },
5090         .slaves         = omap44xx_wd_timer2_slaves,
5091         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5092         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5093 };
5094
5095 /* wd_timer3 */
5096 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5097 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5098         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5099         { .irq = -1 }
5100 };
5101
5102 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5103         {
5104                 .pa_start       = 0x40130000,
5105                 .pa_end         = 0x4013007f,
5106                 .flags          = ADDR_TYPE_RT
5107         },
5108         { }
5109 };
5110
5111 /* l4_abe -> wd_timer3 */
5112 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5113         .master         = &omap44xx_l4_abe_hwmod,
5114         .slave          = &omap44xx_wd_timer3_hwmod,
5115         .clk            = "ocp_abe_iclk",
5116         .addr           = omap44xx_wd_timer3_addrs,
5117         .user           = OCP_USER_MPU,
5118 };
5119
5120 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5121         {
5122                 .pa_start       = 0x49030000,
5123                 .pa_end         = 0x4903007f,
5124                 .flags          = ADDR_TYPE_RT
5125         },
5126         { }
5127 };
5128
5129 /* l4_abe -> wd_timer3 (dma) */
5130 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5131         .master         = &omap44xx_l4_abe_hwmod,
5132         .slave          = &omap44xx_wd_timer3_hwmod,
5133         .clk            = "ocp_abe_iclk",
5134         .addr           = omap44xx_wd_timer3_dma_addrs,
5135         .user           = OCP_USER_SDMA,
5136 };
5137
5138 /* wd_timer3 slave ports */
5139 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5140         &omap44xx_l4_abe__wd_timer3,
5141         &omap44xx_l4_abe__wd_timer3_dma,
5142 };
5143
5144 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5145         .name           = "wd_timer3",
5146         .class          = &omap44xx_wd_timer_hwmod_class,
5147         .clkdm_name     = "abe_clkdm",
5148         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5149         .main_clk       = "wd_timer3_fck",
5150         .prcm = {
5151                 .omap4 = {
5152                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
5153                 },
5154         },
5155         .slaves         = omap44xx_wd_timer3_slaves,
5156         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5157         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5158 };
5159
5160 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5161
5162         /* dmm class */
5163         &omap44xx_dmm_hwmod,
5164
5165         /* emif_fw class */
5166         &omap44xx_emif_fw_hwmod,
5167
5168         /* l3 class */
5169         &omap44xx_l3_instr_hwmod,
5170         &omap44xx_l3_main_1_hwmod,
5171         &omap44xx_l3_main_2_hwmod,
5172         &omap44xx_l3_main_3_hwmod,
5173
5174         /* l4 class */
5175         &omap44xx_l4_abe_hwmod,
5176         &omap44xx_l4_cfg_hwmod,
5177         &omap44xx_l4_per_hwmod,
5178         &omap44xx_l4_wkup_hwmod,
5179
5180         /* mpu_bus class */
5181         &omap44xx_mpu_private_hwmod,
5182
5183         /* aess class */
5184 /*      &omap44xx_aess_hwmod, */
5185
5186         /* bandgap class */
5187         &omap44xx_bandgap_hwmod,
5188
5189         /* counter class */
5190 /*      &omap44xx_counter_32k_hwmod, */
5191
5192         /* dma class */
5193         &omap44xx_dma_system_hwmod,
5194
5195         /* dmic class */
5196         &omap44xx_dmic_hwmod,
5197
5198         /* dsp class */
5199         &omap44xx_dsp_hwmod,
5200         &omap44xx_dsp_c0_hwmod,
5201
5202         /* dss class */
5203         &omap44xx_dss_hwmod,
5204         &omap44xx_dss_dispc_hwmod,
5205         &omap44xx_dss_dsi1_hwmod,
5206         &omap44xx_dss_dsi2_hwmod,
5207         &omap44xx_dss_hdmi_hwmod,
5208         &omap44xx_dss_rfbi_hwmod,
5209         &omap44xx_dss_venc_hwmod,
5210
5211         /* gpio class */
5212         &omap44xx_gpio1_hwmod,
5213         &omap44xx_gpio2_hwmod,
5214         &omap44xx_gpio3_hwmod,
5215         &omap44xx_gpio4_hwmod,
5216         &omap44xx_gpio5_hwmod,
5217         &omap44xx_gpio6_hwmod,
5218
5219         /* hsi class */
5220 /*      &omap44xx_hsi_hwmod, */
5221
5222         /* i2c class */
5223         &omap44xx_i2c1_hwmod,
5224         &omap44xx_i2c2_hwmod,
5225         &omap44xx_i2c3_hwmod,
5226         &omap44xx_i2c4_hwmod,
5227
5228         /* ipu class */
5229         &omap44xx_ipu_hwmod,
5230         &omap44xx_ipu_c0_hwmod,
5231         &omap44xx_ipu_c1_hwmod,
5232
5233         /* iss class */
5234 /*      &omap44xx_iss_hwmod, */
5235
5236         /* iva class */
5237         &omap44xx_iva_hwmod,
5238         &omap44xx_iva_seq0_hwmod,
5239         &omap44xx_iva_seq1_hwmod,
5240
5241         /* kbd class */
5242         &omap44xx_kbd_hwmod,
5243
5244         /* mailbox class */
5245         &omap44xx_mailbox_hwmod,
5246
5247         /* mcbsp class */
5248         &omap44xx_mcbsp1_hwmod,
5249         &omap44xx_mcbsp2_hwmod,
5250         &omap44xx_mcbsp3_hwmod,
5251         &omap44xx_mcbsp4_hwmod,
5252
5253         /* mcpdm class */
5254 /*      &omap44xx_mcpdm_hwmod, */
5255
5256         /* mcspi class */
5257         &omap44xx_mcspi1_hwmod,
5258         &omap44xx_mcspi2_hwmod,
5259         &omap44xx_mcspi3_hwmod,
5260         &omap44xx_mcspi4_hwmod,
5261
5262         /* mmc class */
5263         &omap44xx_mmc1_hwmod,
5264         &omap44xx_mmc2_hwmod,
5265         &omap44xx_mmc3_hwmod,
5266         &omap44xx_mmc4_hwmod,
5267         &omap44xx_mmc5_hwmod,
5268
5269         /* mpu class */
5270         &omap44xx_mpu_hwmod,
5271
5272         /* smartreflex class */
5273         &omap44xx_smartreflex_core_hwmod,
5274         &omap44xx_smartreflex_iva_hwmod,
5275         &omap44xx_smartreflex_mpu_hwmod,
5276
5277         /* spinlock class */
5278         &omap44xx_spinlock_hwmod,
5279
5280         /* timer class */
5281         &omap44xx_timer1_hwmod,
5282         &omap44xx_timer2_hwmod,
5283         &omap44xx_timer3_hwmod,
5284         &omap44xx_timer4_hwmod,
5285         &omap44xx_timer5_hwmod,
5286         &omap44xx_timer6_hwmod,
5287         &omap44xx_timer7_hwmod,
5288         &omap44xx_timer8_hwmod,
5289         &omap44xx_timer9_hwmod,
5290         &omap44xx_timer10_hwmod,
5291         &omap44xx_timer11_hwmod,
5292
5293         /* uart class */
5294         &omap44xx_uart1_hwmod,
5295         &omap44xx_uart2_hwmod,
5296         &omap44xx_uart3_hwmod,
5297         &omap44xx_uart4_hwmod,
5298
5299         /* usb_otg_hs class */
5300         &omap44xx_usb_otg_hs_hwmod,
5301
5302         /* wd_timer class */
5303         &omap44xx_wd_timer2_hwmod,
5304         &omap44xx_wd_timer3_hwmod,
5305
5306         NULL,
5307 };
5308
5309 int __init omap44xx_hwmod_init(void)
5310 {
5311         return omap_hwmod_register(omap44xx_hwmods);
5312 }
5313