2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
25 #include <plat/omap_hwmod.h>
28 #include <linux/platform_data/spi-omap2-mcspi.h>
29 #include <linux/platform_data/asoc-ti-mcbsp.h>
31 #include <plat/dmtimer.h>
32 #include <plat/common.h>
33 #include <plat/iommu.h>
35 #include "omap_hwmod_common_data.h"
39 #include "prm-regbits-44xx.h"
42 /* Base offset for all OMAP4 interrupts external to MPUSS */
43 #define OMAP44XX_IRQ_GIC_START 32
45 /* Base offset for all OMAP4 dma requests */
46 #define OMAP44XX_DMA_REQ_START 1
53 * 'c2c_target_fw' class
54 * instance(s): c2c_target_fw
56 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
57 .name = "c2c_target_fw",
61 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
62 .name = "c2c_target_fw",
63 .class = &omap44xx_c2c_target_fw_hwmod_class,
64 .clkdm_name = "d2d_clkdm",
67 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
68 .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
77 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
82 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
83 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
87 static struct omap_hwmod omap44xx_dmm_hwmod = {
89 .class = &omap44xx_dmm_hwmod_class,
90 .clkdm_name = "l3_emif_clkdm",
91 .mpu_irqs = omap44xx_dmm_irqs,
94 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
95 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
102 * instance(s): emif_fw
104 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
109 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
111 .class = &omap44xx_emif_fw_hwmod_class,
112 .clkdm_name = "l3_emif_clkdm",
115 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
116 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
123 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
125 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
130 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
132 .class = &omap44xx_l3_hwmod_class,
133 .clkdm_name = "l3_instr_clkdm",
136 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
137 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
138 .modulemode = MODULEMODE_HWCTRL,
144 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
145 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
146 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
150 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
152 .class = &omap44xx_l3_hwmod_class,
153 .clkdm_name = "l3_1_clkdm",
154 .mpu_irqs = omap44xx_l3_main_1_irqs,
157 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
158 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
164 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
166 .class = &omap44xx_l3_hwmod_class,
167 .clkdm_name = "l3_2_clkdm",
170 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
171 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
177 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
179 .class = &omap44xx_l3_hwmod_class,
180 .clkdm_name = "l3_instr_clkdm",
183 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
184 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
185 .modulemode = MODULEMODE_HWCTRL,
192 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
194 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
199 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
201 .class = &omap44xx_l4_hwmod_class,
202 .clkdm_name = "abe_clkdm",
205 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
206 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
207 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
208 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
214 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
216 .class = &omap44xx_l4_hwmod_class,
217 .clkdm_name = "l4_cfg_clkdm",
220 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
221 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
227 static struct omap_hwmod omap44xx_l4_per_hwmod = {
229 .class = &omap44xx_l4_hwmod_class,
230 .clkdm_name = "l4_per_clkdm",
233 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
234 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
240 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
242 .class = &omap44xx_l4_hwmod_class,
243 .clkdm_name = "l4_wkup_clkdm",
246 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
247 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
254 * instance(s): mpu_private
256 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
261 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
262 .name = "mpu_private",
263 .class = &omap44xx_mpu_bus_hwmod_class,
264 .clkdm_name = "mpuss_clkdm",
267 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
274 * instance(s): ocp_wp_noc
276 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
277 .name = "ocp_wp_noc",
281 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
282 .name = "ocp_wp_noc",
283 .class = &omap44xx_ocp_wp_noc_hwmod_class,
284 .clkdm_name = "l3_instr_clkdm",
287 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
288 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
289 .modulemode = MODULEMODE_HWCTRL,
295 * Modules omap_hwmod structures
297 * The following IPs are excluded for the moment because:
298 * - They do not need an explicit SW control using omap_hwmod API.
299 * - They still need to be validated with the driver
300 * properly adapted to omap_hwmod / omap_device
307 * audio engine sub system
310 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
313 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
314 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
315 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
316 MSTANDBY_SMART_WKUP),
317 .sysc_fields = &omap_hwmod_sysc_type2,
320 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
322 .sysc = &omap44xx_aess_sysc,
326 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
327 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
331 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
332 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
333 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
334 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
335 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
336 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
337 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
338 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
339 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
343 static struct omap_hwmod omap44xx_aess_hwmod = {
345 .class = &omap44xx_aess_hwmod_class,
346 .clkdm_name = "abe_clkdm",
347 .mpu_irqs = omap44xx_aess_irqs,
348 .sdma_reqs = omap44xx_aess_sdma_reqs,
349 .main_clk = "aess_fck",
352 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
353 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
354 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
355 .modulemode = MODULEMODE_SWCTRL,
362 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
366 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
371 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
372 { .irq = 88 + OMAP44XX_IRQ_GIC_START },
376 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
377 { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
381 static struct omap_hwmod omap44xx_c2c_hwmod = {
383 .class = &omap44xx_c2c_hwmod_class,
384 .clkdm_name = "d2d_clkdm",
385 .mpu_irqs = omap44xx_c2c_irqs,
386 .sdma_reqs = omap44xx_c2c_sdma_reqs,
389 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
390 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
397 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
400 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
403 .sysc_flags = SYSC_HAS_SIDLEMODE,
404 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
405 .sysc_fields = &omap_hwmod_sysc_type1,
408 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
410 .sysc = &omap44xx_counter_sysc,
414 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
415 .name = "counter_32k",
416 .class = &omap44xx_counter_hwmod_class,
417 .clkdm_name = "l4_wkup_clkdm",
418 .flags = HWMOD_SWSUP_SIDLE,
419 .main_clk = "sys_32k_ck",
422 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
423 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
429 * 'ctrl_module' class
430 * attila core control module + core pad control module + wkup pad control
431 * module + attila wkup control module
434 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
437 .sysc_flags = SYSC_HAS_SIDLEMODE,
438 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
440 .sysc_fields = &omap_hwmod_sysc_type2,
443 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
444 .name = "ctrl_module",
445 .sysc = &omap44xx_ctrl_module_sysc,
448 /* ctrl_module_core */
449 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
450 { .irq = 8 + OMAP44XX_IRQ_GIC_START },
454 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
455 .name = "ctrl_module_core",
456 .class = &omap44xx_ctrl_module_hwmod_class,
457 .clkdm_name = "l4_cfg_clkdm",
458 .mpu_irqs = omap44xx_ctrl_module_core_irqs,
461 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
466 /* ctrl_module_pad_core */
467 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
468 .name = "ctrl_module_pad_core",
469 .class = &omap44xx_ctrl_module_hwmod_class,
470 .clkdm_name = "l4_cfg_clkdm",
473 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
478 /* ctrl_module_wkup */
479 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
480 .name = "ctrl_module_wkup",
481 .class = &omap44xx_ctrl_module_hwmod_class,
482 .clkdm_name = "l4_wkup_clkdm",
485 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
490 /* ctrl_module_pad_wkup */
491 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
492 .name = "ctrl_module_pad_wkup",
493 .class = &omap44xx_ctrl_module_hwmod_class,
494 .clkdm_name = "l4_wkup_clkdm",
497 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
504 * debug and emulation sub system
507 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
512 static struct omap_hwmod omap44xx_debugss_hwmod = {
514 .class = &omap44xx_debugss_hwmod_class,
515 .clkdm_name = "emu_sys_clkdm",
516 .main_clk = "trace_clk_div_ck",
519 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
520 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
527 * dma controller for data exchange between memory to memory (i.e. internal or
528 * external memory) and gp peripherals to memory or memory to gp peripherals
531 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
535 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
536 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
537 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
538 SYSS_HAS_RESET_STATUS),
539 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
540 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
541 .sysc_fields = &omap_hwmod_sysc_type1,
544 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
546 .sysc = &omap44xx_dma_sysc,
550 static struct omap_dma_dev_attr dma_dev_attr = {
551 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
552 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
557 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
558 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
559 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
560 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
561 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
565 static struct omap_hwmod omap44xx_dma_system_hwmod = {
566 .name = "dma_system",
567 .class = &omap44xx_dma_hwmod_class,
568 .clkdm_name = "l3_dma_clkdm",
569 .mpu_irqs = omap44xx_dma_system_irqs,
570 .main_clk = "l3_div_ck",
573 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
574 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
577 .dev_attr = &dma_dev_attr,
582 * digital microphone controller
585 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
588 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
589 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
590 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
592 .sysc_fields = &omap_hwmod_sysc_type2,
595 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
597 .sysc = &omap44xx_dmic_sysc,
601 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
602 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
606 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
607 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
611 static struct omap_hwmod omap44xx_dmic_hwmod = {
613 .class = &omap44xx_dmic_hwmod_class,
614 .clkdm_name = "abe_clkdm",
615 .mpu_irqs = omap44xx_dmic_irqs,
616 .sdma_reqs = omap44xx_dmic_sdma_reqs,
617 .main_clk = "dmic_fck",
620 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
621 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
622 .modulemode = MODULEMODE_SWCTRL,
632 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
637 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
638 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
642 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
643 { .name = "dsp", .rst_shift = 0 },
646 static struct omap_hwmod omap44xx_dsp_hwmod = {
648 .class = &omap44xx_dsp_hwmod_class,
649 .clkdm_name = "tesla_clkdm",
650 .mpu_irqs = omap44xx_dsp_irqs,
651 .rst_lines = omap44xx_dsp_resets,
652 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
653 .main_clk = "dsp_fck",
656 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
657 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
658 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
659 .modulemode = MODULEMODE_HWCTRL,
669 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
672 .sysc_flags = SYSS_HAS_RESET_STATUS,
675 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
677 .sysc = &omap44xx_dss_sysc,
678 .reset = omap_dss_reset,
682 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
683 { .role = "sys_clk", .clk = "dss_sys_clk" },
684 { .role = "tv_clk", .clk = "dss_tv_clk" },
685 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
688 static struct omap_hwmod omap44xx_dss_hwmod = {
690 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
691 .class = &omap44xx_dss_hwmod_class,
692 .clkdm_name = "l3_dss_clkdm",
693 .main_clk = "dss_dss_clk",
696 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
697 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
700 .opt_clks = dss_opt_clks,
701 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
709 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
713 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
714 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
715 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
716 SYSS_HAS_RESET_STATUS),
717 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
718 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
719 .sysc_fields = &omap_hwmod_sysc_type1,
722 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
724 .sysc = &omap44xx_dispc_sysc,
728 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
729 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
733 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
734 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
738 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
740 .has_framedonetv_irq = 1
743 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
745 .class = &omap44xx_dispc_hwmod_class,
746 .clkdm_name = "l3_dss_clkdm",
747 .mpu_irqs = omap44xx_dss_dispc_irqs,
748 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
749 .main_clk = "dss_dss_clk",
752 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
753 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
756 .dev_attr = &omap44xx_dss_dispc_dev_attr
761 * display serial interface controller
764 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
768 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
769 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
770 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
771 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
772 .sysc_fields = &omap_hwmod_sysc_type1,
775 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
777 .sysc = &omap44xx_dsi_sysc,
781 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
782 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
786 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
787 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
791 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
792 { .role = "sys_clk", .clk = "dss_sys_clk" },
795 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
797 .class = &omap44xx_dsi_hwmod_class,
798 .clkdm_name = "l3_dss_clkdm",
799 .mpu_irqs = omap44xx_dss_dsi1_irqs,
800 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
801 .main_clk = "dss_dss_clk",
804 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
805 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
808 .opt_clks = dss_dsi1_opt_clks,
809 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
813 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
814 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
818 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
819 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
823 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
824 { .role = "sys_clk", .clk = "dss_sys_clk" },
827 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
829 .class = &omap44xx_dsi_hwmod_class,
830 .clkdm_name = "l3_dss_clkdm",
831 .mpu_irqs = omap44xx_dss_dsi2_irqs,
832 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
833 .main_clk = "dss_dss_clk",
836 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
837 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
840 .opt_clks = dss_dsi2_opt_clks,
841 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
849 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
852 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
854 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
856 .sysc_fields = &omap_hwmod_sysc_type2,
859 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
861 .sysc = &omap44xx_hdmi_sysc,
865 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
866 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
870 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
871 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
875 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
876 { .role = "sys_clk", .clk = "dss_sys_clk" },
879 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
881 .class = &omap44xx_hdmi_hwmod_class,
882 .clkdm_name = "l3_dss_clkdm",
884 * HDMI audio requires to use no-idle mode. Hence,
885 * set idle mode by software.
887 .flags = HWMOD_SWSUP_SIDLE,
888 .mpu_irqs = omap44xx_dss_hdmi_irqs,
889 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
890 .main_clk = "dss_48mhz_clk",
893 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
894 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
897 .opt_clks = dss_hdmi_opt_clks,
898 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
903 * remote frame buffer interface
906 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
910 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
911 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
912 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
913 .sysc_fields = &omap_hwmod_sysc_type1,
916 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
918 .sysc = &omap44xx_rfbi_sysc,
922 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
923 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
927 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
928 { .role = "ick", .clk = "dss_fck" },
931 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
933 .class = &omap44xx_rfbi_hwmod_class,
934 .clkdm_name = "l3_dss_clkdm",
935 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
936 .main_clk = "dss_dss_clk",
939 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
940 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
943 .opt_clks = dss_rfbi_opt_clks,
944 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
952 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
957 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
959 .class = &omap44xx_venc_hwmod_class,
960 .clkdm_name = "l3_dss_clkdm",
961 .main_clk = "dss_tv_clk",
964 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
965 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
972 * bch error location module
975 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
979 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
980 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
981 SYSS_HAS_RESET_STATUS),
982 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
983 .sysc_fields = &omap_hwmod_sysc_type1,
986 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
988 .sysc = &omap44xx_elm_sysc,
992 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
993 { .irq = 4 + OMAP44XX_IRQ_GIC_START },
997 static struct omap_hwmod omap44xx_elm_hwmod = {
999 .class = &omap44xx_elm_hwmod_class,
1000 .clkdm_name = "l4_per_clkdm",
1001 .mpu_irqs = omap44xx_elm_irqs,
1004 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1005 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1012 * external memory interface no1
1015 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1019 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1021 .sysc = &omap44xx_emif_sysc,
1025 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1026 { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1030 static struct omap_hwmod omap44xx_emif1_hwmod = {
1032 .class = &omap44xx_emif_hwmod_class,
1033 .clkdm_name = "l3_emif_clkdm",
1034 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1035 .mpu_irqs = omap44xx_emif1_irqs,
1036 .main_clk = "ddrphy_ck",
1039 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1040 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1041 .modulemode = MODULEMODE_HWCTRL,
1047 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1048 { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1052 static struct omap_hwmod omap44xx_emif2_hwmod = {
1054 .class = &omap44xx_emif_hwmod_class,
1055 .clkdm_name = "l3_emif_clkdm",
1056 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1057 .mpu_irqs = omap44xx_emif2_irqs,
1058 .main_clk = "ddrphy_ck",
1061 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1062 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1063 .modulemode = MODULEMODE_HWCTRL,
1070 * face detection hw accelerator module
1073 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1075 .sysc_offs = 0x0010,
1077 * FDIF needs 100 OCP clk cycles delay after a softreset before
1078 * accessing sysconfig again.
1079 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1080 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1082 * TODO: Indicate errata when available.
1085 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1086 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1087 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1088 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1089 .sysc_fields = &omap_hwmod_sysc_type2,
1092 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1094 .sysc = &omap44xx_fdif_sysc,
1098 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1099 { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1103 static struct omap_hwmod omap44xx_fdif_hwmod = {
1105 .class = &omap44xx_fdif_hwmod_class,
1106 .clkdm_name = "iss_clkdm",
1107 .mpu_irqs = omap44xx_fdif_irqs,
1108 .main_clk = "fdif_fck",
1111 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1112 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1113 .modulemode = MODULEMODE_SWCTRL,
1120 * general purpose io module
1123 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1125 .sysc_offs = 0x0010,
1126 .syss_offs = 0x0114,
1127 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1128 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1129 SYSS_HAS_RESET_STATUS),
1130 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1132 .sysc_fields = &omap_hwmod_sysc_type1,
1135 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1137 .sysc = &omap44xx_gpio_sysc,
1142 static struct omap_gpio_dev_attr gpio_dev_attr = {
1148 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1149 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1153 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1154 { .role = "dbclk", .clk = "gpio1_dbclk" },
1157 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1159 .class = &omap44xx_gpio_hwmod_class,
1160 .clkdm_name = "l4_wkup_clkdm",
1161 .mpu_irqs = omap44xx_gpio1_irqs,
1162 .main_clk = "gpio1_ick",
1165 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1166 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1167 .modulemode = MODULEMODE_HWCTRL,
1170 .opt_clks = gpio1_opt_clks,
1171 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1172 .dev_attr = &gpio_dev_attr,
1176 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1177 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1181 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1182 { .role = "dbclk", .clk = "gpio2_dbclk" },
1185 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1187 .class = &omap44xx_gpio_hwmod_class,
1188 .clkdm_name = "l4_per_clkdm",
1189 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1190 .mpu_irqs = omap44xx_gpio2_irqs,
1191 .main_clk = "gpio2_ick",
1194 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1195 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1196 .modulemode = MODULEMODE_HWCTRL,
1199 .opt_clks = gpio2_opt_clks,
1200 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1201 .dev_attr = &gpio_dev_attr,
1205 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1206 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1210 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1211 { .role = "dbclk", .clk = "gpio3_dbclk" },
1214 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1216 .class = &omap44xx_gpio_hwmod_class,
1217 .clkdm_name = "l4_per_clkdm",
1218 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1219 .mpu_irqs = omap44xx_gpio3_irqs,
1220 .main_clk = "gpio3_ick",
1223 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1224 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1225 .modulemode = MODULEMODE_HWCTRL,
1228 .opt_clks = gpio3_opt_clks,
1229 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1230 .dev_attr = &gpio_dev_attr,
1234 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1235 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1239 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1240 { .role = "dbclk", .clk = "gpio4_dbclk" },
1243 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1245 .class = &omap44xx_gpio_hwmod_class,
1246 .clkdm_name = "l4_per_clkdm",
1247 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1248 .mpu_irqs = omap44xx_gpio4_irqs,
1249 .main_clk = "gpio4_ick",
1252 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1253 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1254 .modulemode = MODULEMODE_HWCTRL,
1257 .opt_clks = gpio4_opt_clks,
1258 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1259 .dev_attr = &gpio_dev_attr,
1263 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1264 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1268 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1269 { .role = "dbclk", .clk = "gpio5_dbclk" },
1272 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1274 .class = &omap44xx_gpio_hwmod_class,
1275 .clkdm_name = "l4_per_clkdm",
1276 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1277 .mpu_irqs = omap44xx_gpio5_irqs,
1278 .main_clk = "gpio5_ick",
1281 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1282 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1283 .modulemode = MODULEMODE_HWCTRL,
1286 .opt_clks = gpio5_opt_clks,
1287 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1288 .dev_attr = &gpio_dev_attr,
1292 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1293 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1297 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1298 { .role = "dbclk", .clk = "gpio6_dbclk" },
1301 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1303 .class = &omap44xx_gpio_hwmod_class,
1304 .clkdm_name = "l4_per_clkdm",
1305 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1306 .mpu_irqs = omap44xx_gpio6_irqs,
1307 .main_clk = "gpio6_ick",
1310 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1311 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1312 .modulemode = MODULEMODE_HWCTRL,
1315 .opt_clks = gpio6_opt_clks,
1316 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1317 .dev_attr = &gpio_dev_attr,
1322 * general purpose memory controller
1325 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1327 .sysc_offs = 0x0010,
1328 .syss_offs = 0x0014,
1329 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1330 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1331 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1332 .sysc_fields = &omap_hwmod_sysc_type1,
1335 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1337 .sysc = &omap44xx_gpmc_sysc,
1341 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1342 { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1346 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1347 { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1351 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1353 .class = &omap44xx_gpmc_hwmod_class,
1354 .clkdm_name = "l3_2_clkdm",
1356 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1357 * block. It is not being added due to any known bugs with
1358 * resetting the GPMC IP block, but rather because any timings
1359 * set by the bootloader are not being correctly programmed by
1360 * the kernel from the board file or DT data.
1361 * HWMOD_INIT_NO_RESET should be removed ASAP.
1363 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1364 .mpu_irqs = omap44xx_gpmc_irqs,
1365 .sdma_reqs = omap44xx_gpmc_sdma_reqs,
1368 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1369 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1370 .modulemode = MODULEMODE_HWCTRL,
1377 * 2d/3d graphics accelerator
1380 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1381 .rev_offs = 0x1fc00,
1382 .sysc_offs = 0x1fc10,
1383 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1384 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1385 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1386 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1387 .sysc_fields = &omap_hwmod_sysc_type2,
1390 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1392 .sysc = &omap44xx_gpu_sysc,
1396 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1397 { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1401 static struct omap_hwmod omap44xx_gpu_hwmod = {
1403 .class = &omap44xx_gpu_hwmod_class,
1404 .clkdm_name = "l3_gfx_clkdm",
1405 .mpu_irqs = omap44xx_gpu_irqs,
1406 .main_clk = "gpu_fck",
1409 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1410 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1411 .modulemode = MODULEMODE_SWCTRL,
1418 * hdq / 1-wire serial interface controller
1421 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1423 .sysc_offs = 0x0014,
1424 .syss_offs = 0x0018,
1425 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1426 SYSS_HAS_RESET_STATUS),
1427 .sysc_fields = &omap_hwmod_sysc_type1,
1430 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1432 .sysc = &omap44xx_hdq1w_sysc,
1436 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1437 { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1441 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1443 .class = &omap44xx_hdq1w_hwmod_class,
1444 .clkdm_name = "l4_per_clkdm",
1445 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1446 .mpu_irqs = omap44xx_hdq1w_irqs,
1447 .main_clk = "hdq1w_fck",
1450 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1451 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1452 .modulemode = MODULEMODE_SWCTRL,
1459 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1463 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1465 .sysc_offs = 0x0010,
1466 .syss_offs = 0x0014,
1467 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1468 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1469 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1470 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1471 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1472 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1473 .sysc_fields = &omap_hwmod_sysc_type1,
1476 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1478 .sysc = &omap44xx_hsi_sysc,
1482 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1483 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1484 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1485 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1489 static struct omap_hwmod omap44xx_hsi_hwmod = {
1491 .class = &omap44xx_hsi_hwmod_class,
1492 .clkdm_name = "l3_init_clkdm",
1493 .mpu_irqs = omap44xx_hsi_irqs,
1494 .main_clk = "hsi_fck",
1497 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1498 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1499 .modulemode = MODULEMODE_HWCTRL,
1506 * multimaster high-speed i2c controller
1509 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1510 .sysc_offs = 0x0010,
1511 .syss_offs = 0x0090,
1512 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1513 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1514 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1515 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1517 .clockact = CLOCKACT_TEST_ICLK,
1518 .sysc_fields = &omap_hwmod_sysc_type1,
1521 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1523 .sysc = &omap44xx_i2c_sysc,
1524 .rev = OMAP_I2C_IP_VERSION_2,
1525 .reset = &omap_i2c_reset,
1528 static struct omap_i2c_dev_attr i2c_dev_attr = {
1529 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1530 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1534 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1535 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1539 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1540 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1541 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1545 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1547 .class = &omap44xx_i2c_hwmod_class,
1548 .clkdm_name = "l4_per_clkdm",
1549 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1550 .mpu_irqs = omap44xx_i2c1_irqs,
1551 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1552 .main_clk = "i2c1_fck",
1555 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1556 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1557 .modulemode = MODULEMODE_SWCTRL,
1560 .dev_attr = &i2c_dev_attr,
1564 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1565 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1569 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1570 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1571 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1575 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1577 .class = &omap44xx_i2c_hwmod_class,
1578 .clkdm_name = "l4_per_clkdm",
1579 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1580 .mpu_irqs = omap44xx_i2c2_irqs,
1581 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1582 .main_clk = "i2c2_fck",
1585 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1586 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1587 .modulemode = MODULEMODE_SWCTRL,
1590 .dev_attr = &i2c_dev_attr,
1594 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1595 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1599 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1600 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1601 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1605 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1607 .class = &omap44xx_i2c_hwmod_class,
1608 .clkdm_name = "l4_per_clkdm",
1609 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1610 .mpu_irqs = omap44xx_i2c3_irqs,
1611 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1612 .main_clk = "i2c3_fck",
1615 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1616 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1617 .modulemode = MODULEMODE_SWCTRL,
1620 .dev_attr = &i2c_dev_attr,
1624 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1625 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1629 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1630 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1631 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1635 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1637 .class = &omap44xx_i2c_hwmod_class,
1638 .clkdm_name = "l4_per_clkdm",
1639 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1640 .mpu_irqs = omap44xx_i2c4_irqs,
1641 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1642 .main_clk = "i2c4_fck",
1645 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1646 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1647 .modulemode = MODULEMODE_SWCTRL,
1650 .dev_attr = &i2c_dev_attr,
1655 * imaging processor unit
1658 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1663 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1664 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1668 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1669 { .name = "cpu0", .rst_shift = 0 },
1670 { .name = "cpu1", .rst_shift = 1 },
1673 static struct omap_hwmod omap44xx_ipu_hwmod = {
1675 .class = &omap44xx_ipu_hwmod_class,
1676 .clkdm_name = "ducati_clkdm",
1677 .mpu_irqs = omap44xx_ipu_irqs,
1678 .rst_lines = omap44xx_ipu_resets,
1679 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1680 .main_clk = "ipu_fck",
1683 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1684 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1685 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1686 .modulemode = MODULEMODE_HWCTRL,
1693 * external images sensor pixel data processor
1696 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1698 .sysc_offs = 0x0010,
1700 * ISS needs 100 OCP clk cycles delay after a softreset before
1701 * accessing sysconfig again.
1702 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1703 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1705 * TODO: Indicate errata when available.
1708 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1709 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1710 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1711 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1712 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1713 .sysc_fields = &omap_hwmod_sysc_type2,
1716 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1718 .sysc = &omap44xx_iss_sysc,
1722 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1723 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1727 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1728 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1729 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1730 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1731 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1735 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1736 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1739 static struct omap_hwmod omap44xx_iss_hwmod = {
1741 .class = &omap44xx_iss_hwmod_class,
1742 .clkdm_name = "iss_clkdm",
1743 .mpu_irqs = omap44xx_iss_irqs,
1744 .sdma_reqs = omap44xx_iss_sdma_reqs,
1745 .main_clk = "iss_fck",
1748 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1749 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1750 .modulemode = MODULEMODE_SWCTRL,
1753 .opt_clks = iss_opt_clks,
1754 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1759 * multi-standard video encoder/decoder hardware accelerator
1762 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1767 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1768 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1769 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1770 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1774 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1775 { .name = "seq0", .rst_shift = 0 },
1776 { .name = "seq1", .rst_shift = 1 },
1777 { .name = "logic", .rst_shift = 2 },
1780 static struct omap_hwmod omap44xx_iva_hwmod = {
1782 .class = &omap44xx_iva_hwmod_class,
1783 .clkdm_name = "ivahd_clkdm",
1784 .mpu_irqs = omap44xx_iva_irqs,
1785 .rst_lines = omap44xx_iva_resets,
1786 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1787 .main_clk = "iva_fck",
1790 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1791 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1792 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1793 .modulemode = MODULEMODE_HWCTRL,
1800 * keyboard controller
1803 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1805 .sysc_offs = 0x0010,
1806 .syss_offs = 0x0014,
1807 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1808 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1809 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1810 SYSS_HAS_RESET_STATUS),
1811 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1812 .sysc_fields = &omap_hwmod_sysc_type1,
1815 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1817 .sysc = &omap44xx_kbd_sysc,
1821 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1822 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1826 static struct omap_hwmod omap44xx_kbd_hwmod = {
1828 .class = &omap44xx_kbd_hwmod_class,
1829 .clkdm_name = "l4_wkup_clkdm",
1830 .mpu_irqs = omap44xx_kbd_irqs,
1831 .main_clk = "kbd_fck",
1834 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1835 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1836 .modulemode = MODULEMODE_SWCTRL,
1843 * mailbox module allowing communication between the on-chip processors using a
1844 * queued mailbox-interrupt mechanism.
1847 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1849 .sysc_offs = 0x0010,
1850 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1851 SYSC_HAS_SOFTRESET),
1852 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1853 .sysc_fields = &omap_hwmod_sysc_type2,
1856 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1858 .sysc = &omap44xx_mailbox_sysc,
1862 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1863 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1867 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1869 .class = &omap44xx_mailbox_hwmod_class,
1870 .clkdm_name = "l4_cfg_clkdm",
1871 .mpu_irqs = omap44xx_mailbox_irqs,
1874 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1875 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1882 * multi-channel audio serial port controller
1885 /* The IP is not compliant to type1 / type2 scheme */
1886 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1890 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1891 .sysc_offs = 0x0004,
1892 .sysc_flags = SYSC_HAS_SIDLEMODE,
1893 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1895 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1898 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1900 .sysc = &omap44xx_mcasp_sysc,
1904 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1905 { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1906 { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1910 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1911 { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1912 { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1916 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1918 .class = &omap44xx_mcasp_hwmod_class,
1919 .clkdm_name = "abe_clkdm",
1920 .mpu_irqs = omap44xx_mcasp_irqs,
1921 .sdma_reqs = omap44xx_mcasp_sdma_reqs,
1922 .main_clk = "mcasp_fck",
1925 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1926 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1927 .modulemode = MODULEMODE_SWCTRL,
1934 * multi channel buffered serial port controller
1937 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1938 .sysc_offs = 0x008c,
1939 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1940 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1941 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1942 .sysc_fields = &omap_hwmod_sysc_type1,
1945 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1947 .sysc = &omap44xx_mcbsp_sysc,
1948 .rev = MCBSP_CONFIG_TYPE4,
1952 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1953 { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1957 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1958 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1959 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1963 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1964 { .role = "pad_fck", .clk = "pad_clks_ck" },
1965 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1968 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1970 .class = &omap44xx_mcbsp_hwmod_class,
1971 .clkdm_name = "abe_clkdm",
1972 .mpu_irqs = omap44xx_mcbsp1_irqs,
1973 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
1974 .main_clk = "mcbsp1_fck",
1977 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1978 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1979 .modulemode = MODULEMODE_SWCTRL,
1982 .opt_clks = mcbsp1_opt_clks,
1983 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1987 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1988 { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1992 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1993 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1994 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1998 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1999 { .role = "pad_fck", .clk = "pad_clks_ck" },
2000 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2003 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2005 .class = &omap44xx_mcbsp_hwmod_class,
2006 .clkdm_name = "abe_clkdm",
2007 .mpu_irqs = omap44xx_mcbsp2_irqs,
2008 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
2009 .main_clk = "mcbsp2_fck",
2012 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2013 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2014 .modulemode = MODULEMODE_SWCTRL,
2017 .opt_clks = mcbsp2_opt_clks,
2018 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
2022 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2023 { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2027 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2028 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2029 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2033 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2034 { .role = "pad_fck", .clk = "pad_clks_ck" },
2035 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2038 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2040 .class = &omap44xx_mcbsp_hwmod_class,
2041 .clkdm_name = "abe_clkdm",
2042 .mpu_irqs = omap44xx_mcbsp3_irqs,
2043 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
2044 .main_clk = "mcbsp3_fck",
2047 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2048 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2049 .modulemode = MODULEMODE_SWCTRL,
2052 .opt_clks = mcbsp3_opt_clks,
2053 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
2057 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2058 { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2062 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2063 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2064 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2068 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2069 { .role = "pad_fck", .clk = "pad_clks_ck" },
2070 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2073 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2075 .class = &omap44xx_mcbsp_hwmod_class,
2076 .clkdm_name = "l4_per_clkdm",
2077 .mpu_irqs = omap44xx_mcbsp4_irqs,
2078 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
2079 .main_clk = "mcbsp4_fck",
2082 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2083 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2084 .modulemode = MODULEMODE_SWCTRL,
2087 .opt_clks = mcbsp4_opt_clks,
2088 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
2093 * multi channel pdm controller (proprietary interface with phoenix power
2097 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2099 .sysc_offs = 0x0010,
2100 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2101 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2102 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2104 .sysc_fields = &omap_hwmod_sysc_type2,
2107 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2109 .sysc = &omap44xx_mcpdm_sysc,
2113 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2114 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2118 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2119 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2120 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2124 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2126 .class = &omap44xx_mcpdm_hwmod_class,
2127 .clkdm_name = "abe_clkdm",
2128 .mpu_irqs = omap44xx_mcpdm_irqs,
2129 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
2130 .main_clk = "mcpdm_fck",
2133 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2134 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2135 .modulemode = MODULEMODE_SWCTRL,
2142 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2146 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2148 .sysc_offs = 0x0010,
2149 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2150 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2151 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2153 .sysc_fields = &omap_hwmod_sysc_type2,
2156 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2158 .sysc = &omap44xx_mcspi_sysc,
2159 .rev = OMAP4_MCSPI_REV,
2163 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2164 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2168 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2169 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2170 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2171 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2172 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2173 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2174 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2175 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2176 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2180 /* mcspi1 dev_attr */
2181 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2182 .num_chipselect = 4,
2185 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2187 .class = &omap44xx_mcspi_hwmod_class,
2188 .clkdm_name = "l4_per_clkdm",
2189 .mpu_irqs = omap44xx_mcspi1_irqs,
2190 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
2191 .main_clk = "mcspi1_fck",
2194 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2195 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2196 .modulemode = MODULEMODE_SWCTRL,
2199 .dev_attr = &mcspi1_dev_attr,
2203 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2204 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2208 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2209 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2210 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2211 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2212 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2216 /* mcspi2 dev_attr */
2217 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2218 .num_chipselect = 2,
2221 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2223 .class = &omap44xx_mcspi_hwmod_class,
2224 .clkdm_name = "l4_per_clkdm",
2225 .mpu_irqs = omap44xx_mcspi2_irqs,
2226 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
2227 .main_clk = "mcspi2_fck",
2230 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2231 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2232 .modulemode = MODULEMODE_SWCTRL,
2235 .dev_attr = &mcspi2_dev_attr,
2239 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2240 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2244 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2245 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2246 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2247 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2248 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2252 /* mcspi3 dev_attr */
2253 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2254 .num_chipselect = 2,
2257 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2259 .class = &omap44xx_mcspi_hwmod_class,
2260 .clkdm_name = "l4_per_clkdm",
2261 .mpu_irqs = omap44xx_mcspi3_irqs,
2262 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
2263 .main_clk = "mcspi3_fck",
2266 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2267 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2268 .modulemode = MODULEMODE_SWCTRL,
2271 .dev_attr = &mcspi3_dev_attr,
2275 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2276 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2280 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2281 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2282 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2286 /* mcspi4 dev_attr */
2287 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2288 .num_chipselect = 1,
2291 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2293 .class = &omap44xx_mcspi_hwmod_class,
2294 .clkdm_name = "l4_per_clkdm",
2295 .mpu_irqs = omap44xx_mcspi4_irqs,
2296 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
2297 .main_clk = "mcspi4_fck",
2300 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2301 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2302 .modulemode = MODULEMODE_SWCTRL,
2305 .dev_attr = &mcspi4_dev_attr,
2310 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2313 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2315 .sysc_offs = 0x0010,
2316 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2317 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2318 SYSC_HAS_SOFTRESET),
2319 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2320 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2321 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2322 .sysc_fields = &omap_hwmod_sysc_type2,
2325 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2327 .sysc = &omap44xx_mmc_sysc,
2331 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2332 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2336 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2337 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2338 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2343 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2344 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2347 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2349 .class = &omap44xx_mmc_hwmod_class,
2350 .clkdm_name = "l3_init_clkdm",
2351 .mpu_irqs = omap44xx_mmc1_irqs,
2352 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
2353 .main_clk = "mmc1_fck",
2356 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2357 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2358 .modulemode = MODULEMODE_SWCTRL,
2361 .dev_attr = &mmc1_dev_attr,
2365 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2366 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2370 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2371 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2372 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2376 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2378 .class = &omap44xx_mmc_hwmod_class,
2379 .clkdm_name = "l3_init_clkdm",
2380 .mpu_irqs = omap44xx_mmc2_irqs,
2381 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
2382 .main_clk = "mmc2_fck",
2385 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2386 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2387 .modulemode = MODULEMODE_SWCTRL,
2393 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2394 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2398 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2399 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2400 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2404 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2406 .class = &omap44xx_mmc_hwmod_class,
2407 .clkdm_name = "l4_per_clkdm",
2408 .mpu_irqs = omap44xx_mmc3_irqs,
2409 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2410 .main_clk = "mmc3_fck",
2413 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2414 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2415 .modulemode = MODULEMODE_SWCTRL,
2421 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2422 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2426 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2427 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2428 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2432 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2434 .class = &omap44xx_mmc_hwmod_class,
2435 .clkdm_name = "l4_per_clkdm",
2436 .mpu_irqs = omap44xx_mmc4_irqs,
2437 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2438 .main_clk = "mmc4_fck",
2441 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2442 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2443 .modulemode = MODULEMODE_SWCTRL,
2449 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2450 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2454 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2455 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2456 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2460 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2462 .class = &omap44xx_mmc_hwmod_class,
2463 .clkdm_name = "l4_per_clkdm",
2464 .mpu_irqs = omap44xx_mmc5_irqs,
2465 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2466 .main_clk = "mmc5_fck",
2469 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2470 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2471 .modulemode = MODULEMODE_SWCTRL,
2478 * The memory management unit performs virtual to physical address translation
2479 * for its requestors.
2482 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2486 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2487 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2488 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2489 .sysc_fields = &omap_hwmod_sysc_type1,
2492 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2499 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2501 .da_end = 0xfffff000,
2502 .nr_tlb_entries = 32,
2505 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2506 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2507 { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2511 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2512 { .name = "mmu_cache", .rst_shift = 2 },
2515 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2517 .pa_start = 0x55082000,
2518 .pa_end = 0x550820ff,
2519 .flags = ADDR_TYPE_RT,
2524 /* l3_main_2 -> mmu_ipu */
2525 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2526 .master = &omap44xx_l3_main_2_hwmod,
2527 .slave = &omap44xx_mmu_ipu_hwmod,
2529 .addr = omap44xx_mmu_ipu_addrs,
2530 .user = OCP_USER_MPU | OCP_USER_SDMA,
2533 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2535 .class = &omap44xx_mmu_hwmod_class,
2536 .clkdm_name = "ducati_clkdm",
2537 .mpu_irqs = omap44xx_mmu_ipu_irqs,
2538 .rst_lines = omap44xx_mmu_ipu_resets,
2539 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2540 .main_clk = "ducati_clk_mux_ck",
2543 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2544 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2545 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2546 .modulemode = MODULEMODE_HWCTRL,
2549 .dev_attr = &mmu_ipu_dev_attr,
2554 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2556 .da_end = 0xfffff000,
2557 .nr_tlb_entries = 32,
2560 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2561 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2562 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2566 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2567 { .name = "mmu_cache", .rst_shift = 1 },
2570 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2572 .pa_start = 0x4a066000,
2573 .pa_end = 0x4a0660ff,
2574 .flags = ADDR_TYPE_RT,
2580 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2581 .master = &omap44xx_l4_cfg_hwmod,
2582 .slave = &omap44xx_mmu_dsp_hwmod,
2584 .addr = omap44xx_mmu_dsp_addrs,
2585 .user = OCP_USER_MPU | OCP_USER_SDMA,
2588 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2590 .class = &omap44xx_mmu_hwmod_class,
2591 .clkdm_name = "tesla_clkdm",
2592 .mpu_irqs = omap44xx_mmu_dsp_irqs,
2593 .rst_lines = omap44xx_mmu_dsp_resets,
2594 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2595 .main_clk = "dpll_iva_m4x2_ck",
2598 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2599 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2600 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2601 .modulemode = MODULEMODE_HWCTRL,
2604 .dev_attr = &mmu_dsp_dev_attr,
2612 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2617 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2618 { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2619 { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2620 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2621 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2622 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2626 static struct omap_hwmod omap44xx_mpu_hwmod = {
2628 .class = &omap44xx_mpu_hwmod_class,
2629 .clkdm_name = "mpuss_clkdm",
2630 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2631 .mpu_irqs = omap44xx_mpu_irqs,
2632 .main_clk = "dpll_mpu_m2_ck",
2635 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2636 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2643 * top-level core on-chip ram
2646 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2651 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2653 .class = &omap44xx_ocmc_ram_hwmod_class,
2654 .clkdm_name = "l3_2_clkdm",
2657 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2658 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2665 * bridge to transform ocp interface protocol to scp (serial control port)
2669 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2671 .sysc_offs = 0x0010,
2672 .syss_offs = 0x0014,
2673 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2674 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2675 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2676 .sysc_fields = &omap_hwmod_sysc_type1,
2679 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2681 .sysc = &omap44xx_ocp2scp_sysc,
2684 /* ocp2scp_usb_phy */
2685 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2686 .name = "ocp2scp_usb_phy",
2687 .class = &omap44xx_ocp2scp_hwmod_class,
2688 .clkdm_name = "l3_init_clkdm",
2689 .main_clk = "ocp2scp_usb_phy_phy_48m",
2692 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2693 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2694 .modulemode = MODULEMODE_HWCTRL,
2701 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2702 * + clock manager 1 (in always on power domain) + local prm in mpu
2705 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2710 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2712 .class = &omap44xx_prcm_hwmod_class,
2713 .clkdm_name = "l4_wkup_clkdm",
2714 .flags = HWMOD_NO_IDLEST,
2717 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2723 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2724 .name = "cm_core_aon",
2725 .class = &omap44xx_prcm_hwmod_class,
2726 .flags = HWMOD_NO_IDLEST,
2729 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2735 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2737 .class = &omap44xx_prcm_hwmod_class,
2738 .flags = HWMOD_NO_IDLEST,
2741 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2747 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2748 { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2752 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2753 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2754 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2757 static struct omap_hwmod omap44xx_prm_hwmod = {
2759 .class = &omap44xx_prcm_hwmod_class,
2760 .mpu_irqs = omap44xx_prm_irqs,
2761 .rst_lines = omap44xx_prm_resets,
2762 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2767 * system clock and reset manager
2770 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2775 static struct omap_hwmod omap44xx_scrm_hwmod = {
2777 .class = &omap44xx_scrm_hwmod_class,
2778 .clkdm_name = "l4_wkup_clkdm",
2781 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2788 * shared level 2 memory interface
2791 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2796 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2798 .class = &omap44xx_sl2if_hwmod_class,
2799 .clkdm_name = "ivahd_clkdm",
2802 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2803 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2804 .modulemode = MODULEMODE_HWCTRL,
2811 * bidirectional, multi-drop, multi-channel two-line serial interface between
2812 * the device and external components
2815 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2817 .sysc_offs = 0x0010,
2818 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2819 SYSC_HAS_SOFTRESET),
2820 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2822 .sysc_fields = &omap_hwmod_sysc_type2,
2825 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2827 .sysc = &omap44xx_slimbus_sysc,
2831 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2832 { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2836 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2837 { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2838 { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2839 { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2840 { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2841 { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2842 { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2843 { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2844 { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2848 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2849 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2850 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2851 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2852 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2855 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2857 .class = &omap44xx_slimbus_hwmod_class,
2858 .clkdm_name = "abe_clkdm",
2859 .mpu_irqs = omap44xx_slimbus1_irqs,
2860 .sdma_reqs = omap44xx_slimbus1_sdma_reqs,
2863 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2864 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2865 .modulemode = MODULEMODE_SWCTRL,
2868 .opt_clks = slimbus1_opt_clks,
2869 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2873 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2874 { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2878 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2879 { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2880 { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2881 { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2882 { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2883 { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2884 { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2885 { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2886 { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2890 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2891 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2892 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2893 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2896 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2898 .class = &omap44xx_slimbus_hwmod_class,
2899 .clkdm_name = "l4_per_clkdm",
2900 .mpu_irqs = omap44xx_slimbus2_irqs,
2901 .sdma_reqs = omap44xx_slimbus2_sdma_reqs,
2904 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2905 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2906 .modulemode = MODULEMODE_SWCTRL,
2909 .opt_clks = slimbus2_opt_clks,
2910 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2914 * 'smartreflex' class
2915 * smartreflex module (monitor silicon performance and outputs a measure of
2916 * performance error)
2919 /* The IP is not compliant to type1 / type2 scheme */
2920 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2925 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2926 .sysc_offs = 0x0038,
2927 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2928 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2930 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2933 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2934 .name = "smartreflex",
2935 .sysc = &omap44xx_smartreflex_sysc,
2939 /* smartreflex_core */
2940 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2941 .sensor_voltdm_name = "core",
2944 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2945 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2949 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2950 .name = "smartreflex_core",
2951 .class = &omap44xx_smartreflex_hwmod_class,
2952 .clkdm_name = "l4_ao_clkdm",
2953 .mpu_irqs = omap44xx_smartreflex_core_irqs,
2955 .main_clk = "smartreflex_core_fck",
2958 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2959 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2960 .modulemode = MODULEMODE_SWCTRL,
2963 .dev_attr = &smartreflex_core_dev_attr,
2966 /* smartreflex_iva */
2967 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2968 .sensor_voltdm_name = "iva",
2971 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
2972 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
2976 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2977 .name = "smartreflex_iva",
2978 .class = &omap44xx_smartreflex_hwmod_class,
2979 .clkdm_name = "l4_ao_clkdm",
2980 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
2981 .main_clk = "smartreflex_iva_fck",
2984 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2985 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2986 .modulemode = MODULEMODE_SWCTRL,
2989 .dev_attr = &smartreflex_iva_dev_attr,
2992 /* smartreflex_mpu */
2993 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2994 .sensor_voltdm_name = "mpu",
2997 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
2998 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3002 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3003 .name = "smartreflex_mpu",
3004 .class = &omap44xx_smartreflex_hwmod_class,
3005 .clkdm_name = "l4_ao_clkdm",
3006 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
3007 .main_clk = "smartreflex_mpu_fck",
3010 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3011 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3012 .modulemode = MODULEMODE_SWCTRL,
3015 .dev_attr = &smartreflex_mpu_dev_attr,
3020 * spinlock provides hardware assistance for synchronizing the processes
3021 * running on multiple processors
3024 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3026 .sysc_offs = 0x0010,
3027 .syss_offs = 0x0014,
3028 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3029 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3030 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3031 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3033 .sysc_fields = &omap_hwmod_sysc_type1,
3036 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3038 .sysc = &omap44xx_spinlock_sysc,
3042 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3044 .class = &omap44xx_spinlock_hwmod_class,
3045 .clkdm_name = "l4_cfg_clkdm",
3048 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3049 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3056 * general purpose timer module with accurate 1ms tick
3057 * This class contains several variants: ['timer_1ms', 'timer']
3060 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3062 .sysc_offs = 0x0010,
3063 .syss_offs = 0x0014,
3064 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3065 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3066 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3067 SYSS_HAS_RESET_STATUS),
3068 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3069 .sysc_fields = &omap_hwmod_sysc_type1,
3072 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3074 .sysc = &omap44xx_timer_1ms_sysc,
3077 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3079 .sysc_offs = 0x0010,
3080 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3081 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3082 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3084 .sysc_fields = &omap_hwmod_sysc_type2,
3087 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3089 .sysc = &omap44xx_timer_sysc,
3092 /* always-on timers dev attribute */
3093 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3094 .timer_capability = OMAP_TIMER_ALWON,
3097 /* pwm timers dev attribute */
3098 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3099 .timer_capability = OMAP_TIMER_HAS_PWM,
3102 /* timers with DSP interrupt dev attribute */
3103 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3104 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
3107 /* pwm timers with DSP interrupt dev attribute */
3108 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3109 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3113 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3114 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3118 static struct omap_hwmod omap44xx_timer1_hwmod = {
3120 .class = &omap44xx_timer_1ms_hwmod_class,
3121 .clkdm_name = "l4_wkup_clkdm",
3122 .mpu_irqs = omap44xx_timer1_irqs,
3123 .main_clk = "timer1_fck",
3126 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3127 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3128 .modulemode = MODULEMODE_SWCTRL,
3131 .dev_attr = &capability_alwon_dev_attr,
3135 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3136 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3140 static struct omap_hwmod omap44xx_timer2_hwmod = {
3142 .class = &omap44xx_timer_1ms_hwmod_class,
3143 .clkdm_name = "l4_per_clkdm",
3144 .mpu_irqs = omap44xx_timer2_irqs,
3145 .main_clk = "timer2_fck",
3148 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3149 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3150 .modulemode = MODULEMODE_SWCTRL,
3156 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3157 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3161 static struct omap_hwmod omap44xx_timer3_hwmod = {
3163 .class = &omap44xx_timer_hwmod_class,
3164 .clkdm_name = "l4_per_clkdm",
3165 .mpu_irqs = omap44xx_timer3_irqs,
3166 .main_clk = "timer3_fck",
3169 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3170 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3171 .modulemode = MODULEMODE_SWCTRL,
3177 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3178 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3182 static struct omap_hwmod omap44xx_timer4_hwmod = {
3184 .class = &omap44xx_timer_hwmod_class,
3185 .clkdm_name = "l4_per_clkdm",
3186 .mpu_irqs = omap44xx_timer4_irqs,
3187 .main_clk = "timer4_fck",
3190 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3191 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3192 .modulemode = MODULEMODE_SWCTRL,
3198 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3199 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3203 static struct omap_hwmod omap44xx_timer5_hwmod = {
3205 .class = &omap44xx_timer_hwmod_class,
3206 .clkdm_name = "abe_clkdm",
3207 .mpu_irqs = omap44xx_timer5_irqs,
3208 .main_clk = "timer5_fck",
3211 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3212 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3213 .modulemode = MODULEMODE_SWCTRL,
3216 .dev_attr = &capability_dsp_dev_attr,
3220 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3221 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3225 static struct omap_hwmod omap44xx_timer6_hwmod = {
3227 .class = &omap44xx_timer_hwmod_class,
3228 .clkdm_name = "abe_clkdm",
3229 .mpu_irqs = omap44xx_timer6_irqs,
3231 .main_clk = "timer6_fck",
3234 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3235 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3236 .modulemode = MODULEMODE_SWCTRL,
3239 .dev_attr = &capability_dsp_dev_attr,
3243 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3244 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3248 static struct omap_hwmod omap44xx_timer7_hwmod = {
3250 .class = &omap44xx_timer_hwmod_class,
3251 .clkdm_name = "abe_clkdm",
3252 .mpu_irqs = omap44xx_timer7_irqs,
3253 .main_clk = "timer7_fck",
3256 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3257 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3258 .modulemode = MODULEMODE_SWCTRL,
3261 .dev_attr = &capability_dsp_dev_attr,
3265 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3266 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3270 static struct omap_hwmod omap44xx_timer8_hwmod = {
3272 .class = &omap44xx_timer_hwmod_class,
3273 .clkdm_name = "abe_clkdm",
3274 .mpu_irqs = omap44xx_timer8_irqs,
3275 .main_clk = "timer8_fck",
3278 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3279 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3280 .modulemode = MODULEMODE_SWCTRL,
3283 .dev_attr = &capability_dsp_pwm_dev_attr,
3287 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3288 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3292 static struct omap_hwmod omap44xx_timer9_hwmod = {
3294 .class = &omap44xx_timer_hwmod_class,
3295 .clkdm_name = "l4_per_clkdm",
3296 .mpu_irqs = omap44xx_timer9_irqs,
3297 .main_clk = "timer9_fck",
3300 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3301 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3302 .modulemode = MODULEMODE_SWCTRL,
3305 .dev_attr = &capability_pwm_dev_attr,
3309 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3310 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3314 static struct omap_hwmod omap44xx_timer10_hwmod = {
3316 .class = &omap44xx_timer_1ms_hwmod_class,
3317 .clkdm_name = "l4_per_clkdm",
3318 .mpu_irqs = omap44xx_timer10_irqs,
3319 .main_clk = "timer10_fck",
3322 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3323 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3324 .modulemode = MODULEMODE_SWCTRL,
3327 .dev_attr = &capability_pwm_dev_attr,
3331 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3332 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3336 static struct omap_hwmod omap44xx_timer11_hwmod = {
3338 .class = &omap44xx_timer_hwmod_class,
3339 .clkdm_name = "l4_per_clkdm",
3340 .mpu_irqs = omap44xx_timer11_irqs,
3341 .main_clk = "timer11_fck",
3344 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3345 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3346 .modulemode = MODULEMODE_SWCTRL,
3349 .dev_attr = &capability_pwm_dev_attr,
3354 * universal asynchronous receiver/transmitter (uart)
3357 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3359 .sysc_offs = 0x0054,
3360 .syss_offs = 0x0058,
3361 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3362 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3363 SYSS_HAS_RESET_STATUS),
3364 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3366 .sysc_fields = &omap_hwmod_sysc_type1,
3369 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3371 .sysc = &omap44xx_uart_sysc,
3375 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3376 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3380 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3381 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3382 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3386 static struct omap_hwmod omap44xx_uart1_hwmod = {
3388 .class = &omap44xx_uart_hwmod_class,
3389 .clkdm_name = "l4_per_clkdm",
3390 .mpu_irqs = omap44xx_uart1_irqs,
3391 .sdma_reqs = omap44xx_uart1_sdma_reqs,
3392 .main_clk = "uart1_fck",
3395 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3396 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3397 .modulemode = MODULEMODE_SWCTRL,
3403 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3404 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3408 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3409 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3410 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3414 static struct omap_hwmod omap44xx_uart2_hwmod = {
3416 .class = &omap44xx_uart_hwmod_class,
3417 .clkdm_name = "l4_per_clkdm",
3418 .mpu_irqs = omap44xx_uart2_irqs,
3419 .sdma_reqs = omap44xx_uart2_sdma_reqs,
3420 .main_clk = "uart2_fck",
3423 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3424 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3425 .modulemode = MODULEMODE_SWCTRL,
3431 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3432 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3436 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3437 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3438 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3442 static struct omap_hwmod omap44xx_uart3_hwmod = {
3444 .class = &omap44xx_uart_hwmod_class,
3445 .clkdm_name = "l4_per_clkdm",
3446 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3447 .mpu_irqs = omap44xx_uart3_irqs,
3448 .sdma_reqs = omap44xx_uart3_sdma_reqs,
3449 .main_clk = "uart3_fck",
3452 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3453 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3454 .modulemode = MODULEMODE_SWCTRL,
3460 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3461 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3465 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3466 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3467 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3471 static struct omap_hwmod omap44xx_uart4_hwmod = {
3473 .class = &omap44xx_uart_hwmod_class,
3474 .clkdm_name = "l4_per_clkdm",
3475 .mpu_irqs = omap44xx_uart4_irqs,
3476 .sdma_reqs = omap44xx_uart4_sdma_reqs,
3477 .main_clk = "uart4_fck",
3480 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3481 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3482 .modulemode = MODULEMODE_SWCTRL,
3488 * 'usb_host_fs' class
3489 * full-speed usb host controller
3492 /* The IP is not compliant to type1 / type2 scheme */
3493 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3499 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3501 .sysc_offs = 0x0210,
3502 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3503 SYSC_HAS_SOFTRESET),
3504 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3506 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
3509 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3510 .name = "usb_host_fs",
3511 .sysc = &omap44xx_usb_host_fs_sysc,
3515 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3516 { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3517 { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3521 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3522 .name = "usb_host_fs",
3523 .class = &omap44xx_usb_host_fs_hwmod_class,
3524 .clkdm_name = "l3_init_clkdm",
3525 .mpu_irqs = omap44xx_usb_host_fs_irqs,
3526 .main_clk = "usb_host_fs_fck",
3529 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3530 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3531 .modulemode = MODULEMODE_SWCTRL,
3537 * 'usb_host_hs' class
3538 * high-speed multi-port usb host controller
3541 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3543 .sysc_offs = 0x0010,
3544 .syss_offs = 0x0014,
3545 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3546 SYSC_HAS_SOFTRESET),
3547 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3548 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3549 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3550 .sysc_fields = &omap_hwmod_sysc_type2,
3553 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3554 .name = "usb_host_hs",
3555 .sysc = &omap44xx_usb_host_hs_sysc,
3559 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3560 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3561 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3565 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3566 .name = "usb_host_hs",
3567 .class = &omap44xx_usb_host_hs_hwmod_class,
3568 .clkdm_name = "l3_init_clkdm",
3569 .main_clk = "usb_host_hs_fck",
3572 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3573 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3574 .modulemode = MODULEMODE_SWCTRL,
3577 .mpu_irqs = omap44xx_usb_host_hs_irqs,
3580 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3584 * In the following configuration :
3585 * - USBHOST module is set to smart-idle mode
3586 * - PRCM asserts idle_req to the USBHOST module ( This typically
3587 * happens when the system is going to a low power mode : all ports
3588 * have been suspended, the master part of the USBHOST module has
3589 * entered the standby state, and SW has cut the functional clocks)
3590 * - an USBHOST interrupt occurs before the module is able to answer
3591 * idle_ack, typically a remote wakeup IRQ.
3592 * Then the USB HOST module will enter a deadlock situation where it
3593 * is no more accessible nor functional.
3596 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3600 * Errata: USB host EHCI may stall when entering smart-standby mode
3604 * When the USBHOST module is set to smart-standby mode, and when it is
3605 * ready to enter the standby state (i.e. all ports are suspended and
3606 * all attached devices are in suspend mode), then it can wrongly assert
3607 * the Mstandby signal too early while there are still some residual OCP
3608 * transactions ongoing. If this condition occurs, the internal state
3609 * machine may go to an undefined state and the USB link may be stuck
3610 * upon the next resume.
3613 * Don't use smart standby; use only force standby,
3614 * hence HWMOD_SWSUP_MSTANDBY
3618 * During system boot; If the hwmod framework resets the module
3619 * the module will have smart idle settings; which can lead to deadlock
3620 * (above Errata Id:i660); so, dont reset the module during boot;
3621 * Use HWMOD_INIT_NO_RESET.
3624 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3625 HWMOD_INIT_NO_RESET,
3629 * 'usb_otg_hs' class
3630 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3633 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3635 .sysc_offs = 0x0404,
3636 .syss_offs = 0x0408,
3637 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3638 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3639 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3640 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3641 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3643 .sysc_fields = &omap_hwmod_sysc_type1,
3646 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3647 .name = "usb_otg_hs",
3648 .sysc = &omap44xx_usb_otg_hs_sysc,
3652 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3653 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3654 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3658 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3659 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3662 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3663 .name = "usb_otg_hs",
3664 .class = &omap44xx_usb_otg_hs_hwmod_class,
3665 .clkdm_name = "l3_init_clkdm",
3666 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3667 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
3668 .main_clk = "usb_otg_hs_ick",
3671 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3672 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3673 .modulemode = MODULEMODE_HWCTRL,
3676 .opt_clks = usb_otg_hs_opt_clks,
3677 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3681 * 'usb_tll_hs' class
3682 * usb_tll_hs module is the adapter on the usb_host_hs ports
3685 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3687 .sysc_offs = 0x0010,
3688 .syss_offs = 0x0014,
3689 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3690 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3692 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3693 .sysc_fields = &omap_hwmod_sysc_type1,
3696 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3697 .name = "usb_tll_hs",
3698 .sysc = &omap44xx_usb_tll_hs_sysc,
3701 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3702 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3706 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3707 .name = "usb_tll_hs",
3708 .class = &omap44xx_usb_tll_hs_hwmod_class,
3709 .clkdm_name = "l3_init_clkdm",
3710 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
3711 .main_clk = "usb_tll_hs_ick",
3714 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3715 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3716 .modulemode = MODULEMODE_HWCTRL,
3723 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3724 * overflow condition
3727 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3729 .sysc_offs = 0x0010,
3730 .syss_offs = 0x0014,
3731 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3732 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3733 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3735 .sysc_fields = &omap_hwmod_sysc_type1,
3738 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3740 .sysc = &omap44xx_wd_timer_sysc,
3741 .pre_shutdown = &omap2_wd_timer_disable,
3742 .reset = &omap2_wd_timer_reset,
3746 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3747 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3751 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3752 .name = "wd_timer2",
3753 .class = &omap44xx_wd_timer_hwmod_class,
3754 .clkdm_name = "l4_wkup_clkdm",
3755 .mpu_irqs = omap44xx_wd_timer2_irqs,
3756 .main_clk = "wd_timer2_fck",
3759 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3760 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3761 .modulemode = MODULEMODE_SWCTRL,
3767 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3768 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3772 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3773 .name = "wd_timer3",
3774 .class = &omap44xx_wd_timer_hwmod_class,
3775 .clkdm_name = "abe_clkdm",
3776 .mpu_irqs = omap44xx_wd_timer3_irqs,
3777 .main_clk = "wd_timer3_fck",
3780 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3781 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3782 .modulemode = MODULEMODE_SWCTRL,
3792 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3794 .pa_start = 0x4a204000,
3795 .pa_end = 0x4a2040ff,
3796 .flags = ADDR_TYPE_RT
3801 /* c2c -> c2c_target_fw */
3802 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3803 .master = &omap44xx_c2c_hwmod,
3804 .slave = &omap44xx_c2c_target_fw_hwmod,
3805 .clk = "div_core_ck",
3806 .addr = omap44xx_c2c_target_fw_addrs,
3807 .user = OCP_USER_MPU,
3810 /* l4_cfg -> c2c_target_fw */
3811 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3812 .master = &omap44xx_l4_cfg_hwmod,
3813 .slave = &omap44xx_c2c_target_fw_hwmod,
3815 .user = OCP_USER_MPU | OCP_USER_SDMA,
3818 /* l3_main_1 -> dmm */
3819 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3820 .master = &omap44xx_l3_main_1_hwmod,
3821 .slave = &omap44xx_dmm_hwmod,
3823 .user = OCP_USER_SDMA,
3826 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3828 .pa_start = 0x4e000000,
3829 .pa_end = 0x4e0007ff,
3830 .flags = ADDR_TYPE_RT
3836 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3837 .master = &omap44xx_mpu_hwmod,
3838 .slave = &omap44xx_dmm_hwmod,
3840 .addr = omap44xx_dmm_addrs,
3841 .user = OCP_USER_MPU,
3844 /* c2c -> emif_fw */
3845 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3846 .master = &omap44xx_c2c_hwmod,
3847 .slave = &omap44xx_emif_fw_hwmod,
3848 .clk = "div_core_ck",
3849 .user = OCP_USER_MPU | OCP_USER_SDMA,
3852 /* dmm -> emif_fw */
3853 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3854 .master = &omap44xx_dmm_hwmod,
3855 .slave = &omap44xx_emif_fw_hwmod,
3857 .user = OCP_USER_MPU | OCP_USER_SDMA,
3860 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3862 .pa_start = 0x4a20c000,
3863 .pa_end = 0x4a20c0ff,
3864 .flags = ADDR_TYPE_RT
3869 /* l4_cfg -> emif_fw */
3870 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3871 .master = &omap44xx_l4_cfg_hwmod,
3872 .slave = &omap44xx_emif_fw_hwmod,
3874 .addr = omap44xx_emif_fw_addrs,
3875 .user = OCP_USER_MPU,
3878 /* iva -> l3_instr */
3879 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3880 .master = &omap44xx_iva_hwmod,
3881 .slave = &omap44xx_l3_instr_hwmod,
3883 .user = OCP_USER_MPU | OCP_USER_SDMA,
3886 /* l3_main_3 -> l3_instr */
3887 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3888 .master = &omap44xx_l3_main_3_hwmod,
3889 .slave = &omap44xx_l3_instr_hwmod,
3891 .user = OCP_USER_MPU | OCP_USER_SDMA,
3894 /* ocp_wp_noc -> l3_instr */
3895 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3896 .master = &omap44xx_ocp_wp_noc_hwmod,
3897 .slave = &omap44xx_l3_instr_hwmod,
3899 .user = OCP_USER_MPU | OCP_USER_SDMA,
3902 /* dsp -> l3_main_1 */
3903 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3904 .master = &omap44xx_dsp_hwmod,
3905 .slave = &omap44xx_l3_main_1_hwmod,
3907 .user = OCP_USER_MPU | OCP_USER_SDMA,
3910 /* dss -> l3_main_1 */
3911 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3912 .master = &omap44xx_dss_hwmod,
3913 .slave = &omap44xx_l3_main_1_hwmod,
3915 .user = OCP_USER_MPU | OCP_USER_SDMA,
3918 /* l3_main_2 -> l3_main_1 */
3919 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3920 .master = &omap44xx_l3_main_2_hwmod,
3921 .slave = &omap44xx_l3_main_1_hwmod,
3923 .user = OCP_USER_MPU | OCP_USER_SDMA,
3926 /* l4_cfg -> l3_main_1 */
3927 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3928 .master = &omap44xx_l4_cfg_hwmod,
3929 .slave = &omap44xx_l3_main_1_hwmod,
3931 .user = OCP_USER_MPU | OCP_USER_SDMA,
3934 /* mmc1 -> l3_main_1 */
3935 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3936 .master = &omap44xx_mmc1_hwmod,
3937 .slave = &omap44xx_l3_main_1_hwmod,
3939 .user = OCP_USER_MPU | OCP_USER_SDMA,
3942 /* mmc2 -> l3_main_1 */
3943 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3944 .master = &omap44xx_mmc2_hwmod,
3945 .slave = &omap44xx_l3_main_1_hwmod,
3947 .user = OCP_USER_MPU | OCP_USER_SDMA,
3950 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3952 .pa_start = 0x44000000,
3953 .pa_end = 0x44000fff,
3954 .flags = ADDR_TYPE_RT
3959 /* mpu -> l3_main_1 */
3960 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3961 .master = &omap44xx_mpu_hwmod,
3962 .slave = &omap44xx_l3_main_1_hwmod,
3964 .addr = omap44xx_l3_main_1_addrs,
3965 .user = OCP_USER_MPU,
3968 /* c2c_target_fw -> l3_main_2 */
3969 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
3970 .master = &omap44xx_c2c_target_fw_hwmod,
3971 .slave = &omap44xx_l3_main_2_hwmod,
3973 .user = OCP_USER_MPU | OCP_USER_SDMA,
3976 /* debugss -> l3_main_2 */
3977 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3978 .master = &omap44xx_debugss_hwmod,
3979 .slave = &omap44xx_l3_main_2_hwmod,
3980 .clk = "dbgclk_mux_ck",
3981 .user = OCP_USER_MPU | OCP_USER_SDMA,
3984 /* dma_system -> l3_main_2 */
3985 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3986 .master = &omap44xx_dma_system_hwmod,
3987 .slave = &omap44xx_l3_main_2_hwmod,
3989 .user = OCP_USER_MPU | OCP_USER_SDMA,
3992 /* fdif -> l3_main_2 */
3993 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3994 .master = &omap44xx_fdif_hwmod,
3995 .slave = &omap44xx_l3_main_2_hwmod,
3997 .user = OCP_USER_MPU | OCP_USER_SDMA,
4000 /* gpu -> l3_main_2 */
4001 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4002 .master = &omap44xx_gpu_hwmod,
4003 .slave = &omap44xx_l3_main_2_hwmod,
4005 .user = OCP_USER_MPU | OCP_USER_SDMA,
4008 /* hsi -> l3_main_2 */
4009 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4010 .master = &omap44xx_hsi_hwmod,
4011 .slave = &omap44xx_l3_main_2_hwmod,
4013 .user = OCP_USER_MPU | OCP_USER_SDMA,
4016 /* ipu -> l3_main_2 */
4017 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4018 .master = &omap44xx_ipu_hwmod,
4019 .slave = &omap44xx_l3_main_2_hwmod,
4021 .user = OCP_USER_MPU | OCP_USER_SDMA,
4024 /* iss -> l3_main_2 */
4025 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4026 .master = &omap44xx_iss_hwmod,
4027 .slave = &omap44xx_l3_main_2_hwmod,
4029 .user = OCP_USER_MPU | OCP_USER_SDMA,
4032 /* iva -> l3_main_2 */
4033 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4034 .master = &omap44xx_iva_hwmod,
4035 .slave = &omap44xx_l3_main_2_hwmod,
4037 .user = OCP_USER_MPU | OCP_USER_SDMA,
4040 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4042 .pa_start = 0x44800000,
4043 .pa_end = 0x44801fff,
4044 .flags = ADDR_TYPE_RT
4049 /* l3_main_1 -> l3_main_2 */
4050 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4051 .master = &omap44xx_l3_main_1_hwmod,
4052 .slave = &omap44xx_l3_main_2_hwmod,
4054 .addr = omap44xx_l3_main_2_addrs,
4055 .user = OCP_USER_MPU,
4058 /* l4_cfg -> l3_main_2 */
4059 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4060 .master = &omap44xx_l4_cfg_hwmod,
4061 .slave = &omap44xx_l3_main_2_hwmod,
4063 .user = OCP_USER_MPU | OCP_USER_SDMA,
4066 /* usb_host_fs -> l3_main_2 */
4067 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4068 .master = &omap44xx_usb_host_fs_hwmod,
4069 .slave = &omap44xx_l3_main_2_hwmod,
4071 .user = OCP_USER_MPU | OCP_USER_SDMA,
4074 /* usb_host_hs -> l3_main_2 */
4075 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4076 .master = &omap44xx_usb_host_hs_hwmod,
4077 .slave = &omap44xx_l3_main_2_hwmod,
4079 .user = OCP_USER_MPU | OCP_USER_SDMA,
4082 /* usb_otg_hs -> l3_main_2 */
4083 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4084 .master = &omap44xx_usb_otg_hs_hwmod,
4085 .slave = &omap44xx_l3_main_2_hwmod,
4087 .user = OCP_USER_MPU | OCP_USER_SDMA,
4090 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4092 .pa_start = 0x45000000,
4093 .pa_end = 0x45000fff,
4094 .flags = ADDR_TYPE_RT
4099 /* l3_main_1 -> l3_main_3 */
4100 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4101 .master = &omap44xx_l3_main_1_hwmod,
4102 .slave = &omap44xx_l3_main_3_hwmod,
4104 .addr = omap44xx_l3_main_3_addrs,
4105 .user = OCP_USER_MPU,
4108 /* l3_main_2 -> l3_main_3 */
4109 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4110 .master = &omap44xx_l3_main_2_hwmod,
4111 .slave = &omap44xx_l3_main_3_hwmod,
4113 .user = OCP_USER_MPU | OCP_USER_SDMA,
4116 /* l4_cfg -> l3_main_3 */
4117 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4118 .master = &omap44xx_l4_cfg_hwmod,
4119 .slave = &omap44xx_l3_main_3_hwmod,
4121 .user = OCP_USER_MPU | OCP_USER_SDMA,
4124 /* aess -> l4_abe */
4125 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4126 .master = &omap44xx_aess_hwmod,
4127 .slave = &omap44xx_l4_abe_hwmod,
4128 .clk = "ocp_abe_iclk",
4129 .user = OCP_USER_MPU | OCP_USER_SDMA,
4133 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4134 .master = &omap44xx_dsp_hwmod,
4135 .slave = &omap44xx_l4_abe_hwmod,
4136 .clk = "ocp_abe_iclk",
4137 .user = OCP_USER_MPU | OCP_USER_SDMA,
4140 /* l3_main_1 -> l4_abe */
4141 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4142 .master = &omap44xx_l3_main_1_hwmod,
4143 .slave = &omap44xx_l4_abe_hwmod,
4145 .user = OCP_USER_MPU | OCP_USER_SDMA,
4149 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4150 .master = &omap44xx_mpu_hwmod,
4151 .slave = &omap44xx_l4_abe_hwmod,
4152 .clk = "ocp_abe_iclk",
4153 .user = OCP_USER_MPU | OCP_USER_SDMA,
4156 /* l3_main_1 -> l4_cfg */
4157 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4158 .master = &omap44xx_l3_main_1_hwmod,
4159 .slave = &omap44xx_l4_cfg_hwmod,
4161 .user = OCP_USER_MPU | OCP_USER_SDMA,
4164 /* l3_main_2 -> l4_per */
4165 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4166 .master = &omap44xx_l3_main_2_hwmod,
4167 .slave = &omap44xx_l4_per_hwmod,
4169 .user = OCP_USER_MPU | OCP_USER_SDMA,
4172 /* l4_cfg -> l4_wkup */
4173 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4174 .master = &omap44xx_l4_cfg_hwmod,
4175 .slave = &omap44xx_l4_wkup_hwmod,
4177 .user = OCP_USER_MPU | OCP_USER_SDMA,
4180 /* mpu -> mpu_private */
4181 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4182 .master = &omap44xx_mpu_hwmod,
4183 .slave = &omap44xx_mpu_private_hwmod,
4185 .user = OCP_USER_MPU | OCP_USER_SDMA,
4188 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4190 .pa_start = 0x4a102000,
4191 .pa_end = 0x4a10207f,
4192 .flags = ADDR_TYPE_RT
4197 /* l4_cfg -> ocp_wp_noc */
4198 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4199 .master = &omap44xx_l4_cfg_hwmod,
4200 .slave = &omap44xx_ocp_wp_noc_hwmod,
4202 .addr = omap44xx_ocp_wp_noc_addrs,
4203 .user = OCP_USER_MPU | OCP_USER_SDMA,
4206 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4208 .pa_start = 0x401f1000,
4209 .pa_end = 0x401f13ff,
4210 .flags = ADDR_TYPE_RT
4215 /* l4_abe -> aess */
4216 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4217 .master = &omap44xx_l4_abe_hwmod,
4218 .slave = &omap44xx_aess_hwmod,
4219 .clk = "ocp_abe_iclk",
4220 .addr = omap44xx_aess_addrs,
4221 .user = OCP_USER_MPU,
4224 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4226 .pa_start = 0x490f1000,
4227 .pa_end = 0x490f13ff,
4228 .flags = ADDR_TYPE_RT
4233 /* l4_abe -> aess (dma) */
4234 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4235 .master = &omap44xx_l4_abe_hwmod,
4236 .slave = &omap44xx_aess_hwmod,
4237 .clk = "ocp_abe_iclk",
4238 .addr = omap44xx_aess_dma_addrs,
4239 .user = OCP_USER_SDMA,
4242 /* l3_main_2 -> c2c */
4243 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4244 .master = &omap44xx_l3_main_2_hwmod,
4245 .slave = &omap44xx_c2c_hwmod,
4247 .user = OCP_USER_MPU | OCP_USER_SDMA,
4250 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4252 .pa_start = 0x4a304000,
4253 .pa_end = 0x4a30401f,
4254 .flags = ADDR_TYPE_RT
4259 /* l4_wkup -> counter_32k */
4260 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4261 .master = &omap44xx_l4_wkup_hwmod,
4262 .slave = &omap44xx_counter_32k_hwmod,
4263 .clk = "l4_wkup_clk_mux_ck",
4264 .addr = omap44xx_counter_32k_addrs,
4265 .user = OCP_USER_MPU | OCP_USER_SDMA,
4268 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4270 .pa_start = 0x4a002000,
4271 .pa_end = 0x4a0027ff,
4272 .flags = ADDR_TYPE_RT
4277 /* l4_cfg -> ctrl_module_core */
4278 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4279 .master = &omap44xx_l4_cfg_hwmod,
4280 .slave = &omap44xx_ctrl_module_core_hwmod,
4282 .addr = omap44xx_ctrl_module_core_addrs,
4283 .user = OCP_USER_MPU | OCP_USER_SDMA,
4286 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4288 .pa_start = 0x4a100000,
4289 .pa_end = 0x4a1007ff,
4290 .flags = ADDR_TYPE_RT
4295 /* l4_cfg -> ctrl_module_pad_core */
4296 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4297 .master = &omap44xx_l4_cfg_hwmod,
4298 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
4300 .addr = omap44xx_ctrl_module_pad_core_addrs,
4301 .user = OCP_USER_MPU | OCP_USER_SDMA,
4304 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4306 .pa_start = 0x4a30c000,
4307 .pa_end = 0x4a30c7ff,
4308 .flags = ADDR_TYPE_RT
4313 /* l4_wkup -> ctrl_module_wkup */
4314 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4315 .master = &omap44xx_l4_wkup_hwmod,
4316 .slave = &omap44xx_ctrl_module_wkup_hwmod,
4317 .clk = "l4_wkup_clk_mux_ck",
4318 .addr = omap44xx_ctrl_module_wkup_addrs,
4319 .user = OCP_USER_MPU | OCP_USER_SDMA,
4322 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4324 .pa_start = 0x4a31e000,
4325 .pa_end = 0x4a31e7ff,
4326 .flags = ADDR_TYPE_RT
4331 /* l4_wkup -> ctrl_module_pad_wkup */
4332 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4333 .master = &omap44xx_l4_wkup_hwmod,
4334 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
4335 .clk = "l4_wkup_clk_mux_ck",
4336 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
4337 .user = OCP_USER_MPU | OCP_USER_SDMA,
4340 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4342 .pa_start = 0x54160000,
4343 .pa_end = 0x54167fff,
4344 .flags = ADDR_TYPE_RT
4349 /* l3_instr -> debugss */
4350 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4351 .master = &omap44xx_l3_instr_hwmod,
4352 .slave = &omap44xx_debugss_hwmod,
4354 .addr = omap44xx_debugss_addrs,
4355 .user = OCP_USER_MPU | OCP_USER_SDMA,
4358 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4360 .pa_start = 0x4a056000,
4361 .pa_end = 0x4a056fff,
4362 .flags = ADDR_TYPE_RT
4367 /* l4_cfg -> dma_system */
4368 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4369 .master = &omap44xx_l4_cfg_hwmod,
4370 .slave = &omap44xx_dma_system_hwmod,
4372 .addr = omap44xx_dma_system_addrs,
4373 .user = OCP_USER_MPU | OCP_USER_SDMA,
4376 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4379 .pa_start = 0x4012e000,
4380 .pa_end = 0x4012e07f,
4381 .flags = ADDR_TYPE_RT
4386 /* l4_abe -> dmic */
4387 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4388 .master = &omap44xx_l4_abe_hwmod,
4389 .slave = &omap44xx_dmic_hwmod,
4390 .clk = "ocp_abe_iclk",
4391 .addr = omap44xx_dmic_addrs,
4392 .user = OCP_USER_MPU,
4395 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4398 .pa_start = 0x4902e000,
4399 .pa_end = 0x4902e07f,
4400 .flags = ADDR_TYPE_RT
4405 /* l4_abe -> dmic (dma) */
4406 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4407 .master = &omap44xx_l4_abe_hwmod,
4408 .slave = &omap44xx_dmic_hwmod,
4409 .clk = "ocp_abe_iclk",
4410 .addr = omap44xx_dmic_dma_addrs,
4411 .user = OCP_USER_SDMA,
4415 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4416 .master = &omap44xx_dsp_hwmod,
4417 .slave = &omap44xx_iva_hwmod,
4418 .clk = "dpll_iva_m5x2_ck",
4419 .user = OCP_USER_DSP,
4423 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4424 .master = &omap44xx_dsp_hwmod,
4425 .slave = &omap44xx_sl2if_hwmod,
4426 .clk = "dpll_iva_m5x2_ck",
4427 .user = OCP_USER_DSP,
4431 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4432 .master = &omap44xx_l4_cfg_hwmod,
4433 .slave = &omap44xx_dsp_hwmod,
4435 .user = OCP_USER_MPU | OCP_USER_SDMA,
4438 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4440 .pa_start = 0x58000000,
4441 .pa_end = 0x5800007f,
4442 .flags = ADDR_TYPE_RT
4447 /* l3_main_2 -> dss */
4448 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4449 .master = &omap44xx_l3_main_2_hwmod,
4450 .slave = &omap44xx_dss_hwmod,
4452 .addr = omap44xx_dss_dma_addrs,
4453 .user = OCP_USER_SDMA,
4456 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4458 .pa_start = 0x48040000,
4459 .pa_end = 0x4804007f,
4460 .flags = ADDR_TYPE_RT
4466 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4467 .master = &omap44xx_l4_per_hwmod,
4468 .slave = &omap44xx_dss_hwmod,
4470 .addr = omap44xx_dss_addrs,
4471 .user = OCP_USER_MPU,
4474 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4476 .pa_start = 0x58001000,
4477 .pa_end = 0x58001fff,
4478 .flags = ADDR_TYPE_RT
4483 /* l3_main_2 -> dss_dispc */
4484 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4485 .master = &omap44xx_l3_main_2_hwmod,
4486 .slave = &omap44xx_dss_dispc_hwmod,
4488 .addr = omap44xx_dss_dispc_dma_addrs,
4489 .user = OCP_USER_SDMA,
4492 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4494 .pa_start = 0x48041000,
4495 .pa_end = 0x48041fff,
4496 .flags = ADDR_TYPE_RT
4501 /* l4_per -> dss_dispc */
4502 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4503 .master = &omap44xx_l4_per_hwmod,
4504 .slave = &omap44xx_dss_dispc_hwmod,
4506 .addr = omap44xx_dss_dispc_addrs,
4507 .user = OCP_USER_MPU,
4510 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4512 .pa_start = 0x58004000,
4513 .pa_end = 0x580041ff,
4514 .flags = ADDR_TYPE_RT
4519 /* l3_main_2 -> dss_dsi1 */
4520 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4521 .master = &omap44xx_l3_main_2_hwmod,
4522 .slave = &omap44xx_dss_dsi1_hwmod,
4524 .addr = omap44xx_dss_dsi1_dma_addrs,
4525 .user = OCP_USER_SDMA,
4528 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4530 .pa_start = 0x48044000,
4531 .pa_end = 0x480441ff,
4532 .flags = ADDR_TYPE_RT
4537 /* l4_per -> dss_dsi1 */
4538 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4539 .master = &omap44xx_l4_per_hwmod,
4540 .slave = &omap44xx_dss_dsi1_hwmod,
4542 .addr = omap44xx_dss_dsi1_addrs,
4543 .user = OCP_USER_MPU,
4546 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4548 .pa_start = 0x58005000,
4549 .pa_end = 0x580051ff,
4550 .flags = ADDR_TYPE_RT
4555 /* l3_main_2 -> dss_dsi2 */
4556 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4557 .master = &omap44xx_l3_main_2_hwmod,
4558 .slave = &omap44xx_dss_dsi2_hwmod,
4560 .addr = omap44xx_dss_dsi2_dma_addrs,
4561 .user = OCP_USER_SDMA,
4564 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4566 .pa_start = 0x48045000,
4567 .pa_end = 0x480451ff,
4568 .flags = ADDR_TYPE_RT
4573 /* l4_per -> dss_dsi2 */
4574 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4575 .master = &omap44xx_l4_per_hwmod,
4576 .slave = &omap44xx_dss_dsi2_hwmod,
4578 .addr = omap44xx_dss_dsi2_addrs,
4579 .user = OCP_USER_MPU,
4582 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4584 .pa_start = 0x58006000,
4585 .pa_end = 0x58006fff,
4586 .flags = ADDR_TYPE_RT
4591 /* l3_main_2 -> dss_hdmi */
4592 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4593 .master = &omap44xx_l3_main_2_hwmod,
4594 .slave = &omap44xx_dss_hdmi_hwmod,
4596 .addr = omap44xx_dss_hdmi_dma_addrs,
4597 .user = OCP_USER_SDMA,
4600 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4602 .pa_start = 0x48046000,
4603 .pa_end = 0x48046fff,
4604 .flags = ADDR_TYPE_RT
4609 /* l4_per -> dss_hdmi */
4610 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4611 .master = &omap44xx_l4_per_hwmod,
4612 .slave = &omap44xx_dss_hdmi_hwmod,
4614 .addr = omap44xx_dss_hdmi_addrs,
4615 .user = OCP_USER_MPU,
4618 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4620 .pa_start = 0x58002000,
4621 .pa_end = 0x580020ff,
4622 .flags = ADDR_TYPE_RT
4627 /* l3_main_2 -> dss_rfbi */
4628 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4629 .master = &omap44xx_l3_main_2_hwmod,
4630 .slave = &omap44xx_dss_rfbi_hwmod,
4632 .addr = omap44xx_dss_rfbi_dma_addrs,
4633 .user = OCP_USER_SDMA,
4636 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4638 .pa_start = 0x48042000,
4639 .pa_end = 0x480420ff,
4640 .flags = ADDR_TYPE_RT
4645 /* l4_per -> dss_rfbi */
4646 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4647 .master = &omap44xx_l4_per_hwmod,
4648 .slave = &omap44xx_dss_rfbi_hwmod,
4650 .addr = omap44xx_dss_rfbi_addrs,
4651 .user = OCP_USER_MPU,
4654 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4656 .pa_start = 0x58003000,
4657 .pa_end = 0x580030ff,
4658 .flags = ADDR_TYPE_RT
4663 /* l3_main_2 -> dss_venc */
4664 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4665 .master = &omap44xx_l3_main_2_hwmod,
4666 .slave = &omap44xx_dss_venc_hwmod,
4668 .addr = omap44xx_dss_venc_dma_addrs,
4669 .user = OCP_USER_SDMA,
4672 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4674 .pa_start = 0x48043000,
4675 .pa_end = 0x480430ff,
4676 .flags = ADDR_TYPE_RT
4681 /* l4_per -> dss_venc */
4682 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4683 .master = &omap44xx_l4_per_hwmod,
4684 .slave = &omap44xx_dss_venc_hwmod,
4686 .addr = omap44xx_dss_venc_addrs,
4687 .user = OCP_USER_MPU,
4690 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4692 .pa_start = 0x48078000,
4693 .pa_end = 0x48078fff,
4694 .flags = ADDR_TYPE_RT
4700 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4701 .master = &omap44xx_l4_per_hwmod,
4702 .slave = &omap44xx_elm_hwmod,
4704 .addr = omap44xx_elm_addrs,
4705 .user = OCP_USER_MPU | OCP_USER_SDMA,
4708 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4710 .pa_start = 0x4c000000,
4711 .pa_end = 0x4c0000ff,
4712 .flags = ADDR_TYPE_RT
4717 /* emif_fw -> emif1 */
4718 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4719 .master = &omap44xx_emif_fw_hwmod,
4720 .slave = &omap44xx_emif1_hwmod,
4722 .addr = omap44xx_emif1_addrs,
4723 .user = OCP_USER_MPU | OCP_USER_SDMA,
4726 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4728 .pa_start = 0x4d000000,
4729 .pa_end = 0x4d0000ff,
4730 .flags = ADDR_TYPE_RT
4735 /* emif_fw -> emif2 */
4736 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4737 .master = &omap44xx_emif_fw_hwmod,
4738 .slave = &omap44xx_emif2_hwmod,
4740 .addr = omap44xx_emif2_addrs,
4741 .user = OCP_USER_MPU | OCP_USER_SDMA,
4744 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4746 .pa_start = 0x4a10a000,
4747 .pa_end = 0x4a10a1ff,
4748 .flags = ADDR_TYPE_RT
4753 /* l4_cfg -> fdif */
4754 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4755 .master = &omap44xx_l4_cfg_hwmod,
4756 .slave = &omap44xx_fdif_hwmod,
4758 .addr = omap44xx_fdif_addrs,
4759 .user = OCP_USER_MPU | OCP_USER_SDMA,
4762 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4764 .pa_start = 0x4a310000,
4765 .pa_end = 0x4a3101ff,
4766 .flags = ADDR_TYPE_RT
4771 /* l4_wkup -> gpio1 */
4772 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4773 .master = &omap44xx_l4_wkup_hwmod,
4774 .slave = &omap44xx_gpio1_hwmod,
4775 .clk = "l4_wkup_clk_mux_ck",
4776 .addr = omap44xx_gpio1_addrs,
4777 .user = OCP_USER_MPU | OCP_USER_SDMA,
4780 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4782 .pa_start = 0x48055000,
4783 .pa_end = 0x480551ff,
4784 .flags = ADDR_TYPE_RT
4789 /* l4_per -> gpio2 */
4790 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4791 .master = &omap44xx_l4_per_hwmod,
4792 .slave = &omap44xx_gpio2_hwmod,
4794 .addr = omap44xx_gpio2_addrs,
4795 .user = OCP_USER_MPU | OCP_USER_SDMA,
4798 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4800 .pa_start = 0x48057000,
4801 .pa_end = 0x480571ff,
4802 .flags = ADDR_TYPE_RT
4807 /* l4_per -> gpio3 */
4808 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4809 .master = &omap44xx_l4_per_hwmod,
4810 .slave = &omap44xx_gpio3_hwmod,
4812 .addr = omap44xx_gpio3_addrs,
4813 .user = OCP_USER_MPU | OCP_USER_SDMA,
4816 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4818 .pa_start = 0x48059000,
4819 .pa_end = 0x480591ff,
4820 .flags = ADDR_TYPE_RT
4825 /* l4_per -> gpio4 */
4826 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4827 .master = &omap44xx_l4_per_hwmod,
4828 .slave = &omap44xx_gpio4_hwmod,
4830 .addr = omap44xx_gpio4_addrs,
4831 .user = OCP_USER_MPU | OCP_USER_SDMA,
4834 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4836 .pa_start = 0x4805b000,
4837 .pa_end = 0x4805b1ff,
4838 .flags = ADDR_TYPE_RT
4843 /* l4_per -> gpio5 */
4844 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4845 .master = &omap44xx_l4_per_hwmod,
4846 .slave = &omap44xx_gpio5_hwmod,
4848 .addr = omap44xx_gpio5_addrs,
4849 .user = OCP_USER_MPU | OCP_USER_SDMA,
4852 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4854 .pa_start = 0x4805d000,
4855 .pa_end = 0x4805d1ff,
4856 .flags = ADDR_TYPE_RT
4861 /* l4_per -> gpio6 */
4862 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4863 .master = &omap44xx_l4_per_hwmod,
4864 .slave = &omap44xx_gpio6_hwmod,
4866 .addr = omap44xx_gpio6_addrs,
4867 .user = OCP_USER_MPU | OCP_USER_SDMA,
4870 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4872 .pa_start = 0x50000000,
4873 .pa_end = 0x500003ff,
4874 .flags = ADDR_TYPE_RT
4879 /* l3_main_2 -> gpmc */
4880 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4881 .master = &omap44xx_l3_main_2_hwmod,
4882 .slave = &omap44xx_gpmc_hwmod,
4884 .addr = omap44xx_gpmc_addrs,
4885 .user = OCP_USER_MPU | OCP_USER_SDMA,
4888 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4890 .pa_start = 0x56000000,
4891 .pa_end = 0x5600ffff,
4892 .flags = ADDR_TYPE_RT
4897 /* l3_main_2 -> gpu */
4898 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4899 .master = &omap44xx_l3_main_2_hwmod,
4900 .slave = &omap44xx_gpu_hwmod,
4902 .addr = omap44xx_gpu_addrs,
4903 .user = OCP_USER_MPU | OCP_USER_SDMA,
4906 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4908 .pa_start = 0x480b2000,
4909 .pa_end = 0x480b201f,
4910 .flags = ADDR_TYPE_RT
4915 /* l4_per -> hdq1w */
4916 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4917 .master = &omap44xx_l4_per_hwmod,
4918 .slave = &omap44xx_hdq1w_hwmod,
4920 .addr = omap44xx_hdq1w_addrs,
4921 .user = OCP_USER_MPU | OCP_USER_SDMA,
4924 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4926 .pa_start = 0x4a058000,
4927 .pa_end = 0x4a05bfff,
4928 .flags = ADDR_TYPE_RT
4934 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4935 .master = &omap44xx_l4_cfg_hwmod,
4936 .slave = &omap44xx_hsi_hwmod,
4938 .addr = omap44xx_hsi_addrs,
4939 .user = OCP_USER_MPU | OCP_USER_SDMA,
4942 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4944 .pa_start = 0x48070000,
4945 .pa_end = 0x480700ff,
4946 .flags = ADDR_TYPE_RT
4951 /* l4_per -> i2c1 */
4952 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4953 .master = &omap44xx_l4_per_hwmod,
4954 .slave = &omap44xx_i2c1_hwmod,
4956 .addr = omap44xx_i2c1_addrs,
4957 .user = OCP_USER_MPU | OCP_USER_SDMA,
4960 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4962 .pa_start = 0x48072000,
4963 .pa_end = 0x480720ff,
4964 .flags = ADDR_TYPE_RT
4969 /* l4_per -> i2c2 */
4970 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4971 .master = &omap44xx_l4_per_hwmod,
4972 .slave = &omap44xx_i2c2_hwmod,
4974 .addr = omap44xx_i2c2_addrs,
4975 .user = OCP_USER_MPU | OCP_USER_SDMA,
4978 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
4980 .pa_start = 0x48060000,
4981 .pa_end = 0x480600ff,
4982 .flags = ADDR_TYPE_RT
4987 /* l4_per -> i2c3 */
4988 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4989 .master = &omap44xx_l4_per_hwmod,
4990 .slave = &omap44xx_i2c3_hwmod,
4992 .addr = omap44xx_i2c3_addrs,
4993 .user = OCP_USER_MPU | OCP_USER_SDMA,
4996 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
4998 .pa_start = 0x48350000,
4999 .pa_end = 0x483500ff,
5000 .flags = ADDR_TYPE_RT
5005 /* l4_per -> i2c4 */
5006 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5007 .master = &omap44xx_l4_per_hwmod,
5008 .slave = &omap44xx_i2c4_hwmod,
5010 .addr = omap44xx_i2c4_addrs,
5011 .user = OCP_USER_MPU | OCP_USER_SDMA,
5014 /* l3_main_2 -> ipu */
5015 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5016 .master = &omap44xx_l3_main_2_hwmod,
5017 .slave = &omap44xx_ipu_hwmod,
5019 .user = OCP_USER_MPU | OCP_USER_SDMA,
5022 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5024 .pa_start = 0x52000000,
5025 .pa_end = 0x520000ff,
5026 .flags = ADDR_TYPE_RT
5031 /* l3_main_2 -> iss */
5032 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5033 .master = &omap44xx_l3_main_2_hwmod,
5034 .slave = &omap44xx_iss_hwmod,
5036 .addr = omap44xx_iss_addrs,
5037 .user = OCP_USER_MPU | OCP_USER_SDMA,
5041 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5042 .master = &omap44xx_iva_hwmod,
5043 .slave = &omap44xx_sl2if_hwmod,
5044 .clk = "dpll_iva_m5x2_ck",
5045 .user = OCP_USER_IVA,
5048 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5050 .pa_start = 0x5a000000,
5051 .pa_end = 0x5a07ffff,
5052 .flags = ADDR_TYPE_RT
5057 /* l3_main_2 -> iva */
5058 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5059 .master = &omap44xx_l3_main_2_hwmod,
5060 .slave = &omap44xx_iva_hwmod,
5062 .addr = omap44xx_iva_addrs,
5063 .user = OCP_USER_MPU,
5066 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5068 .pa_start = 0x4a31c000,
5069 .pa_end = 0x4a31c07f,
5070 .flags = ADDR_TYPE_RT
5075 /* l4_wkup -> kbd */
5076 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5077 .master = &omap44xx_l4_wkup_hwmod,
5078 .slave = &omap44xx_kbd_hwmod,
5079 .clk = "l4_wkup_clk_mux_ck",
5080 .addr = omap44xx_kbd_addrs,
5081 .user = OCP_USER_MPU | OCP_USER_SDMA,
5084 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5086 .pa_start = 0x4a0f4000,
5087 .pa_end = 0x4a0f41ff,
5088 .flags = ADDR_TYPE_RT
5093 /* l4_cfg -> mailbox */
5094 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5095 .master = &omap44xx_l4_cfg_hwmod,
5096 .slave = &omap44xx_mailbox_hwmod,
5098 .addr = omap44xx_mailbox_addrs,
5099 .user = OCP_USER_MPU | OCP_USER_SDMA,
5102 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5104 .pa_start = 0x40128000,
5105 .pa_end = 0x401283ff,
5106 .flags = ADDR_TYPE_RT
5111 /* l4_abe -> mcasp */
5112 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5113 .master = &omap44xx_l4_abe_hwmod,
5114 .slave = &omap44xx_mcasp_hwmod,
5115 .clk = "ocp_abe_iclk",
5116 .addr = omap44xx_mcasp_addrs,
5117 .user = OCP_USER_MPU,
5120 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5122 .pa_start = 0x49028000,
5123 .pa_end = 0x490283ff,
5124 .flags = ADDR_TYPE_RT
5129 /* l4_abe -> mcasp (dma) */
5130 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5131 .master = &omap44xx_l4_abe_hwmod,
5132 .slave = &omap44xx_mcasp_hwmod,
5133 .clk = "ocp_abe_iclk",
5134 .addr = omap44xx_mcasp_dma_addrs,
5135 .user = OCP_USER_SDMA,
5138 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5141 .pa_start = 0x40122000,
5142 .pa_end = 0x401220ff,
5143 .flags = ADDR_TYPE_RT
5148 /* l4_abe -> mcbsp1 */
5149 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5150 .master = &omap44xx_l4_abe_hwmod,
5151 .slave = &omap44xx_mcbsp1_hwmod,
5152 .clk = "ocp_abe_iclk",
5153 .addr = omap44xx_mcbsp1_addrs,
5154 .user = OCP_USER_MPU,
5157 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5160 .pa_start = 0x49022000,
5161 .pa_end = 0x490220ff,
5162 .flags = ADDR_TYPE_RT
5167 /* l4_abe -> mcbsp1 (dma) */
5168 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5169 .master = &omap44xx_l4_abe_hwmod,
5170 .slave = &omap44xx_mcbsp1_hwmod,
5171 .clk = "ocp_abe_iclk",
5172 .addr = omap44xx_mcbsp1_dma_addrs,
5173 .user = OCP_USER_SDMA,
5176 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5179 .pa_start = 0x40124000,
5180 .pa_end = 0x401240ff,
5181 .flags = ADDR_TYPE_RT
5186 /* l4_abe -> mcbsp2 */
5187 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5188 .master = &omap44xx_l4_abe_hwmod,
5189 .slave = &omap44xx_mcbsp2_hwmod,
5190 .clk = "ocp_abe_iclk",
5191 .addr = omap44xx_mcbsp2_addrs,
5192 .user = OCP_USER_MPU,
5195 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5198 .pa_start = 0x49024000,
5199 .pa_end = 0x490240ff,
5200 .flags = ADDR_TYPE_RT
5205 /* l4_abe -> mcbsp2 (dma) */
5206 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5207 .master = &omap44xx_l4_abe_hwmod,
5208 .slave = &omap44xx_mcbsp2_hwmod,
5209 .clk = "ocp_abe_iclk",
5210 .addr = omap44xx_mcbsp2_dma_addrs,
5211 .user = OCP_USER_SDMA,
5214 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5217 .pa_start = 0x40126000,
5218 .pa_end = 0x401260ff,
5219 .flags = ADDR_TYPE_RT
5224 /* l4_abe -> mcbsp3 */
5225 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5226 .master = &omap44xx_l4_abe_hwmod,
5227 .slave = &omap44xx_mcbsp3_hwmod,
5228 .clk = "ocp_abe_iclk",
5229 .addr = omap44xx_mcbsp3_addrs,
5230 .user = OCP_USER_MPU,
5233 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5236 .pa_start = 0x49026000,
5237 .pa_end = 0x490260ff,
5238 .flags = ADDR_TYPE_RT
5243 /* l4_abe -> mcbsp3 (dma) */
5244 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5245 .master = &omap44xx_l4_abe_hwmod,
5246 .slave = &omap44xx_mcbsp3_hwmod,
5247 .clk = "ocp_abe_iclk",
5248 .addr = omap44xx_mcbsp3_dma_addrs,
5249 .user = OCP_USER_SDMA,
5252 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5254 .pa_start = 0x48096000,
5255 .pa_end = 0x480960ff,
5256 .flags = ADDR_TYPE_RT
5261 /* l4_per -> mcbsp4 */
5262 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5263 .master = &omap44xx_l4_per_hwmod,
5264 .slave = &omap44xx_mcbsp4_hwmod,
5266 .addr = omap44xx_mcbsp4_addrs,
5267 .user = OCP_USER_MPU | OCP_USER_SDMA,
5270 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5273 .pa_start = 0x40132000,
5274 .pa_end = 0x4013207f,
5275 .flags = ADDR_TYPE_RT
5280 /* l4_abe -> mcpdm */
5281 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5282 .master = &omap44xx_l4_abe_hwmod,
5283 .slave = &omap44xx_mcpdm_hwmod,
5284 .clk = "ocp_abe_iclk",
5285 .addr = omap44xx_mcpdm_addrs,
5286 .user = OCP_USER_MPU,
5289 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5292 .pa_start = 0x49032000,
5293 .pa_end = 0x4903207f,
5294 .flags = ADDR_TYPE_RT
5299 /* l4_abe -> mcpdm (dma) */
5300 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5301 .master = &omap44xx_l4_abe_hwmod,
5302 .slave = &omap44xx_mcpdm_hwmod,
5303 .clk = "ocp_abe_iclk",
5304 .addr = omap44xx_mcpdm_dma_addrs,
5305 .user = OCP_USER_SDMA,
5308 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5310 .pa_start = 0x48098000,
5311 .pa_end = 0x480981ff,
5312 .flags = ADDR_TYPE_RT
5317 /* l4_per -> mcspi1 */
5318 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5319 .master = &omap44xx_l4_per_hwmod,
5320 .slave = &omap44xx_mcspi1_hwmod,
5322 .addr = omap44xx_mcspi1_addrs,
5323 .user = OCP_USER_MPU | OCP_USER_SDMA,
5326 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5328 .pa_start = 0x4809a000,
5329 .pa_end = 0x4809a1ff,
5330 .flags = ADDR_TYPE_RT
5335 /* l4_per -> mcspi2 */
5336 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5337 .master = &omap44xx_l4_per_hwmod,
5338 .slave = &omap44xx_mcspi2_hwmod,
5340 .addr = omap44xx_mcspi2_addrs,
5341 .user = OCP_USER_MPU | OCP_USER_SDMA,
5344 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5346 .pa_start = 0x480b8000,
5347 .pa_end = 0x480b81ff,
5348 .flags = ADDR_TYPE_RT
5353 /* l4_per -> mcspi3 */
5354 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5355 .master = &omap44xx_l4_per_hwmod,
5356 .slave = &omap44xx_mcspi3_hwmod,
5358 .addr = omap44xx_mcspi3_addrs,
5359 .user = OCP_USER_MPU | OCP_USER_SDMA,
5362 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5364 .pa_start = 0x480ba000,
5365 .pa_end = 0x480ba1ff,
5366 .flags = ADDR_TYPE_RT
5371 /* l4_per -> mcspi4 */
5372 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5373 .master = &omap44xx_l4_per_hwmod,
5374 .slave = &omap44xx_mcspi4_hwmod,
5376 .addr = omap44xx_mcspi4_addrs,
5377 .user = OCP_USER_MPU | OCP_USER_SDMA,
5380 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5382 .pa_start = 0x4809c000,
5383 .pa_end = 0x4809c3ff,
5384 .flags = ADDR_TYPE_RT
5389 /* l4_per -> mmc1 */
5390 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5391 .master = &omap44xx_l4_per_hwmod,
5392 .slave = &omap44xx_mmc1_hwmod,
5394 .addr = omap44xx_mmc1_addrs,
5395 .user = OCP_USER_MPU | OCP_USER_SDMA,
5398 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5400 .pa_start = 0x480b4000,
5401 .pa_end = 0x480b43ff,
5402 .flags = ADDR_TYPE_RT
5407 /* l4_per -> mmc2 */
5408 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5409 .master = &omap44xx_l4_per_hwmod,
5410 .slave = &omap44xx_mmc2_hwmod,
5412 .addr = omap44xx_mmc2_addrs,
5413 .user = OCP_USER_MPU | OCP_USER_SDMA,
5416 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5418 .pa_start = 0x480ad000,
5419 .pa_end = 0x480ad3ff,
5420 .flags = ADDR_TYPE_RT
5425 /* l4_per -> mmc3 */
5426 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5427 .master = &omap44xx_l4_per_hwmod,
5428 .slave = &omap44xx_mmc3_hwmod,
5430 .addr = omap44xx_mmc3_addrs,
5431 .user = OCP_USER_MPU | OCP_USER_SDMA,
5434 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5436 .pa_start = 0x480d1000,
5437 .pa_end = 0x480d13ff,
5438 .flags = ADDR_TYPE_RT
5443 /* l4_per -> mmc4 */
5444 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5445 .master = &omap44xx_l4_per_hwmod,
5446 .slave = &omap44xx_mmc4_hwmod,
5448 .addr = omap44xx_mmc4_addrs,
5449 .user = OCP_USER_MPU | OCP_USER_SDMA,
5452 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5454 .pa_start = 0x480d5000,
5455 .pa_end = 0x480d53ff,
5456 .flags = ADDR_TYPE_RT
5461 /* l4_per -> mmc5 */
5462 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5463 .master = &omap44xx_l4_per_hwmod,
5464 .slave = &omap44xx_mmc5_hwmod,
5466 .addr = omap44xx_mmc5_addrs,
5467 .user = OCP_USER_MPU | OCP_USER_SDMA,
5470 /* l3_main_2 -> ocmc_ram */
5471 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5472 .master = &omap44xx_l3_main_2_hwmod,
5473 .slave = &omap44xx_ocmc_ram_hwmod,
5475 .user = OCP_USER_MPU | OCP_USER_SDMA,
5478 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5480 .pa_start = 0x4a0ad000,
5481 .pa_end = 0x4a0ad01f,
5482 .flags = ADDR_TYPE_RT
5487 /* l4_cfg -> ocp2scp_usb_phy */
5488 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5489 .master = &omap44xx_l4_cfg_hwmod,
5490 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
5492 .addr = omap44xx_ocp2scp_usb_phy_addrs,
5493 .user = OCP_USER_MPU | OCP_USER_SDMA,
5496 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5498 .pa_start = 0x48243000,
5499 .pa_end = 0x48243fff,
5500 .flags = ADDR_TYPE_RT
5505 /* mpu_private -> prcm_mpu */
5506 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5507 .master = &omap44xx_mpu_private_hwmod,
5508 .slave = &omap44xx_prcm_mpu_hwmod,
5510 .addr = omap44xx_prcm_mpu_addrs,
5511 .user = OCP_USER_MPU | OCP_USER_SDMA,
5514 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5516 .pa_start = 0x4a004000,
5517 .pa_end = 0x4a004fff,
5518 .flags = ADDR_TYPE_RT
5523 /* l4_wkup -> cm_core_aon */
5524 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5525 .master = &omap44xx_l4_wkup_hwmod,
5526 .slave = &omap44xx_cm_core_aon_hwmod,
5527 .clk = "l4_wkup_clk_mux_ck",
5528 .addr = omap44xx_cm_core_aon_addrs,
5529 .user = OCP_USER_MPU | OCP_USER_SDMA,
5532 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5534 .pa_start = 0x4a008000,
5535 .pa_end = 0x4a009fff,
5536 .flags = ADDR_TYPE_RT
5541 /* l4_cfg -> cm_core */
5542 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5543 .master = &omap44xx_l4_cfg_hwmod,
5544 .slave = &omap44xx_cm_core_hwmod,
5546 .addr = omap44xx_cm_core_addrs,
5547 .user = OCP_USER_MPU | OCP_USER_SDMA,
5550 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5552 .pa_start = 0x4a306000,
5553 .pa_end = 0x4a307fff,
5554 .flags = ADDR_TYPE_RT
5559 /* l4_wkup -> prm */
5560 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5561 .master = &omap44xx_l4_wkup_hwmod,
5562 .slave = &omap44xx_prm_hwmod,
5563 .clk = "l4_wkup_clk_mux_ck",
5564 .addr = omap44xx_prm_addrs,
5565 .user = OCP_USER_MPU | OCP_USER_SDMA,
5568 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5570 .pa_start = 0x4a30a000,
5571 .pa_end = 0x4a30a7ff,
5572 .flags = ADDR_TYPE_RT
5577 /* l4_wkup -> scrm */
5578 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5579 .master = &omap44xx_l4_wkup_hwmod,
5580 .slave = &omap44xx_scrm_hwmod,
5581 .clk = "l4_wkup_clk_mux_ck",
5582 .addr = omap44xx_scrm_addrs,
5583 .user = OCP_USER_MPU | OCP_USER_SDMA,
5586 /* l3_main_2 -> sl2if */
5587 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5588 .master = &omap44xx_l3_main_2_hwmod,
5589 .slave = &omap44xx_sl2if_hwmod,
5591 .user = OCP_USER_MPU | OCP_USER_SDMA,
5594 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5596 .pa_start = 0x4012c000,
5597 .pa_end = 0x4012c3ff,
5598 .flags = ADDR_TYPE_RT
5603 /* l4_abe -> slimbus1 */
5604 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5605 .master = &omap44xx_l4_abe_hwmod,
5606 .slave = &omap44xx_slimbus1_hwmod,
5607 .clk = "ocp_abe_iclk",
5608 .addr = omap44xx_slimbus1_addrs,
5609 .user = OCP_USER_MPU,
5612 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5614 .pa_start = 0x4902c000,
5615 .pa_end = 0x4902c3ff,
5616 .flags = ADDR_TYPE_RT
5621 /* l4_abe -> slimbus1 (dma) */
5622 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5623 .master = &omap44xx_l4_abe_hwmod,
5624 .slave = &omap44xx_slimbus1_hwmod,
5625 .clk = "ocp_abe_iclk",
5626 .addr = omap44xx_slimbus1_dma_addrs,
5627 .user = OCP_USER_SDMA,
5630 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5632 .pa_start = 0x48076000,
5633 .pa_end = 0x480763ff,
5634 .flags = ADDR_TYPE_RT
5639 /* l4_per -> slimbus2 */
5640 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5641 .master = &omap44xx_l4_per_hwmod,
5642 .slave = &omap44xx_slimbus2_hwmod,
5644 .addr = omap44xx_slimbus2_addrs,
5645 .user = OCP_USER_MPU | OCP_USER_SDMA,
5648 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5650 .pa_start = 0x4a0dd000,
5651 .pa_end = 0x4a0dd03f,
5652 .flags = ADDR_TYPE_RT
5657 /* l4_cfg -> smartreflex_core */
5658 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5659 .master = &omap44xx_l4_cfg_hwmod,
5660 .slave = &omap44xx_smartreflex_core_hwmod,
5662 .addr = omap44xx_smartreflex_core_addrs,
5663 .user = OCP_USER_MPU | OCP_USER_SDMA,
5666 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5668 .pa_start = 0x4a0db000,
5669 .pa_end = 0x4a0db03f,
5670 .flags = ADDR_TYPE_RT
5675 /* l4_cfg -> smartreflex_iva */
5676 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5677 .master = &omap44xx_l4_cfg_hwmod,
5678 .slave = &omap44xx_smartreflex_iva_hwmod,
5680 .addr = omap44xx_smartreflex_iva_addrs,
5681 .user = OCP_USER_MPU | OCP_USER_SDMA,
5684 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5686 .pa_start = 0x4a0d9000,
5687 .pa_end = 0x4a0d903f,
5688 .flags = ADDR_TYPE_RT
5693 /* l4_cfg -> smartreflex_mpu */
5694 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5695 .master = &omap44xx_l4_cfg_hwmod,
5696 .slave = &omap44xx_smartreflex_mpu_hwmod,
5698 .addr = omap44xx_smartreflex_mpu_addrs,
5699 .user = OCP_USER_MPU | OCP_USER_SDMA,
5702 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5704 .pa_start = 0x4a0f6000,
5705 .pa_end = 0x4a0f6fff,
5706 .flags = ADDR_TYPE_RT
5711 /* l4_cfg -> spinlock */
5712 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5713 .master = &omap44xx_l4_cfg_hwmod,
5714 .slave = &omap44xx_spinlock_hwmod,
5716 .addr = omap44xx_spinlock_addrs,
5717 .user = OCP_USER_MPU | OCP_USER_SDMA,
5720 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5722 .pa_start = 0x4a318000,
5723 .pa_end = 0x4a31807f,
5724 .flags = ADDR_TYPE_RT
5729 /* l4_wkup -> timer1 */
5730 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5731 .master = &omap44xx_l4_wkup_hwmod,
5732 .slave = &omap44xx_timer1_hwmod,
5733 .clk = "l4_wkup_clk_mux_ck",
5734 .addr = omap44xx_timer1_addrs,
5735 .user = OCP_USER_MPU | OCP_USER_SDMA,
5738 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5740 .pa_start = 0x48032000,
5741 .pa_end = 0x4803207f,
5742 .flags = ADDR_TYPE_RT
5747 /* l4_per -> timer2 */
5748 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5749 .master = &omap44xx_l4_per_hwmod,
5750 .slave = &omap44xx_timer2_hwmod,
5752 .addr = omap44xx_timer2_addrs,
5753 .user = OCP_USER_MPU | OCP_USER_SDMA,
5756 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5758 .pa_start = 0x48034000,
5759 .pa_end = 0x4803407f,
5760 .flags = ADDR_TYPE_RT
5765 /* l4_per -> timer3 */
5766 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5767 .master = &omap44xx_l4_per_hwmod,
5768 .slave = &omap44xx_timer3_hwmod,
5770 .addr = omap44xx_timer3_addrs,
5771 .user = OCP_USER_MPU | OCP_USER_SDMA,
5774 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5776 .pa_start = 0x48036000,
5777 .pa_end = 0x4803607f,
5778 .flags = ADDR_TYPE_RT
5783 /* l4_per -> timer4 */
5784 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5785 .master = &omap44xx_l4_per_hwmod,
5786 .slave = &omap44xx_timer4_hwmod,
5788 .addr = omap44xx_timer4_addrs,
5789 .user = OCP_USER_MPU | OCP_USER_SDMA,
5792 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5794 .pa_start = 0x40138000,
5795 .pa_end = 0x4013807f,
5796 .flags = ADDR_TYPE_RT
5801 /* l4_abe -> timer5 */
5802 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5803 .master = &omap44xx_l4_abe_hwmod,
5804 .slave = &omap44xx_timer5_hwmod,
5805 .clk = "ocp_abe_iclk",
5806 .addr = omap44xx_timer5_addrs,
5807 .user = OCP_USER_MPU,
5810 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5812 .pa_start = 0x49038000,
5813 .pa_end = 0x4903807f,
5814 .flags = ADDR_TYPE_RT
5819 /* l4_abe -> timer5 (dma) */
5820 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5821 .master = &omap44xx_l4_abe_hwmod,
5822 .slave = &omap44xx_timer5_hwmod,
5823 .clk = "ocp_abe_iclk",
5824 .addr = omap44xx_timer5_dma_addrs,
5825 .user = OCP_USER_SDMA,
5828 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5830 .pa_start = 0x4013a000,
5831 .pa_end = 0x4013a07f,
5832 .flags = ADDR_TYPE_RT
5837 /* l4_abe -> timer6 */
5838 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5839 .master = &omap44xx_l4_abe_hwmod,
5840 .slave = &omap44xx_timer6_hwmod,
5841 .clk = "ocp_abe_iclk",
5842 .addr = omap44xx_timer6_addrs,
5843 .user = OCP_USER_MPU,
5846 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5848 .pa_start = 0x4903a000,
5849 .pa_end = 0x4903a07f,
5850 .flags = ADDR_TYPE_RT
5855 /* l4_abe -> timer6 (dma) */
5856 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5857 .master = &omap44xx_l4_abe_hwmod,
5858 .slave = &omap44xx_timer6_hwmod,
5859 .clk = "ocp_abe_iclk",
5860 .addr = omap44xx_timer6_dma_addrs,
5861 .user = OCP_USER_SDMA,
5864 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5866 .pa_start = 0x4013c000,
5867 .pa_end = 0x4013c07f,
5868 .flags = ADDR_TYPE_RT
5873 /* l4_abe -> timer7 */
5874 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5875 .master = &omap44xx_l4_abe_hwmod,
5876 .slave = &omap44xx_timer7_hwmod,
5877 .clk = "ocp_abe_iclk",
5878 .addr = omap44xx_timer7_addrs,
5879 .user = OCP_USER_MPU,
5882 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5884 .pa_start = 0x4903c000,
5885 .pa_end = 0x4903c07f,
5886 .flags = ADDR_TYPE_RT
5891 /* l4_abe -> timer7 (dma) */
5892 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5893 .master = &omap44xx_l4_abe_hwmod,
5894 .slave = &omap44xx_timer7_hwmod,
5895 .clk = "ocp_abe_iclk",
5896 .addr = omap44xx_timer7_dma_addrs,
5897 .user = OCP_USER_SDMA,
5900 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5902 .pa_start = 0x4013e000,
5903 .pa_end = 0x4013e07f,
5904 .flags = ADDR_TYPE_RT
5909 /* l4_abe -> timer8 */
5910 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5911 .master = &omap44xx_l4_abe_hwmod,
5912 .slave = &omap44xx_timer8_hwmod,
5913 .clk = "ocp_abe_iclk",
5914 .addr = omap44xx_timer8_addrs,
5915 .user = OCP_USER_MPU,
5918 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5920 .pa_start = 0x4903e000,
5921 .pa_end = 0x4903e07f,
5922 .flags = ADDR_TYPE_RT
5927 /* l4_abe -> timer8 (dma) */
5928 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5929 .master = &omap44xx_l4_abe_hwmod,
5930 .slave = &omap44xx_timer8_hwmod,
5931 .clk = "ocp_abe_iclk",
5932 .addr = omap44xx_timer8_dma_addrs,
5933 .user = OCP_USER_SDMA,
5936 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5938 .pa_start = 0x4803e000,
5939 .pa_end = 0x4803e07f,
5940 .flags = ADDR_TYPE_RT
5945 /* l4_per -> timer9 */
5946 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5947 .master = &omap44xx_l4_per_hwmod,
5948 .slave = &omap44xx_timer9_hwmod,
5950 .addr = omap44xx_timer9_addrs,
5951 .user = OCP_USER_MPU | OCP_USER_SDMA,
5954 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5956 .pa_start = 0x48086000,
5957 .pa_end = 0x4808607f,
5958 .flags = ADDR_TYPE_RT
5963 /* l4_per -> timer10 */
5964 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
5965 .master = &omap44xx_l4_per_hwmod,
5966 .slave = &omap44xx_timer10_hwmod,
5968 .addr = omap44xx_timer10_addrs,
5969 .user = OCP_USER_MPU | OCP_USER_SDMA,
5972 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
5974 .pa_start = 0x48088000,
5975 .pa_end = 0x4808807f,
5976 .flags = ADDR_TYPE_RT
5981 /* l4_per -> timer11 */
5982 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
5983 .master = &omap44xx_l4_per_hwmod,
5984 .slave = &omap44xx_timer11_hwmod,
5986 .addr = omap44xx_timer11_addrs,
5987 .user = OCP_USER_MPU | OCP_USER_SDMA,
5990 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
5992 .pa_start = 0x4806a000,
5993 .pa_end = 0x4806a0ff,
5994 .flags = ADDR_TYPE_RT
5999 /* l4_per -> uart1 */
6000 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6001 .master = &omap44xx_l4_per_hwmod,
6002 .slave = &omap44xx_uart1_hwmod,
6004 .addr = omap44xx_uart1_addrs,
6005 .user = OCP_USER_MPU | OCP_USER_SDMA,
6008 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6010 .pa_start = 0x4806c000,
6011 .pa_end = 0x4806c0ff,
6012 .flags = ADDR_TYPE_RT
6017 /* l4_per -> uart2 */
6018 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6019 .master = &omap44xx_l4_per_hwmod,
6020 .slave = &omap44xx_uart2_hwmod,
6022 .addr = omap44xx_uart2_addrs,
6023 .user = OCP_USER_MPU | OCP_USER_SDMA,
6026 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6028 .pa_start = 0x48020000,
6029 .pa_end = 0x480200ff,
6030 .flags = ADDR_TYPE_RT
6035 /* l4_per -> uart3 */
6036 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6037 .master = &omap44xx_l4_per_hwmod,
6038 .slave = &omap44xx_uart3_hwmod,
6040 .addr = omap44xx_uart3_addrs,
6041 .user = OCP_USER_MPU | OCP_USER_SDMA,
6044 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6046 .pa_start = 0x4806e000,
6047 .pa_end = 0x4806e0ff,
6048 .flags = ADDR_TYPE_RT
6053 /* l4_per -> uart4 */
6054 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6055 .master = &omap44xx_l4_per_hwmod,
6056 .slave = &omap44xx_uart4_hwmod,
6058 .addr = omap44xx_uart4_addrs,
6059 .user = OCP_USER_MPU | OCP_USER_SDMA,
6062 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6064 .pa_start = 0x4a0a9000,
6065 .pa_end = 0x4a0a93ff,
6066 .flags = ADDR_TYPE_RT
6071 /* l4_cfg -> usb_host_fs */
6072 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6073 .master = &omap44xx_l4_cfg_hwmod,
6074 .slave = &omap44xx_usb_host_fs_hwmod,
6076 .addr = omap44xx_usb_host_fs_addrs,
6077 .user = OCP_USER_MPU | OCP_USER_SDMA,
6080 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6083 .pa_start = 0x4a064000,
6084 .pa_end = 0x4a0647ff,
6085 .flags = ADDR_TYPE_RT
6089 .pa_start = 0x4a064800,
6090 .pa_end = 0x4a064bff,
6094 .pa_start = 0x4a064c00,
6095 .pa_end = 0x4a064fff,
6100 /* l4_cfg -> usb_host_hs */
6101 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6102 .master = &omap44xx_l4_cfg_hwmod,
6103 .slave = &omap44xx_usb_host_hs_hwmod,
6105 .addr = omap44xx_usb_host_hs_addrs,
6106 .user = OCP_USER_MPU | OCP_USER_SDMA,
6109 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6111 .pa_start = 0x4a0ab000,
6112 .pa_end = 0x4a0ab7ff,
6113 .flags = ADDR_TYPE_RT
6116 /* XXX: Remove this once control module driver is in place */
6117 .pa_start = 0x4a00233c,
6118 .pa_end = 0x4a00233f,
6119 .flags = ADDR_TYPE_RT
6124 /* l4_cfg -> usb_otg_hs */
6125 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6126 .master = &omap44xx_l4_cfg_hwmod,
6127 .slave = &omap44xx_usb_otg_hs_hwmod,
6129 .addr = omap44xx_usb_otg_hs_addrs,
6130 .user = OCP_USER_MPU | OCP_USER_SDMA,
6133 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6136 .pa_start = 0x4a062000,
6137 .pa_end = 0x4a063fff,
6138 .flags = ADDR_TYPE_RT
6143 /* l4_cfg -> usb_tll_hs */
6144 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6145 .master = &omap44xx_l4_cfg_hwmod,
6146 .slave = &omap44xx_usb_tll_hs_hwmod,
6148 .addr = omap44xx_usb_tll_hs_addrs,
6149 .user = OCP_USER_MPU | OCP_USER_SDMA,
6152 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6154 .pa_start = 0x4a314000,
6155 .pa_end = 0x4a31407f,
6156 .flags = ADDR_TYPE_RT
6161 /* l4_wkup -> wd_timer2 */
6162 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6163 .master = &omap44xx_l4_wkup_hwmod,
6164 .slave = &omap44xx_wd_timer2_hwmod,
6165 .clk = "l4_wkup_clk_mux_ck",
6166 .addr = omap44xx_wd_timer2_addrs,
6167 .user = OCP_USER_MPU | OCP_USER_SDMA,
6170 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6172 .pa_start = 0x40130000,
6173 .pa_end = 0x4013007f,
6174 .flags = ADDR_TYPE_RT
6179 /* l4_abe -> wd_timer3 */
6180 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6181 .master = &omap44xx_l4_abe_hwmod,
6182 .slave = &omap44xx_wd_timer3_hwmod,
6183 .clk = "ocp_abe_iclk",
6184 .addr = omap44xx_wd_timer3_addrs,
6185 .user = OCP_USER_MPU,
6188 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6190 .pa_start = 0x49030000,
6191 .pa_end = 0x4903007f,
6192 .flags = ADDR_TYPE_RT
6197 /* l4_abe -> wd_timer3 (dma) */
6198 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6199 .master = &omap44xx_l4_abe_hwmod,
6200 .slave = &omap44xx_wd_timer3_hwmod,
6201 .clk = "ocp_abe_iclk",
6202 .addr = omap44xx_wd_timer3_dma_addrs,
6203 .user = OCP_USER_SDMA,
6206 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6207 &omap44xx_c2c__c2c_target_fw,
6208 &omap44xx_l4_cfg__c2c_target_fw,
6209 &omap44xx_l3_main_1__dmm,
6211 &omap44xx_c2c__emif_fw,
6212 &omap44xx_dmm__emif_fw,
6213 &omap44xx_l4_cfg__emif_fw,
6214 &omap44xx_iva__l3_instr,
6215 &omap44xx_l3_main_3__l3_instr,
6216 &omap44xx_ocp_wp_noc__l3_instr,
6217 &omap44xx_dsp__l3_main_1,
6218 &omap44xx_dss__l3_main_1,
6219 &omap44xx_l3_main_2__l3_main_1,
6220 &omap44xx_l4_cfg__l3_main_1,
6221 &omap44xx_mmc1__l3_main_1,
6222 &omap44xx_mmc2__l3_main_1,
6223 &omap44xx_mpu__l3_main_1,
6224 &omap44xx_c2c_target_fw__l3_main_2,
6225 &omap44xx_debugss__l3_main_2,
6226 &omap44xx_dma_system__l3_main_2,
6227 &omap44xx_fdif__l3_main_2,
6228 &omap44xx_gpu__l3_main_2,
6229 &omap44xx_hsi__l3_main_2,
6230 &omap44xx_ipu__l3_main_2,
6231 &omap44xx_iss__l3_main_2,
6232 &omap44xx_iva__l3_main_2,
6233 &omap44xx_l3_main_1__l3_main_2,
6234 &omap44xx_l4_cfg__l3_main_2,
6235 /* &omap44xx_usb_host_fs__l3_main_2, */
6236 &omap44xx_usb_host_hs__l3_main_2,
6237 &omap44xx_usb_otg_hs__l3_main_2,
6238 &omap44xx_l3_main_1__l3_main_3,
6239 &omap44xx_l3_main_2__l3_main_3,
6240 &omap44xx_l4_cfg__l3_main_3,
6241 /* &omap44xx_aess__l4_abe, */
6242 &omap44xx_dsp__l4_abe,
6243 &omap44xx_l3_main_1__l4_abe,
6244 &omap44xx_mpu__l4_abe,
6245 &omap44xx_l3_main_1__l4_cfg,
6246 &omap44xx_l3_main_2__l4_per,
6247 &omap44xx_l4_cfg__l4_wkup,
6248 &omap44xx_mpu__mpu_private,
6249 &omap44xx_l4_cfg__ocp_wp_noc,
6250 /* &omap44xx_l4_abe__aess, */
6251 /* &omap44xx_l4_abe__aess_dma, */
6252 &omap44xx_l3_main_2__c2c,
6253 &omap44xx_l4_wkup__counter_32k,
6254 &omap44xx_l4_cfg__ctrl_module_core,
6255 &omap44xx_l4_cfg__ctrl_module_pad_core,
6256 &omap44xx_l4_wkup__ctrl_module_wkup,
6257 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6258 &omap44xx_l3_instr__debugss,
6259 &omap44xx_l4_cfg__dma_system,
6260 &omap44xx_l4_abe__dmic,
6261 &omap44xx_l4_abe__dmic_dma,
6263 /* &omap44xx_dsp__sl2if, */
6264 &omap44xx_l4_cfg__dsp,
6265 &omap44xx_l3_main_2__dss,
6266 &omap44xx_l4_per__dss,
6267 &omap44xx_l3_main_2__dss_dispc,
6268 &omap44xx_l4_per__dss_dispc,
6269 &omap44xx_l3_main_2__dss_dsi1,
6270 &omap44xx_l4_per__dss_dsi1,
6271 &omap44xx_l3_main_2__dss_dsi2,
6272 &omap44xx_l4_per__dss_dsi2,
6273 &omap44xx_l3_main_2__dss_hdmi,
6274 &omap44xx_l4_per__dss_hdmi,
6275 &omap44xx_l3_main_2__dss_rfbi,
6276 &omap44xx_l4_per__dss_rfbi,
6277 &omap44xx_l3_main_2__dss_venc,
6278 &omap44xx_l4_per__dss_venc,
6279 &omap44xx_l4_per__elm,
6280 &omap44xx_emif_fw__emif1,
6281 &omap44xx_emif_fw__emif2,
6282 &omap44xx_l4_cfg__fdif,
6283 &omap44xx_l4_wkup__gpio1,
6284 &omap44xx_l4_per__gpio2,
6285 &omap44xx_l4_per__gpio3,
6286 &omap44xx_l4_per__gpio4,
6287 &omap44xx_l4_per__gpio5,
6288 &omap44xx_l4_per__gpio6,
6289 &omap44xx_l3_main_2__gpmc,
6290 &omap44xx_l3_main_2__gpu,
6291 &omap44xx_l4_per__hdq1w,
6292 &omap44xx_l4_cfg__hsi,
6293 &omap44xx_l4_per__i2c1,
6294 &omap44xx_l4_per__i2c2,
6295 &omap44xx_l4_per__i2c3,
6296 &omap44xx_l4_per__i2c4,
6297 &omap44xx_l3_main_2__ipu,
6298 &omap44xx_l3_main_2__iss,
6299 /* &omap44xx_iva__sl2if, */
6300 &omap44xx_l3_main_2__iva,
6301 &omap44xx_l4_wkup__kbd,
6302 &omap44xx_l4_cfg__mailbox,
6303 &omap44xx_l4_abe__mcasp,
6304 &omap44xx_l4_abe__mcasp_dma,
6305 &omap44xx_l4_abe__mcbsp1,
6306 &omap44xx_l4_abe__mcbsp1_dma,
6307 &omap44xx_l4_abe__mcbsp2,
6308 &omap44xx_l4_abe__mcbsp2_dma,
6309 &omap44xx_l4_abe__mcbsp3,
6310 &omap44xx_l4_abe__mcbsp3_dma,
6311 &omap44xx_l4_per__mcbsp4,
6312 &omap44xx_l4_abe__mcpdm,
6313 &omap44xx_l4_abe__mcpdm_dma,
6314 &omap44xx_l4_per__mcspi1,
6315 &omap44xx_l4_per__mcspi2,
6316 &omap44xx_l4_per__mcspi3,
6317 &omap44xx_l4_per__mcspi4,
6318 &omap44xx_l4_per__mmc1,
6319 &omap44xx_l4_per__mmc2,
6320 &omap44xx_l4_per__mmc3,
6321 &omap44xx_l4_per__mmc4,
6322 &omap44xx_l4_per__mmc5,
6323 &omap44xx_l3_main_2__mmu_ipu,
6324 &omap44xx_l4_cfg__mmu_dsp,
6325 &omap44xx_l3_main_2__ocmc_ram,
6326 &omap44xx_l4_cfg__ocp2scp_usb_phy,
6327 &omap44xx_mpu_private__prcm_mpu,
6328 &omap44xx_l4_wkup__cm_core_aon,
6329 &omap44xx_l4_cfg__cm_core,
6330 &omap44xx_l4_wkup__prm,
6331 &omap44xx_l4_wkup__scrm,
6332 /* &omap44xx_l3_main_2__sl2if, */
6333 &omap44xx_l4_abe__slimbus1,
6334 &omap44xx_l4_abe__slimbus1_dma,
6335 &omap44xx_l4_per__slimbus2,
6336 &omap44xx_l4_cfg__smartreflex_core,
6337 &omap44xx_l4_cfg__smartreflex_iva,
6338 &omap44xx_l4_cfg__smartreflex_mpu,
6339 &omap44xx_l4_cfg__spinlock,
6340 &omap44xx_l4_wkup__timer1,
6341 &omap44xx_l4_per__timer2,
6342 &omap44xx_l4_per__timer3,
6343 &omap44xx_l4_per__timer4,
6344 &omap44xx_l4_abe__timer5,
6345 &omap44xx_l4_abe__timer5_dma,
6346 &omap44xx_l4_abe__timer6,
6347 &omap44xx_l4_abe__timer6_dma,
6348 &omap44xx_l4_abe__timer7,
6349 &omap44xx_l4_abe__timer7_dma,
6350 &omap44xx_l4_abe__timer8,
6351 &omap44xx_l4_abe__timer8_dma,
6352 &omap44xx_l4_per__timer9,
6353 &omap44xx_l4_per__timer10,
6354 &omap44xx_l4_per__timer11,
6355 &omap44xx_l4_per__uart1,
6356 &omap44xx_l4_per__uart2,
6357 &omap44xx_l4_per__uart3,
6358 &omap44xx_l4_per__uart4,
6359 /* &omap44xx_l4_cfg__usb_host_fs, */
6360 &omap44xx_l4_cfg__usb_host_hs,
6361 &omap44xx_l4_cfg__usb_otg_hs,
6362 &omap44xx_l4_cfg__usb_tll_hs,
6363 &omap44xx_l4_wkup__wd_timer2,
6364 &omap44xx_l4_abe__wd_timer3,
6365 &omap44xx_l4_abe__wd_timer3_dma,
6369 int __init omap44xx_hwmod_init(void)
6372 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);