arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17 #include <linux/power/smartreflex.h>
  18 #include <linux/platform_data/gpio-omap.h>
  19
  20 #include <plat/omap_hwmod.h>
  21 #include <plat/dma.h>
  22 #include <plat/serial.h>
  23 #include <plat/l3_3xxx.h>
  24 #include <plat/l4_3xxx.h>
  25 #include <plat/i2c.h>
  26 #include <plat/mmc.h>
  27 #include <plat/mcbsp.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/dmtimer.h>
  30 #include <plat/iommu.h>
  31
  32 #include <mach/am35xx.h>
  33
  34 #include "soc.h"
  35 #include "omap_hwmod_common_data.h"
  36 #include "prm-regbits-34xx.h"
  37 #include "cm-regbits-34xx.h"
  38 #include "wd_timer.h"
  39
  40 /*
  41  * OMAP3xxx hardware module integration data
  42  *
  43  * All of the data in this section should be autogeneratable from the
  44  * TI hardware database or other technical documentation.  Data that
  45  * is driver-specific or driver-kernel integration-specific belongs
  46  * elsewhere.
  47  */
  48
  49 /*
  50  * IP blocks
  51  */
  52
  53 /* L3 */
  54 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  55         { .irq = 9 + OMAP_INTC_START, },
  56         { .irq = 10 + OMAP_INTC_START, },
  57         { .irq = -1 },
  58 };
  59
  60 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  61         .name           = "l3_main",
  62         .class          = &l3_hwmod_class,
  63         .mpu_irqs       = omap3xxx_l3_main_irqs,
  64         .flags          = HWMOD_NO_IDLEST,
  65 };
  66
  67 /* L4 CORE */
  68 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  69         .name           = "l4_core",
  70         .class          = &l4_hwmod_class,
  71         .flags          = HWMOD_NO_IDLEST,
  72 };
  73
  74 /* L4 PER */
  75 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  76         .name           = "l4_per",
  77         .class          = &l4_hwmod_class,
  78         .flags          = HWMOD_NO_IDLEST,
  79 };
  80
  81 /* L4 WKUP */
  82 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  83         .name           = "l4_wkup",
  84         .class          = &l4_hwmod_class,
  85         .flags          = HWMOD_NO_IDLEST,
  86 };
  87
  88 /* L4 SEC */
  89 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  90         .name           = "l4_sec",
  91         .class          = &l4_hwmod_class,
  92         .flags          = HWMOD_NO_IDLEST,
  93 };
  94
  95 /* MPU */
  96 static struct omap_hwmod omap3xxx_mpu_hwmod = {
  97         .name           = "mpu",
  98         .class          = &mpu_hwmod_class,
  99         .main_clk       = "arm_fck",
 100 };
 101
 102 /* IVA2 (IVA2) */
 103 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 104         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
 105         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
 106         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 107 };
 108
 109 static struct omap_hwmod omap3xxx_iva_hwmod = {
 110         .name           = "iva",
 111         .class          = &iva_hwmod_class,
 112         .clkdm_name     = "iva2_clkdm",
 113         .rst_lines      = omap3xxx_iva_resets,
 114         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 115         .main_clk       = "iva2_ck",
 116         .prcm = {
 117                 .omap2 = {
 118                         .module_offs = OMAP3430_IVA2_MOD,
 119                         .prcm_reg_id = 1,
 120                         .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
 121                         .idlest_reg_id = 1,
 122                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 123                 }
 124         },
 125 };
 126
 127 /* timer class */
 128 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 129         .rev_offs       = 0x0000,
 130         .sysc_offs      = 0x0010,
 131         .syss_offs      = 0x0014,
 132         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 133                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 134                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 135         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 136         .sysc_fields    = &omap_hwmod_sysc_type1,
 137 };
 138
 139 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 140         .name = "timer",
 141         .sysc = &omap3xxx_timer_1ms_sysc,
 142 };
 143
 144 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 145         .rev_offs       = 0x0000,
 146         .sysc_offs      = 0x0010,
 147         .syss_offs      = 0x0014,
 148         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 149                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 150         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 151         .sysc_fields    = &omap_hwmod_sysc_type1,
 152 };
 153
 154 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 155         .name = "timer",
 156         .sysc = &omap3xxx_timer_sysc,
 157 };
 158
 159 /* secure timers dev attribute */
 160 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 161         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 162 };
 163
 164 /* always-on timers dev attribute */
 165 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 166         .timer_capability       = OMAP_TIMER_ALWON,
 167 };
 168
 169 /* pwm timers dev attribute */
 170 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 171         .timer_capability       = OMAP_TIMER_HAS_PWM,
 172 };
 173
 174 /* timer1 */
 175 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 176         .name           = "timer1",
 177         .mpu_irqs       = omap2_timer1_mpu_irqs,
 178         .main_clk       = "gpt1_fck",
 179         .prcm           = {
 180                 .omap2 = {
 181                         .prcm_reg_id = 1,
 182                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 183                         .module_offs = WKUP_MOD,
 184                         .idlest_reg_id = 1,
 185                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 186                 },
 187         },
 188         .dev_attr       = &capability_alwon_dev_attr,
 189         .class          = &omap3xxx_timer_1ms_hwmod_class,
 190 };
 191
 192 /* timer2 */
 193 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 194         .name           = "timer2",
 195         .mpu_irqs       = omap2_timer2_mpu_irqs,
 196         .main_clk       = "gpt2_fck",
 197         .prcm           = {
 198                 .omap2 = {
 199                         .prcm_reg_id = 1,
 200                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 201                         .module_offs = OMAP3430_PER_MOD,
 202                         .idlest_reg_id = 1,
 203                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 204                 },
 205         },
 206         .class          = &omap3xxx_timer_1ms_hwmod_class,
 207 };
 208
 209 /* timer3 */
 210 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 211         .name           = "timer3",
 212         .mpu_irqs       = omap2_timer3_mpu_irqs,
 213         .main_clk       = "gpt3_fck",
 214         .prcm           = {
 215                 .omap2 = {
 216                         .prcm_reg_id = 1,
 217                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 218                         .module_offs = OMAP3430_PER_MOD,
 219                         .idlest_reg_id = 1,
 220                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 221                 },
 222         },
 223         .class          = &omap3xxx_timer_hwmod_class,
 224 };
 225
 226 /* timer4 */
 227 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 228         .name           = "timer4",
 229         .mpu_irqs       = omap2_timer4_mpu_irqs,
 230         .main_clk       = "gpt4_fck",
 231         .prcm           = {
 232                 .omap2 = {
 233                         .prcm_reg_id = 1,
 234                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 235                         .module_offs = OMAP3430_PER_MOD,
 236                         .idlest_reg_id = 1,
 237                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 238                 },
 239         },
 240         .class          = &omap3xxx_timer_hwmod_class,
 241 };
 242
 243 /* timer5 */
 244 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 245         .name           = "timer5",
 246         .mpu_irqs       = omap2_timer5_mpu_irqs,
 247         .main_clk       = "gpt5_fck",
 248         .prcm           = {
 249                 .omap2 = {
 250                         .prcm_reg_id = 1,
 251                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 252                         .module_offs = OMAP3430_PER_MOD,
 253                         .idlest_reg_id = 1,
 254                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 255                 },
 256         },
 257         .class          = &omap3xxx_timer_hwmod_class,
 258 };
 259
 260 /* timer6 */
 261 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 262         .name           = "timer6",
 263         .mpu_irqs       = omap2_timer6_mpu_irqs,
 264         .main_clk       = "gpt6_fck",
 265         .prcm           = {
 266                 .omap2 = {
 267                         .prcm_reg_id = 1,
 268                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 269                         .module_offs = OMAP3430_PER_MOD,
 270                         .idlest_reg_id = 1,
 271                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 272                 },
 273         },
 274         .class          = &omap3xxx_timer_hwmod_class,
 275 };
 276
 277 /* timer7 */
 278 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 279         .name           = "timer7",
 280         .mpu_irqs       = omap2_timer7_mpu_irqs,
 281         .main_clk       = "gpt7_fck",
 282         .prcm           = {
 283                 .omap2 = {
 284                         .prcm_reg_id = 1,
 285                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 286                         .module_offs = OMAP3430_PER_MOD,
 287                         .idlest_reg_id = 1,
 288                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 289                 },
 290         },
 291         .class          = &omap3xxx_timer_hwmod_class,
 292 };
 293
 294 /* timer8 */
 295 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 296         .name           = "timer8",
 297         .mpu_irqs       = omap2_timer8_mpu_irqs,
 298         .main_clk       = "gpt8_fck",
 299         .prcm           = {
 300                 .omap2 = {
 301                         .prcm_reg_id = 1,
 302                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 303                         .module_offs = OMAP3430_PER_MOD,
 304                         .idlest_reg_id = 1,
 305                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 306                 },
 307         },
 308         .dev_attr       = &capability_pwm_dev_attr,
 309         .class          = &omap3xxx_timer_hwmod_class,
 310 };
 311
 312 /* timer9 */
 313 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 314         .name           = "timer9",
 315         .mpu_irqs       = omap2_timer9_mpu_irqs,
 316         .main_clk       = "gpt9_fck",
 317         .prcm           = {
 318                 .omap2 = {
 319                         .prcm_reg_id = 1,
 320                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 321                         .module_offs = OMAP3430_PER_MOD,
 322                         .idlest_reg_id = 1,
 323                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 324                 },
 325         },
 326         .dev_attr       = &capability_pwm_dev_attr,
 327         .class          = &omap3xxx_timer_hwmod_class,
 328 };
 329
 330 /* timer10 */
 331 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 332         .name           = "timer10",
 333         .mpu_irqs       = omap2_timer10_mpu_irqs,
 334         .main_clk       = "gpt10_fck",
 335         .prcm           = {
 336                 .omap2 = {
 337                         .prcm_reg_id = 1,
 338                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 339                         .module_offs = CORE_MOD,
 340                         .idlest_reg_id = 1,
 341                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 342                 },
 343         },
 344         .dev_attr       = &capability_pwm_dev_attr,
 345         .class          = &omap3xxx_timer_1ms_hwmod_class,
 346 };
 347
 348 /* timer11 */
 349 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 350         .name           = "timer11",
 351         .mpu_irqs       = omap2_timer11_mpu_irqs,
 352         .main_clk       = "gpt11_fck",
 353         .prcm           = {
 354                 .omap2 = {
 355                         .prcm_reg_id = 1,
 356                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 357                         .module_offs = CORE_MOD,
 358                         .idlest_reg_id = 1,
 359                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 360                 },
 361         },
 362         .dev_attr       = &capability_pwm_dev_attr,
 363         .class          = &omap3xxx_timer_hwmod_class,
 364 };
 365
 366 /* timer12 */
 367 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 368         { .irq = 95 + OMAP_INTC_START, },
 369         { .irq = -1 },
 370 };
 371
 372 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 373         .name           = "timer12",
 374         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 375         .main_clk       = "gpt12_fck",
 376         .prcm           = {
 377                 .omap2 = {
 378                         .prcm_reg_id = 1,
 379                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 380                         .module_offs = WKUP_MOD,
 381                         .idlest_reg_id = 1,
 382                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 383                 },
 384         },
 385         .dev_attr       = &capability_secure_dev_attr,
 386         .class          = &omap3xxx_timer_hwmod_class,
 387 };
 388
 389 /*
 390  * 'wd_timer' class
 391  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 392  * overflow condition
 393  */
 394
 395 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 396         .rev_offs       = 0x0000,
 397         .sysc_offs      = 0x0010,
 398         .syss_offs      = 0x0014,
 399         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 400                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 401                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 402                            SYSS_HAS_RESET_STATUS),
 403         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 404         .sysc_fields    = &omap_hwmod_sysc_type1,
 405 };
 406
 407 /* I2C common */
 408 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 409         .rev_offs       = 0x00,
 410         .sysc_offs      = 0x20,
 411         .syss_offs      = 0x10,
 412         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 413                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 414                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 415         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 416         .clockact       = CLOCKACT_TEST_ICLK,
 417         .sysc_fields    = &omap_hwmod_sysc_type1,
 418 };
 419
 420 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 421         .name           = "wd_timer",
 422         .sysc           = &omap3xxx_wd_timer_sysc,
 423         .pre_shutdown   = &omap2_wd_timer_disable,
 424         .reset          = &omap2_wd_timer_reset,
 425 };
 426
 427 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 428         .name           = "wd_timer2",
 429         .class          = &omap3xxx_wd_timer_hwmod_class,
 430         .main_clk       = "wdt2_fck",
 431         .prcm           = {
 432                 .omap2 = {
 433                         .prcm_reg_id = 1,
 434                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 435                         .module_offs = WKUP_MOD,
 436                         .idlest_reg_id = 1,
 437                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 438                 },
 439         },
 440         /*
 441          * XXX: Use software supervised mode, HW supervised smartidle seems to
 442          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 443          */
 444         .flags          = HWMOD_SWSUP_SIDLE,
 445 };
 446
 447 /* UART1 */
 448 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 449         .name           = "uart1",
 450         .mpu_irqs       = omap2_uart1_mpu_irqs,
 451         .sdma_reqs      = omap2_uart1_sdma_reqs,
 452         .main_clk       = "uart1_fck",
 453         .prcm           = {
 454                 .omap2 = {
 455                         .module_offs = CORE_MOD,
 456                         .prcm_reg_id = 1,
 457                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 458                         .idlest_reg_id = 1,
 459                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 460                 },
 461         },
 462         .class          = &omap2_uart_class,
 463 };
 464
 465 /* UART2 */
 466 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 467         .name           = "uart2",
 468         .mpu_irqs       = omap2_uart2_mpu_irqs,
 469         .sdma_reqs      = omap2_uart2_sdma_reqs,
 470         .main_clk       = "uart2_fck",
 471         .prcm           = {
 472                 .omap2 = {
 473                         .module_offs = CORE_MOD,
 474                         .prcm_reg_id = 1,
 475                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 476                         .idlest_reg_id = 1,
 477                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 478                 },
 479         },
 480         .class          = &omap2_uart_class,
 481 };
 482
 483 /* UART3 */
 484 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 485         .name           = "uart3",
 486         .mpu_irqs       = omap2_uart3_mpu_irqs,
 487         .sdma_reqs      = omap2_uart3_sdma_reqs,
 488         .main_clk       = "uart3_fck",
 489         .prcm           = {
 490                 .omap2 = {
 491                         .module_offs = OMAP3430_PER_MOD,
 492                         .prcm_reg_id = 1,
 493                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 494                         .idlest_reg_id = 1,
 495                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 496                 },
 497         },
 498         .class          = &omap2_uart_class,
 499 };
 500
 501 /* UART4 */
 502 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 503         { .irq = 80 + OMAP_INTC_START, },
 504         { .irq = -1 },
 505 };
 506
 507 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 508         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 509         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 510         { .dma_req = -1 }
 511 };
 512
 513 static struct omap_hwmod omap36xx_uart4_hwmod = {
 514         .name           = "uart4",
 515         .mpu_irqs       = uart4_mpu_irqs,
 516         .sdma_reqs      = uart4_sdma_reqs,
 517         .main_clk       = "uart4_fck",
 518         .prcm           = {
 519                 .omap2 = {
 520                         .module_offs = OMAP3430_PER_MOD,
 521                         .prcm_reg_id = 1,
 522                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 523                         .idlest_reg_id = 1,
 524                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 525                 },
 526         },
 527         .class          = &omap2_uart_class,
 528 };
 529
 530 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 531         { .irq = 84 + OMAP_INTC_START, },
 532         { .irq = -1 },
 533 };
 534
 535 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 536         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
 537         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 538         { .dma_req = -1 }
 539 };
 540
 541 /*
 542  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 543  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 544  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 545  * should not be needed.  The functional clock structure of the AM35xx
 546  * UART4 is extremely unclear and opaque; it is unclear what the role
 547  * of uart1/2_fck is for the UART4.  Any clarification from either
 548  * empirical testing or the AM3505/3517 hardware designers would be
 549  * most welcome.
 550  */
 551 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 552         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 553 };
 554
 555 static struct omap_hwmod am35xx_uart4_hwmod = {
 556         .name           = "uart4",
 557         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 558         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 559         .main_clk       = "uart4_fck",
 560         .prcm           = {
 561                 .omap2 = {
 562                         .module_offs = CORE_MOD,
 563                         .prcm_reg_id = 1,
 564                         .module_bit = AM35XX_EN_UART4_SHIFT,
 565                         .idlest_reg_id = 1,
 566                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 567                 },
 568         },
 569         .opt_clks       = am35xx_uart4_opt_clks,
 570         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 571         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 572         .class          = &omap2_uart_class,
 573 };
 574
 575 static struct omap_hwmod_class i2c_class = {
 576         .name   = "i2c",
 577         .sysc   = &i2c_sysc,
 578         .rev    = OMAP_I2C_IP_VERSION_1,
 579         .reset  = &omap_i2c_reset,
 580 };
 581
 582 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 583         { .name = "dispc", .dma_req = 5 },
 584         { .name = "dsi1", .dma_req = 74 },
 585         { .dma_req = -1 }
 586 };
 587
 588 /* dss */
 589 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 590         /*
 591          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 592          * driver does not use these clocks.
 593          */
 594         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 595         { .role = "tv_clk", .clk = "dss_tv_fck" },
 596         /* required only on OMAP3430 */
 597         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 598 };
 599
 600 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 601         .name           = "dss_core",
 602         .class          = &omap2_dss_hwmod_class,
 603         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 604         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 605         .prcm           = {
 606                 .omap2 = {
 607                         .prcm_reg_id = 1,
 608                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 609                         .module_offs = OMAP3430_DSS_MOD,
 610                         .idlest_reg_id = 1,
 611                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 612                 },
 613         },
 614         .opt_clks       = dss_opt_clks,
 615         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 616         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 617 };
 618
 619 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 620         .name           = "dss_core",
 621         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 622         .class          = &omap2_dss_hwmod_class,
 623         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 624         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 625         .prcm           = {
 626                 .omap2 = {
 627                         .prcm_reg_id = 1,
 628                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 629                         .module_offs = OMAP3430_DSS_MOD,
 630                         .idlest_reg_id = 1,
 631                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 632                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 633                 },
 634         },
 635         .opt_clks       = dss_opt_clks,
 636         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 637 };
 638
 639 /*
 640  * 'dispc' class
 641  * display controller
 642  */
 643
 644 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 645         .rev_offs       = 0x0000,
 646         .sysc_offs      = 0x0010,
 647         .syss_offs      = 0x0014,
 648         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 649                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 650                            SYSC_HAS_ENAWAKEUP),
 651         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 652                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 653         .sysc_fields    = &omap_hwmod_sysc_type1,
 654 };
 655
 656 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 657         .name   = "dispc",
 658         .sysc   = &omap3_dispc_sysc,
 659 };
 660
 661 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 662         .name           = "dss_dispc",
 663         .class          = &omap3_dispc_hwmod_class,
 664         .mpu_irqs       = omap2_dispc_irqs,
 665         .main_clk       = "dss1_alwon_fck",
 666         .prcm           = {
 667                 .omap2 = {
 668                         .prcm_reg_id = 1,
 669                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 670                         .module_offs = OMAP3430_DSS_MOD,
 671                 },
 672         },
 673         .flags          = HWMOD_NO_IDLEST,
 674         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 675 };
 676
 677 /*
 678  * 'dsi' class
 679  * display serial interface controller
 680  */
 681
 682 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 683         .name = "dsi",
 684 };
 685
 686 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 687         { .irq = 25 + OMAP_INTC_START, },
 688         { .irq = -1 },
 689 };
 690
 691 /* dss_dsi1 */
 692 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 693         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 694 };
 695
 696 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 697         .name           = "dss_dsi1",
 698         .class          = &omap3xxx_dsi_hwmod_class,
 699         .mpu_irqs       = omap3xxx_dsi1_irqs,
 700         .main_clk       = "dss1_alwon_fck",
 701         .prcm           = {
 702                 .omap2 = {
 703                         .prcm_reg_id = 1,
 704                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 705                         .module_offs = OMAP3430_DSS_MOD,
 706                 },
 707         },
 708         .opt_clks       = dss_dsi1_opt_clks,
 709         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 710         .flags          = HWMOD_NO_IDLEST,
 711 };
 712
 713 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 714         { .role = "ick", .clk = "dss_ick" },
 715 };
 716
 717 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 718         .name           = "dss_rfbi",
 719         .class          = &omap2_rfbi_hwmod_class,
 720         .main_clk       = "dss1_alwon_fck",
 721         .prcm           = {
 722                 .omap2 = {
 723                         .prcm_reg_id = 1,
 724                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 725                         .module_offs = OMAP3430_DSS_MOD,
 726                 },
 727         },
 728         .opt_clks       = dss_rfbi_opt_clks,
 729         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 730         .flags          = HWMOD_NO_IDLEST,
 731 };
 732
 733 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 734         /* required only on OMAP3430 */
 735         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 736 };
 737
 738 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 739         .name           = "dss_venc",
 740         .class          = &omap2_venc_hwmod_class,
 741         .main_clk       = "dss_tv_fck",
 742         .prcm           = {
 743                 .omap2 = {
 744                         .prcm_reg_id = 1,
 745                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 746                         .module_offs = OMAP3430_DSS_MOD,
 747                 },
 748         },
 749         .opt_clks       = dss_venc_opt_clks,
 750         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 751         .flags          = HWMOD_NO_IDLEST,
 752 };
 753
 754 /* I2C1 */
 755 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 756         .fifo_depth     = 8, /* bytes */
 757         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 758                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 759                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 760 };
 761
 762 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 763         .name           = "i2c1",
 764         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 765         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 766         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 767         .main_clk       = "i2c1_fck",
 768         .prcm           = {
 769                 .omap2 = {
 770                         .module_offs = CORE_MOD,
 771                         .prcm_reg_id = 1,
 772                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 773                         .idlest_reg_id = 1,
 774                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 775                 },
 776         },
 777         .class          = &i2c_class,
 778         .dev_attr       = &i2c1_dev_attr,
 779 };
 780
 781 /* I2C2 */
 782 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 783         .fifo_depth     = 8, /* bytes */
 784         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 785                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 786                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 787 };
 788
 789 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 790         .name           = "i2c2",
 791         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 792         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 793         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 794         .main_clk       = "i2c2_fck",
 795         .prcm           = {
 796                 .omap2 = {
 797                         .module_offs = CORE_MOD,
 798                         .prcm_reg_id = 1,
 799                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 800                         .idlest_reg_id = 1,
 801                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 802                 },
 803         },
 804         .class          = &i2c_class,
 805         .dev_attr       = &i2c2_dev_attr,
 806 };
 807
 808 /* I2C3 */
 809 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 810         .fifo_depth     = 64, /* bytes */
 811         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 812                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 813                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 814 };
 815
 816 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 817         { .irq = 61 + OMAP_INTC_START, },
 818         { .irq = -1 },
 819 };
 820
 821 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 822         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 823         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 824         { .dma_req = -1 }
 825 };
 826
 827 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 828         .name           = "i2c3",
 829         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 830         .mpu_irqs       = i2c3_mpu_irqs,
 831         .sdma_reqs      = i2c3_sdma_reqs,
 832         .main_clk       = "i2c3_fck",
 833         .prcm           = {
 834                 .omap2 = {
 835                         .module_offs = CORE_MOD,
 836                         .prcm_reg_id = 1,
 837                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 838                         .idlest_reg_id = 1,
 839                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 840                 },
 841         },
 842         .class          = &i2c_class,
 843         .dev_attr       = &i2c3_dev_attr,
 844 };
 845
 846 /*
 847  * 'gpio' class
 848  * general purpose io module
 849  */
 850
 851 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 852         .rev_offs       = 0x0000,
 853         .sysc_offs      = 0x0010,
 854         .syss_offs      = 0x0014,
 855         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 856                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 857                            SYSS_HAS_RESET_STATUS),
 858         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 859         .sysc_fields    = &omap_hwmod_sysc_type1,
 860 };
 861
 862 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 863         .name = "gpio",
 864         .sysc = &omap3xxx_gpio_sysc,
 865         .rev = 1,
 866 };
 867
 868 /* gpio_dev_attr */
 869 static struct omap_gpio_dev_attr gpio_dev_attr = {
 870         .bank_width = 32,
 871         .dbck_flag = true,
 872 };
 873
 874 /* gpio1 */
 875 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 876         { .role = "dbclk", .clk = "gpio1_dbck", },
 877 };
 878
 879 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 880         .name           = "gpio1",
 881         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 882         .mpu_irqs       = omap2_gpio1_irqs,
 883         .main_clk       = "gpio1_ick",
 884         .opt_clks       = gpio1_opt_clks,
 885         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 886         .prcm           = {
 887                 .omap2 = {
 888                         .prcm_reg_id = 1,
 889                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 890                         .module_offs = WKUP_MOD,
 891                         .idlest_reg_id = 1,
 892                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 893                 },
 894         },
 895         .class          = &omap3xxx_gpio_hwmod_class,
 896         .dev_attr       = &gpio_dev_attr,
 897 };
 898
 899 /* gpio2 */
 900 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 901         { .role = "dbclk", .clk = "gpio2_dbck", },
 902 };
 903
 904 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 905         .name           = "gpio2",
 906         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 907         .mpu_irqs       = omap2_gpio2_irqs,
 908         .main_clk       = "gpio2_ick",
 909         .opt_clks       = gpio2_opt_clks,
 910         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 911         .prcm           = {
 912                 .omap2 = {
 913                         .prcm_reg_id = 1,
 914                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 915                         .module_offs = OMAP3430_PER_MOD,
 916                         .idlest_reg_id = 1,
 917                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 918                 },
 919         },
 920         .class          = &omap3xxx_gpio_hwmod_class,
 921         .dev_attr       = &gpio_dev_attr,
 922 };
 923
 924 /* gpio3 */
 925 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 926         { .role = "dbclk", .clk = "gpio3_dbck", },
 927 };
 928
 929 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 930         .name           = "gpio3",
 931         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 932         .mpu_irqs       = omap2_gpio3_irqs,
 933         .main_clk       = "gpio3_ick",
 934         .opt_clks       = gpio3_opt_clks,
 935         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 936         .prcm           = {
 937                 .omap2 = {
 938                         .prcm_reg_id = 1,
 939                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 940                         .module_offs = OMAP3430_PER_MOD,
 941                         .idlest_reg_id = 1,
 942                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 943                 },
 944         },
 945         .class          = &omap3xxx_gpio_hwmod_class,
 946         .dev_attr       = &gpio_dev_attr,
 947 };
 948
 949 /* gpio4 */
 950 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 951         { .role = "dbclk", .clk = "gpio4_dbck", },
 952 };
 953
 954 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 955         .name           = "gpio4",
 956         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 957         .mpu_irqs       = omap2_gpio4_irqs,
 958         .main_clk       = "gpio4_ick",
 959         .opt_clks       = gpio4_opt_clks,
 960         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 961         .prcm           = {
 962                 .omap2 = {
 963                         .prcm_reg_id = 1,
 964                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
 965                         .module_offs = OMAP3430_PER_MOD,
 966                         .idlest_reg_id = 1,
 967                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
 968                 },
 969         },
 970         .class          = &omap3xxx_gpio_hwmod_class,
 971         .dev_attr       = &gpio_dev_attr,
 972 };
 973
 974 /* gpio5 */
 975 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
 976         { .irq = 33 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK5 */
 977         { .irq = -1 },
 978 };
 979
 980 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 981         { .role = "dbclk", .clk = "gpio5_dbck", },
 982 };
 983
 984 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 985         .name           = "gpio5",
 986         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 987         .mpu_irqs       = omap3xxx_gpio5_irqs,
 988         .main_clk       = "gpio5_ick",
 989         .opt_clks       = gpio5_opt_clks,
 990         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 991         .prcm           = {
 992                 .omap2 = {
 993                         .prcm_reg_id = 1,
 994                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
 995                         .module_offs = OMAP3430_PER_MOD,
 996                         .idlest_reg_id = 1,
 997                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
 998                 },
 999         },
1000         .class          = &omap3xxx_gpio_hwmod_class,
1001         .dev_attr       = &gpio_dev_attr,
1002 };
1003
1004 /* gpio6 */
1005 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1006         { .irq = 34 + OMAP_INTC_START, }, /* INT_34XX_GPIO_BANK6 */
1007         { .irq = -1 },
1008 };
1009
1010 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1011         { .role = "dbclk", .clk = "gpio6_dbck", },
1012 };
1013
1014 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1015         .name           = "gpio6",
1016         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1017         .mpu_irqs       = omap3xxx_gpio6_irqs,
1018         .main_clk       = "gpio6_ick",
1019         .opt_clks       = gpio6_opt_clks,
1020         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1021         .prcm           = {
1022                 .omap2 = {
1023                         .prcm_reg_id = 1,
1024                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1025                         .module_offs = OMAP3430_PER_MOD,
1026                         .idlest_reg_id = 1,
1027                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1028                 },
1029         },
1030         .class          = &omap3xxx_gpio_hwmod_class,
1031         .dev_attr       = &gpio_dev_attr,
1032 };
1033
1034 /* dma attributes */
1035 static struct omap_dma_dev_attr dma_dev_attr = {
1036         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1037                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1038         .lch_count = 32,
1039 };
1040
1041 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1042         .rev_offs       = 0x0000,
1043         .sysc_offs      = 0x002c,
1044         .syss_offs      = 0x0028,
1045         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1046                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1047                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1048                            SYSS_HAS_RESET_STATUS),
1049         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1050                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1051         .sysc_fields    = &omap_hwmod_sysc_type1,
1052 };
1053
1054 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1055         .name = "dma",
1056         .sysc = &omap3xxx_dma_sysc,
1057 };
1058
1059 /* dma_system */
1060 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1061         .name           = "dma",
1062         .class          = &omap3xxx_dma_hwmod_class,
1063         .mpu_irqs       = omap2_dma_system_irqs,
1064         .main_clk       = "core_l3_ick",
1065         .prcm = {
1066                 .omap2 = {
1067                         .module_offs            = CORE_MOD,
1068                         .prcm_reg_id            = 1,
1069                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1070                         .idlest_reg_id          = 1,
1071                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1072                 },
1073         },
1074         .dev_attr       = &dma_dev_attr,
1075         .flags          = HWMOD_NO_IDLEST,
1076 };
1077
1078 /*
1079  * 'mcbsp' class
1080  * multi channel buffered serial port controller
1081  */
1082
1083 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1084         .sysc_offs      = 0x008c,
1085         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1086                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1087         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1088         .sysc_fields    = &omap_hwmod_sysc_type1,
1089         .clockact       = 0x2,
1090 };
1091
1092 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1093         .name = "mcbsp",
1094         .sysc = &omap3xxx_mcbsp_sysc,
1095         .rev  = MCBSP_CONFIG_TYPE3,
1096 };
1097
1098 /* McBSP functional clock mapping */
1099 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
1100         { .role = "pad_fck", .clk = "mcbsp_clks" },
1101         { .role = "prcm_fck", .clk = "core_96m_fck" },
1102 };
1103
1104 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
1105         { .role = "pad_fck", .clk = "mcbsp_clks" },
1106         { .role = "prcm_fck", .clk = "per_96m_fck" },
1107 };
1108
1109 /* mcbsp1 */
1110 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1111         { .name = "common", .irq = 16 + OMAP_INTC_START, },
1112         { .name = "tx", .irq = 59 + OMAP_INTC_START, },
1113         { .name = "rx", .irq = 60 + OMAP_INTC_START, },
1114         { .irq = -1 },
1115 };
1116
1117 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1118         .name           = "mcbsp1",
1119         .class          = &omap3xxx_mcbsp_hwmod_class,
1120         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1121         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1122         .main_clk       = "mcbsp1_fck",
1123         .prcm           = {
1124                 .omap2 = {
1125                         .prcm_reg_id = 1,
1126                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1127                         .module_offs = CORE_MOD,
1128                         .idlest_reg_id = 1,
1129                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1130                 },
1131         },
1132         .opt_clks       = mcbsp15_opt_clks,
1133         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1134 };
1135
1136 /* mcbsp2 */
1137 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1138         { .name = "common", .irq = 17 + OMAP_INTC_START, },
1139         { .name = "tx", .irq = 62 + OMAP_INTC_START, },
1140         { .name = "rx", .irq = 63 + OMAP_INTC_START, },
1141         { .irq = -1 },
1142 };
1143
1144 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1145         .sidetone       = "mcbsp2_sidetone",
1146 };
1147
1148 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1149         .name           = "mcbsp2",
1150         .class          = &omap3xxx_mcbsp_hwmod_class,
1151         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1152         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1153         .main_clk       = "mcbsp2_fck",
1154         .prcm           = {
1155                 .omap2 = {
1156                         .prcm_reg_id = 1,
1157                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1158                         .module_offs = OMAP3430_PER_MOD,
1159                         .idlest_reg_id = 1,
1160                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1161                 },
1162         },
1163         .opt_clks       = mcbsp234_opt_clks,
1164         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1165         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1166 };
1167
1168 /* mcbsp3 */
1169 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1170         { .name = "common", .irq = 22 + OMAP_INTC_START, },
1171         { .name = "tx", .irq = 89 + OMAP_INTC_START, },
1172         { .name = "rx", .irq = 90 + OMAP_INTC_START, },
1173         { .irq = -1 },
1174 };
1175
1176 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1177         .sidetone       = "mcbsp3_sidetone",
1178 };
1179
1180 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1181         .name           = "mcbsp3",
1182         .class          = &omap3xxx_mcbsp_hwmod_class,
1183         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1184         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1185         .main_clk       = "mcbsp3_fck",
1186         .prcm           = {
1187                 .omap2 = {
1188                         .prcm_reg_id = 1,
1189                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1190                         .module_offs = OMAP3430_PER_MOD,
1191                         .idlest_reg_id = 1,
1192                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1193                 },
1194         },
1195         .opt_clks       = mcbsp234_opt_clks,
1196         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1197         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1198 };
1199
1200 /* mcbsp4 */
1201 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1202         { .name = "common", .irq = 23 + OMAP_INTC_START, },
1203         { .name = "tx", .irq = 54 + OMAP_INTC_START, },
1204         { .name = "rx", .irq = 55 + OMAP_INTC_START, },
1205         { .irq = -1 },
1206 };
1207
1208 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1209         { .name = "rx", .dma_req = 20 },
1210         { .name = "tx", .dma_req = 19 },
1211         { .dma_req = -1 }
1212 };
1213
1214 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1215         .name           = "mcbsp4",
1216         .class          = &omap3xxx_mcbsp_hwmod_class,
1217         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1218         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1219         .main_clk       = "mcbsp4_fck",
1220         .prcm           = {
1221                 .omap2 = {
1222                         .prcm_reg_id = 1,
1223                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1224                         .module_offs = OMAP3430_PER_MOD,
1225                         .idlest_reg_id = 1,
1226                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1227                 },
1228         },
1229         .opt_clks       = mcbsp234_opt_clks,
1230         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
1231 };
1232
1233 /* mcbsp5 */
1234 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1235         { .name = "common", .irq = 27 + OMAP_INTC_START, },
1236         { .name = "tx", .irq = 81 + OMAP_INTC_START, },
1237         { .name = "rx", .irq = 82 + OMAP_INTC_START, },
1238         { .irq = -1 },
1239 };
1240
1241 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1242         { .name = "rx", .dma_req = 22 },
1243         { .name = "tx", .dma_req = 21 },
1244         { .dma_req = -1 }
1245 };
1246
1247 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1248         .name           = "mcbsp5",
1249         .class          = &omap3xxx_mcbsp_hwmod_class,
1250         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1251         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1252         .main_clk       = "mcbsp5_fck",
1253         .prcm           = {
1254                 .omap2 = {
1255                         .prcm_reg_id = 1,
1256                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1257                         .module_offs = CORE_MOD,
1258                         .idlest_reg_id = 1,
1259                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1260                 },
1261         },
1262         .opt_clks       = mcbsp15_opt_clks,
1263         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
1264 };
1265
1266 /* 'mcbsp sidetone' class */
1267 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1268         .sysc_offs      = 0x0010,
1269         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1270         .sysc_fields    = &omap_hwmod_sysc_type1,
1271 };
1272
1273 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1274         .name = "mcbsp_sidetone",
1275         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1276 };
1277
1278 /* mcbsp2_sidetone */
1279 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1280         { .name = "irq", .irq = 4 + OMAP_INTC_START, },
1281         { .irq = -1 },
1282 };
1283
1284 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1285         .name           = "mcbsp2_sidetone",
1286         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1287         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1288         .main_clk       = "mcbsp2_fck",
1289         .prcm           = {
1290                 .omap2 = {
1291                         .prcm_reg_id = 1,
1292                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1293                         .module_offs = OMAP3430_PER_MOD,
1294                         .idlest_reg_id = 1,
1295                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1296                 },
1297         },
1298 };
1299
1300 /* mcbsp3_sidetone */
1301 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1302         { .name = "irq", .irq = 5 + OMAP_INTC_START, },
1303         { .irq = -1 },
1304 };
1305
1306 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1307         .name           = "mcbsp3_sidetone",
1308         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1309         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1310         .main_clk       = "mcbsp3_fck",
1311         .prcm           = {
1312                 .omap2 = {
1313                         .prcm_reg_id = 1,
1314                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1315                         .module_offs = OMAP3430_PER_MOD,
1316                         .idlest_reg_id = 1,
1317                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1318                 },
1319         },
1320 };
1321
1322 /* SR common */
1323 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1324         .clkact_shift   = 20,
1325 };
1326
1327 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1328         .sysc_offs      = 0x24,
1329         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1330         .clockact       = CLOCKACT_TEST_ICLK,
1331         .sysc_fields    = &omap34xx_sr_sysc_fields,
1332 };
1333
1334 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1335         .name = "smartreflex",
1336         .sysc = &omap34xx_sr_sysc,
1337         .rev  = 1,
1338 };
1339
1340 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1341         .sidle_shift    = 24,
1342         .enwkup_shift   = 26,
1343 };
1344
1345 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1346         .sysc_offs      = 0x38,
1347         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1348         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1349                         SYSC_NO_CACHE),
1350         .sysc_fields    = &omap36xx_sr_sysc_fields,
1351 };
1352
1353 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1354         .name = "smartreflex",
1355         .sysc = &omap36xx_sr_sysc,
1356         .rev  = 2,
1357 };
1358
1359 /* SR1 */
1360 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1361         .sensor_voltdm_name   = "mpu_iva",
1362 };
1363
1364 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1365         { .irq = 18 + OMAP_INTC_START, },
1366         { .irq = -1 },
1367 };
1368
1369 static struct omap_hwmod omap34xx_sr1_hwmod = {
1370         .name           = "smartreflex_mpu_iva",
1371         .class          = &omap34xx_smartreflex_hwmod_class,
1372         .main_clk       = "sr1_fck",
1373         .prcm           = {
1374                 .omap2 = {
1375                         .prcm_reg_id = 1,
1376                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1377                         .module_offs = WKUP_MOD,
1378                         .idlest_reg_id = 1,
1379                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1380                 },
1381         },
1382         .dev_attr       = &sr1_dev_attr,
1383         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1384         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1385 };
1386
1387 static struct omap_hwmod omap36xx_sr1_hwmod = {
1388         .name           = "smartreflex_mpu_iva",
1389         .class          = &omap36xx_smartreflex_hwmod_class,
1390         .main_clk       = "sr1_fck",
1391         .prcm           = {
1392                 .omap2 = {
1393                         .prcm_reg_id = 1,
1394                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1395                         .module_offs = WKUP_MOD,
1396                         .idlest_reg_id = 1,
1397                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1398                 },
1399         },
1400         .dev_attr       = &sr1_dev_attr,
1401         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1402 };
1403
1404 /* SR2 */
1405 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1406         .sensor_voltdm_name     = "core",
1407 };
1408
1409 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1410         { .irq = 19 + OMAP_INTC_START, },
1411         { .irq = -1 },
1412 };
1413
1414 static struct omap_hwmod omap34xx_sr2_hwmod = {
1415         .name           = "smartreflex_core",
1416         .class          = &omap34xx_smartreflex_hwmod_class,
1417         .main_clk       = "sr2_fck",
1418         .prcm           = {
1419                 .omap2 = {
1420                         .prcm_reg_id = 1,
1421                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1422                         .module_offs = WKUP_MOD,
1423                         .idlest_reg_id = 1,
1424                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1425                 },
1426         },
1427         .dev_attr       = &sr2_dev_attr,
1428         .mpu_irqs       = omap3_smartreflex_core_irqs,
1429         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1430 };
1431
1432 static struct omap_hwmod omap36xx_sr2_hwmod = {
1433         .name           = "smartreflex_core",
1434         .class          = &omap36xx_smartreflex_hwmod_class,
1435         .main_clk       = "sr2_fck",
1436         .prcm           = {
1437                 .omap2 = {
1438                         .prcm_reg_id = 1,
1439                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1440                         .module_offs = WKUP_MOD,
1441                         .idlest_reg_id = 1,
1442                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1443                 },
1444         },
1445         .dev_attr       = &sr2_dev_attr,
1446         .mpu_irqs       = omap3_smartreflex_core_irqs,
1447 };
1448
1449 /*
1450  * 'mailbox' class
1451  * mailbox module allowing communication between the on-chip processors
1452  * using a queued mailbox-interrupt mechanism.
1453  */
1454
1455 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1456         .rev_offs       = 0x000,
1457         .sysc_offs      = 0x010,
1458         .syss_offs      = 0x014,
1459         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1460                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1461         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1462         .sysc_fields    = &omap_hwmod_sysc_type1,
1463 };
1464
1465 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1466         .name = "mailbox",
1467         .sysc = &omap3xxx_mailbox_sysc,
1468 };
1469
1470 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1471         { .irq = 26 + OMAP_INTC_START, },
1472         { .irq = -1 },
1473 };
1474
1475 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1476         .name           = "mailbox",
1477         .class          = &omap3xxx_mailbox_hwmod_class,
1478         .mpu_irqs       = omap3xxx_mailbox_irqs,
1479         .main_clk       = "mailboxes_ick",
1480         .prcm           = {
1481                 .omap2 = {
1482                         .prcm_reg_id = 1,
1483                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1484                         .module_offs = CORE_MOD,
1485                         .idlest_reg_id = 1,
1486                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1487                 },
1488         },
1489 };
1490
1491 /*
1492  * 'mcspi' class
1493  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1494  * bus
1495  */
1496
1497 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1498         .rev_offs       = 0x0000,
1499         .sysc_offs      = 0x0010,
1500         .syss_offs      = 0x0014,
1501         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1502                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1503                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1504         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1505         .sysc_fields    = &omap_hwmod_sysc_type1,
1506 };
1507
1508 static struct omap_hwmod_class omap34xx_mcspi_class = {
1509         .name = "mcspi",
1510         .sysc = &omap34xx_mcspi_sysc,
1511         .rev = OMAP3_MCSPI_REV,
1512 };
1513
1514 /* mcspi1 */
1515 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1516         .num_chipselect = 4,
1517 };
1518
1519 static struct omap_hwmod omap34xx_mcspi1 = {
1520         .name           = "mcspi1",
1521         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1522         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1523         .main_clk       = "mcspi1_fck",
1524         .prcm           = {
1525                 .omap2 = {
1526                         .module_offs = CORE_MOD,
1527                         .prcm_reg_id = 1,
1528                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1529                         .idlest_reg_id = 1,
1530                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1531                 },
1532         },
1533         .class          = &omap34xx_mcspi_class,
1534         .dev_attr       = &omap_mcspi1_dev_attr,
1535 };
1536
1537 /* mcspi2 */
1538 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1539         .num_chipselect = 2,
1540 };
1541
1542 static struct omap_hwmod omap34xx_mcspi2 = {
1543         .name           = "mcspi2",
1544         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1545         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1546         .main_clk       = "mcspi2_fck",
1547         .prcm           = {
1548                 .omap2 = {
1549                         .module_offs = CORE_MOD,
1550                         .prcm_reg_id = 1,
1551                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1552                         .idlest_reg_id = 1,
1553                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1554                 },
1555         },
1556         .class          = &omap34xx_mcspi_class,
1557         .dev_attr       = &omap_mcspi2_dev_attr,
1558 };
1559
1560 /* mcspi3 */
1561 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1562         { .name = "irq", .irq = 91 + OMAP_INTC_START, }, /* 91 */
1563         { .irq = -1 },
1564 };
1565
1566 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1567         { .name = "tx0", .dma_req = 15 },
1568         { .name = "rx0", .dma_req = 16 },
1569         { .name = "tx1", .dma_req = 23 },
1570         { .name = "rx1", .dma_req = 24 },
1571         { .dma_req = -1 }
1572 };
1573
1574 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1575         .num_chipselect = 2,
1576 };
1577
1578 static struct omap_hwmod omap34xx_mcspi3 = {
1579         .name           = "mcspi3",
1580         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1581         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1582         .main_clk       = "mcspi3_fck",
1583         .prcm           = {
1584                 .omap2 = {
1585                         .module_offs = CORE_MOD,
1586                         .prcm_reg_id = 1,
1587                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1588                         .idlest_reg_id = 1,
1589                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1590                 },
1591         },
1592         .class          = &omap34xx_mcspi_class,
1593         .dev_attr       = &omap_mcspi3_dev_attr,
1594 };
1595
1596 /* mcspi4 */
1597 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1598         { .name = "irq", .irq = 48 + OMAP_INTC_START, },
1599         { .irq = -1 },
1600 };
1601
1602 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1603         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1604         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1605         { .dma_req = -1 }
1606 };
1607
1608 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1609         .num_chipselect = 1,
1610 };
1611
1612 static struct omap_hwmod omap34xx_mcspi4 = {
1613         .name           = "mcspi4",
1614         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1615         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1616         .main_clk       = "mcspi4_fck",
1617         .prcm           = {
1618                 .omap2 = {
1619                         .module_offs = CORE_MOD,
1620                         .prcm_reg_id = 1,
1621                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1622                         .idlest_reg_id = 1,
1623                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1624                 },
1625         },
1626         .class          = &omap34xx_mcspi_class,
1627         .dev_attr       = &omap_mcspi4_dev_attr,
1628 };
1629
1630 /* usbhsotg */
1631 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1632         .rev_offs       = 0x0400,
1633         .sysc_offs      = 0x0404,
1634         .syss_offs      = 0x0408,
1635         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1636                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1637                           SYSC_HAS_AUTOIDLE),
1638         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1639                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1640         .sysc_fields    = &omap_hwmod_sysc_type1,
1641 };
1642
1643 static struct omap_hwmod_class usbotg_class = {
1644         .name = "usbotg",
1645         .sysc = &omap3xxx_usbhsotg_sysc,
1646 };
1647
1648 /* usb_otg_hs */
1649 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1650
1651         { .name = "mc", .irq = 92 + OMAP_INTC_START, },
1652         { .name = "dma", .irq = 93 + OMAP_INTC_START, },
1653         { .irq = -1 },
1654 };
1655
1656 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1657         .name           = "usb_otg_hs",
1658         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1659         .main_clk       = "hsotgusb_ick",
1660         .prcm           = {
1661                 .omap2 = {
1662                         .prcm_reg_id = 1,
1663                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1664                         .module_offs = CORE_MOD,
1665                         .idlest_reg_id = 1,
1666                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1667                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1668                 },
1669         },
1670         .class          = &usbotg_class,
1671
1672         /*
1673          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1674          * broken when autoidle is enabled
1675          * workaround is to disable the autoidle bit at module level.
1676          */
1677         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1678                                 | HWMOD_SWSUP_MSTANDBY,
1679 };
1680
1681 /* usb_otg_hs */
1682 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1683         { .name = "mc", .irq = 71 + OMAP_INTC_START, },
1684         { .irq = -1 },
1685 };
1686
1687 static struct omap_hwmod_class am35xx_usbotg_class = {
1688         .name = "am35xx_usbotg",
1689 };
1690
1691 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1692         .name           = "am35x_otg_hs",
1693         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1694         .main_clk       = "hsotgusb_fck",
1695         .class          = &am35xx_usbotg_class,
1696         .flags          = HWMOD_NO_IDLEST,
1697 };
1698
1699 /* MMC/SD/SDIO common */
1700 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1701         .rev_offs       = 0x1fc,
1702         .sysc_offs      = 0x10,
1703         .syss_offs      = 0x14,
1704         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1705                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1706                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1707         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1708         .sysc_fields    = &omap_hwmod_sysc_type1,
1709 };
1710
1711 static struct omap_hwmod_class omap34xx_mmc_class = {
1712         .name = "mmc",
1713         .sysc = &omap34xx_mmc_sysc,
1714 };
1715
1716 /* MMC/SD/SDIO1 */
1717
1718 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1719         { .irq = 83 + OMAP_INTC_START, },
1720         { .irq = -1 },
1721 };
1722
1723 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1724         { .name = "tx", .dma_req = 61, },
1725         { .name = "rx", .dma_req = 62, },
1726         { .dma_req = -1 }
1727 };
1728
1729 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1730         { .role = "dbck", .clk = "omap_32k_fck", },
1731 };
1732
1733 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1734         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1735 };
1736
1737 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1738 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1739         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1740                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1741 };
1742
1743 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1744         .name           = "mmc1",
1745         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1746         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1747         .opt_clks       = omap34xx_mmc1_opt_clks,
1748         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1749         .main_clk       = "mmchs1_fck",
1750         .prcm           = {
1751                 .omap2 = {
1752                         .module_offs = CORE_MOD,
1753                         .prcm_reg_id = 1,
1754                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1755                         .idlest_reg_id = 1,
1756                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1757                 },
1758         },
1759         .dev_attr       = &mmc1_pre_es3_dev_attr,
1760         .class          = &omap34xx_mmc_class,
1761 };
1762
1763 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1764         .name           = "mmc1",
1765         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1766         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1767         .opt_clks       = omap34xx_mmc1_opt_clks,
1768         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1769         .main_clk       = "mmchs1_fck",
1770         .prcm           = {
1771                 .omap2 = {
1772                         .module_offs = CORE_MOD,
1773                         .prcm_reg_id = 1,
1774                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1775                         .idlest_reg_id = 1,
1776                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1777                 },
1778         },
1779         .dev_attr       = &mmc1_dev_attr,
1780         .class          = &omap34xx_mmc_class,
1781 };
1782
1783 /* MMC/SD/SDIO2 */
1784
1785 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1786         { .irq = 86 + OMAP_INTC_START, },
1787         { .irq = -1 },
1788 };
1789
1790 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1791         { .name = "tx", .dma_req = 47, },
1792         { .name = "rx", .dma_req = 48, },
1793         { .dma_req = -1 }
1794 };
1795
1796 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1797         { .role = "dbck", .clk = "omap_32k_fck", },
1798 };
1799
1800 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1801 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1802         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1803 };
1804
1805 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1806         .name           = "mmc2",
1807         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1808         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1809         .opt_clks       = omap34xx_mmc2_opt_clks,
1810         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1811         .main_clk       = "mmchs2_fck",
1812         .prcm           = {
1813                 .omap2 = {
1814                         .module_offs = CORE_MOD,
1815                         .prcm_reg_id = 1,
1816                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1817                         .idlest_reg_id = 1,
1818                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1819                 },
1820         },
1821         .dev_attr       = &mmc2_pre_es3_dev_attr,
1822         .class          = &omap34xx_mmc_class,
1823 };
1824
1825 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1826         .name           = "mmc2",
1827         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1828         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1829         .opt_clks       = omap34xx_mmc2_opt_clks,
1830         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1831         .main_clk       = "mmchs2_fck",
1832         .prcm           = {
1833                 .omap2 = {
1834                         .module_offs = CORE_MOD,
1835                         .prcm_reg_id = 1,
1836                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1837                         .idlest_reg_id = 1,
1838                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1839                 },
1840         },
1841         .class          = &omap34xx_mmc_class,
1842 };
1843
1844 /* MMC/SD/SDIO3 */
1845
1846 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1847         { .irq = 94 + OMAP_INTC_START, },
1848         { .irq = -1 },
1849 };
1850
1851 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1852         { .name = "tx", .dma_req = 77, },
1853         { .name = "rx", .dma_req = 78, },
1854         { .dma_req = -1 }
1855 };
1856
1857 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1858         { .role = "dbck", .clk = "omap_32k_fck", },
1859 };
1860
1861 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1862         .name           = "mmc3",
1863         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1864         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1865         .opt_clks       = omap34xx_mmc3_opt_clks,
1866         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1867         .main_clk       = "mmchs3_fck",
1868         .prcm           = {
1869                 .omap2 = {
1870                         .prcm_reg_id = 1,
1871                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1872                         .idlest_reg_id = 1,
1873                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1874                 },
1875         },
1876         .class          = &omap34xx_mmc_class,
1877 };
1878
1879 /*
1880  * 'usb_host_hs' class
1881  * high-speed multi-port usb host controller
1882  */
1883
1884 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1885         .rev_offs       = 0x0000,
1886         .sysc_offs      = 0x0010,
1887         .syss_offs      = 0x0014,
1888         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1889                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1890                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1891         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1892                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1893         .sysc_fields    = &omap_hwmod_sysc_type1,
1894 };
1895
1896 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1897         .name = "usb_host_hs",
1898         .sysc = &omap3xxx_usb_host_hs_sysc,
1899 };
1900
1901 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1902           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1903 };
1904
1905 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1906         { .name = "ohci-irq", .irq = 76 + OMAP_INTC_START, },
1907         { .name = "ehci-irq", .irq = 77 + OMAP_INTC_START, },
1908         { .irq = -1 },
1909 };
1910
1911 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1912         .name           = "usb_host_hs",
1913         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1914         .clkdm_name     = "l3_init_clkdm",
1915         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1916         .main_clk       = "usbhost_48m_fck",
1917         .prcm = {
1918                 .omap2 = {
1919                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1920                         .prcm_reg_id = 1,
1921                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1922                         .idlest_reg_id = 1,
1923                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1924                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1925                 },
1926         },
1927         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
1928         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1929
1930         /*
1931          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1932          * id: i660
1933          *
1934          * Description:
1935          * In the following configuration :
1936          * - USBHOST module is set to smart-idle mode
1937          * - PRCM asserts idle_req to the USBHOST module ( This typically
1938          *   happens when the system is going to a low power mode : all ports
1939          *   have been suspended, the master part of the USBHOST module has
1940          *   entered the standby state, and SW has cut the functional clocks)
1941          * - an USBHOST interrupt occurs before the module is able to answer
1942          *   idle_ack, typically a remote wakeup IRQ.
1943          * Then the USB HOST module will enter a deadlock situation where it
1944          * is no more accessible nor functional.
1945          *
1946          * Workaround:
1947          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1948          */
1949
1950         /*
1951          * Errata: USB host EHCI may stall when entering smart-standby mode
1952          * Id: i571
1953          *
1954          * Description:
1955          * When the USBHOST module is set to smart-standby mode, and when it is
1956          * ready to enter the standby state (i.e. all ports are suspended and
1957          * all attached devices are in suspend mode), then it can wrongly assert
1958          * the Mstandby signal too early while there are still some residual OCP
1959          * transactions ongoing. If this condition occurs, the internal state
1960          * machine may go to an undefined state and the USB link may be stuck
1961          * upon the next resume.
1962          *
1963          * Workaround:
1964          * Don't use smart standby; use only force standby,
1965          * hence HWMOD_SWSUP_MSTANDBY
1966          */
1967
1968         /*
1969          * During system boot; If the hwmod framework resets the module
1970          * the module will have smart idle settings; which can lead to deadlock
1971          * (above Errata Id:i660); so, dont reset the module during boot;
1972          * Use HWMOD_INIT_NO_RESET.
1973          */
1974
1975         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1976                           HWMOD_INIT_NO_RESET,
1977 };
1978
1979 /*
1980  * 'usb_tll_hs' class
1981  * usb_tll_hs module is the adapter on the usb_host_hs ports
1982  */
1983 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1984         .rev_offs       = 0x0000,
1985         .sysc_offs      = 0x0010,
1986         .syss_offs      = 0x0014,
1987         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1988                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1989                            SYSC_HAS_AUTOIDLE),
1990         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1991         .sysc_fields    = &omap_hwmod_sysc_type1,
1992 };
1993
1994 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1995         .name = "usb_tll_hs",
1996         .sysc = &omap3xxx_usb_tll_hs_sysc,
1997 };
1998
1999 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
2000         { .name = "tll-irq", .irq = 78 + OMAP_INTC_START, },
2001         { .irq = -1 },
2002 };
2003
2004 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
2005         .name           = "usb_tll_hs",
2006         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
2007         .clkdm_name     = "l3_init_clkdm",
2008         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
2009         .main_clk       = "usbtll_fck",
2010         .prcm = {
2011                 .omap2 = {
2012                         .module_offs = CORE_MOD,
2013                         .prcm_reg_id = 3,
2014                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
2015                         .idlest_reg_id = 3,
2016                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
2017                 },
2018         },
2019 };
2020
2021 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
2022         .name           = "hdq1w",
2023         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2024         .main_clk       = "hdq_fck",
2025         .prcm           = {
2026                 .omap2 = {
2027                         .module_offs = CORE_MOD,
2028                         .prcm_reg_id = 1,
2029                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2030                         .idlest_reg_id = 1,
2031                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2032                 },
2033         },
2034         .class          = &omap2_hdq1w_class,
2035 };
2036
2037 /* SAD2D */
2038 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
2039         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
2040         { .name = "rst_modem_sw", .rst_shift = 1 },
2041 };
2042
2043 static struct omap_hwmod_class omap3xxx_sad2d_class = {
2044         .name                   = "sad2d",
2045 };
2046
2047 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
2048         .name           = "sad2d",
2049         .rst_lines      = omap3xxx_sad2d_resets,
2050         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
2051         .main_clk       = "sad2d_ick",
2052         .prcm           = {
2053                 .omap2 = {
2054                         .module_offs = CORE_MOD,
2055                         .prcm_reg_id = 1,
2056                         .module_bit = OMAP3430_EN_SAD2D_SHIFT,
2057                         .idlest_reg_id = 1,
2058                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
2059                 },
2060         },
2061         .class          = &omap3xxx_sad2d_class,
2062 };
2063
2064 /*
2065  * '32K sync counter' class
2066  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2067  */
2068 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2069         .rev_offs       = 0x0000,
2070         .sysc_offs      = 0x0004,
2071         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2072         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2073         .sysc_fields    = &omap_hwmod_sysc_type1,
2074 };
2075
2076 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2077         .name   = "counter",
2078         .sysc   = &omap3xxx_counter_sysc,
2079 };
2080
2081 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2082         .name           = "counter_32k",
2083         .class          = &omap3xxx_counter_hwmod_class,
2084         .clkdm_name     = "wkup_clkdm",
2085         .flags          = HWMOD_SWSUP_SIDLE,
2086         .main_clk       = "wkup_32k_fck",
2087         .prcm           = {
2088                 .omap2  = {
2089                         .module_offs = WKUP_MOD,
2090                         .prcm_reg_id = 1,
2091                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2092                         .idlest_reg_id = 1,
2093                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2094                 },
2095         },
2096 };
2097
2098 /*
2099  * 'gpmc' class
2100  * general purpose memory controller
2101  */
2102
2103 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
2104         .rev_offs       = 0x0000,
2105         .sysc_offs      = 0x0010,
2106         .syss_offs      = 0x0014,
2107         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2108                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2109         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2110         .sysc_fields    = &omap_hwmod_sysc_type1,
2111 };
2112
2113 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
2114         .name   = "gpmc",
2115         .sysc   = &omap3xxx_gpmc_sysc,
2116 };
2117
2118 static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
2119         { .irq = 20 },
2120         { .irq = -1 }
2121 };
2122
2123 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
2124         .name           = "gpmc",
2125         .class          = &omap3xxx_gpmc_hwmod_class,
2126         .clkdm_name     = "core_l3_clkdm",
2127         .mpu_irqs       = omap3xxx_gpmc_irqs,
2128         .main_clk       = "gpmc_fck",
2129         /*
2130          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
2131          * block.  It is not being added due to any known bugs with
2132          * resetting the GPMC IP block, but rather because any timings
2133          * set by the bootloader are not being correctly programmed by
2134          * the kernel from the board file or DT data.
2135          * HWMOD_INIT_NO_RESET should be removed ASAP.
2136          */
2137         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
2138                            HWMOD_NO_IDLEST),
2139 };
2140
2141 /*
2142  * interfaces
2143  */
2144
2145 /* L3 -> L4_CORE interface */
2146 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2147         .master = &omap3xxx_l3_main_hwmod,
2148         .slave  = &omap3xxx_l4_core_hwmod,
2149         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2150 };
2151
2152 /* L3 -> L4_PER interface */
2153 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2154         .master = &omap3xxx_l3_main_hwmod,
2155         .slave  = &omap3xxx_l4_per_hwmod,
2156         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2157 };
2158
2159 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2160         {
2161                 .pa_start       = 0x68000000,
2162                 .pa_end         = 0x6800ffff,
2163                 .flags          = ADDR_TYPE_RT,
2164         },
2165         { }
2166 };
2167
2168 /* MPU -> L3 interface */
2169 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2170         .master   = &omap3xxx_mpu_hwmod,
2171         .slave    = &omap3xxx_l3_main_hwmod,
2172         .addr     = omap3xxx_l3_main_addrs,
2173         .user   = OCP_USER_MPU,
2174 };
2175
2176 /* DSS -> l3 */
2177 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2178         .master         = &omap3430es1_dss_core_hwmod,
2179         .slave          = &omap3xxx_l3_main_hwmod,
2180         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2181 };
2182
2183 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2184         .master         = &omap3xxx_dss_core_hwmod,
2185         .slave          = &omap3xxx_l3_main_hwmod,
2186         .fw = {
2187                 .omap2 = {
2188                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2189                         .flags  = OMAP_FIREWALL_L3,
2190                 }
2191         },
2192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2193 };
2194
2195 /* l3_core -> usbhsotg interface */
2196 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2197         .master         = &omap3xxx_usbhsotg_hwmod,
2198         .slave          = &omap3xxx_l3_main_hwmod,
2199         .clk            = "core_l3_ick",
2200         .user           = OCP_USER_MPU,
2201 };
2202
2203 /* l3_core -> am35xx_usbhsotg interface */
2204 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2205         .master         = &am35xx_usbhsotg_hwmod,
2206         .slave          = &omap3xxx_l3_main_hwmod,
2207         .clk            = "hsotgusb_ick",
2208         .user           = OCP_USER_MPU,
2209 };
2210
2211 /* l3_core -> sad2d interface */
2212 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
2213         .master         = &omap3xxx_sad2d_hwmod,
2214         .slave          = &omap3xxx_l3_main_hwmod,
2215         .clk            = "core_l3_ick",
2216         .user           = OCP_USER_MPU,
2217 };
2218
2219 /* L4_CORE -> L4_WKUP interface */
2220 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2221         .master = &omap3xxx_l4_core_hwmod,
2222         .slave  = &omap3xxx_l4_wkup_hwmod,
2223         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2224 };
2225
2226 /* L4 CORE -> MMC1 interface */
2227 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2228         .master         = &omap3xxx_l4_core_hwmod,
2229         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2230         .clk            = "mmchs1_ick",
2231         .addr           = omap2430_mmc1_addr_space,
2232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2233         .flags          = OMAP_FIREWALL_L4
2234 };
2235
2236 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2237         .master         = &omap3xxx_l4_core_hwmod,
2238         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2239         .clk            = "mmchs1_ick",
2240         .addr           = omap2430_mmc1_addr_space,
2241         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2242         .flags          = OMAP_FIREWALL_L4
2243 };
2244
2245 /* L4 CORE -> MMC2 interface */
2246 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2247         .master         = &omap3xxx_l4_core_hwmod,
2248         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2249         .clk            = "mmchs2_ick",
2250         .addr           = omap2430_mmc2_addr_space,
2251         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2252         .flags          = OMAP_FIREWALL_L4
2253 };
2254
2255 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2256         .master         = &omap3xxx_l4_core_hwmod,
2257         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2258         .clk            = "mmchs2_ick",
2259         .addr           = omap2430_mmc2_addr_space,
2260         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2261         .flags          = OMAP_FIREWALL_L4
2262 };
2263
2264 /* L4 CORE -> MMC3 interface */
2265 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2266         {
2267                 .pa_start       = 0x480ad000,
2268                 .pa_end         = 0x480ad1ff,
2269                 .flags          = ADDR_TYPE_RT,
2270         },
2271         { }
2272 };
2273
2274 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2275         .master         = &omap3xxx_l4_core_hwmod,
2276         .slave          = &omap3xxx_mmc3_hwmod,
2277         .clk            = "mmchs3_ick",
2278         .addr           = omap3xxx_mmc3_addr_space,
2279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2280         .flags          = OMAP_FIREWALL_L4
2281 };
2282
2283 /* L4 CORE -> UART1 interface */
2284 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2285         {
2286                 .pa_start       = OMAP3_UART1_BASE,
2287                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2288                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2289         },
2290         { }
2291 };
2292
2293 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2294         .master         = &omap3xxx_l4_core_hwmod,
2295         .slave          = &omap3xxx_uart1_hwmod,
2296         .clk            = "uart1_ick",
2297         .addr           = omap3xxx_uart1_addr_space,
2298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2299 };
2300
2301 /* L4 CORE -> UART2 interface */
2302 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2303         {
2304                 .pa_start       = OMAP3_UART2_BASE,
2305                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2306                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2307         },
2308         { }
2309 };
2310
2311 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2312         .master         = &omap3xxx_l4_core_hwmod,
2313         .slave          = &omap3xxx_uart2_hwmod,
2314         .clk            = "uart2_ick",
2315         .addr           = omap3xxx_uart2_addr_space,
2316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2317 };
2318
2319 /* L4 PER -> UART3 interface */
2320 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2321         {
2322                 .pa_start       = OMAP3_UART3_BASE,
2323                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2324                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2325         },
2326         { }
2327 };
2328
2329 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2330         .master         = &omap3xxx_l4_per_hwmod,
2331         .slave          = &omap3xxx_uart3_hwmod,
2332         .clk            = "uart3_ick",
2333         .addr           = omap3xxx_uart3_addr_space,
2334         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2335 };
2336
2337 /* L4 PER -> UART4 interface */
2338 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2339         {
2340                 .pa_start       = OMAP3_UART4_BASE,
2341                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2342                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2343         },
2344         { }
2345 };
2346
2347 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2348         .master         = &omap3xxx_l4_per_hwmod,
2349         .slave          = &omap36xx_uart4_hwmod,
2350         .clk            = "uart4_ick",
2351         .addr           = omap36xx_uart4_addr_space,
2352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2353 };
2354
2355 /* AM35xx: L4 CORE -> UART4 interface */
2356 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2357         {
2358                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2359                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2360                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2361         },
2362         { }
2363 };
2364
2365 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2366         .master         = &omap3xxx_l4_core_hwmod,
2367         .slave          = &am35xx_uart4_hwmod,
2368         .clk            = "uart4_ick",
2369         .addr           = am35xx_uart4_addr_space,
2370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2371 };
2372
2373 /* L4 CORE -> I2C1 interface */
2374 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2375         .master         = &omap3xxx_l4_core_hwmod,
2376         .slave          = &omap3xxx_i2c1_hwmod,
2377         .clk            = "i2c1_ick",
2378         .addr           = omap2_i2c1_addr_space,
2379         .fw = {
2380                 .omap2 = {
2381                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2382                         .l4_prot_group = 7,
2383                         .flags  = OMAP_FIREWALL_L4,
2384                 }
2385         },
2386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2387 };
2388
2389 /* L4 CORE -> I2C2 interface */
2390 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2391         .master         = &omap3xxx_l4_core_hwmod,
2392         .slave          = &omap3xxx_i2c2_hwmod,
2393         .clk            = "i2c2_ick",
2394         .addr           = omap2_i2c2_addr_space,
2395         .fw = {
2396                 .omap2 = {
2397                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2398                         .l4_prot_group = 7,
2399                         .flags = OMAP_FIREWALL_L4,
2400                 }
2401         },
2402         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2403 };
2404
2405 /* L4 CORE -> I2C3 interface */
2406 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2407         {
2408                 .pa_start       = 0x48060000,
2409                 .pa_end         = 0x48060000 + SZ_128 - 1,
2410                 .flags          = ADDR_TYPE_RT,
2411         },
2412         { }
2413 };
2414
2415 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2416         .master         = &omap3xxx_l4_core_hwmod,
2417         .slave          = &omap3xxx_i2c3_hwmod,
2418         .clk            = "i2c3_ick",
2419         .addr           = omap3xxx_i2c3_addr_space,
2420         .fw = {
2421                 .omap2 = {
2422                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2423                         .l4_prot_group = 7,
2424                         .flags = OMAP_FIREWALL_L4,
2425                 }
2426         },
2427         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2428 };
2429
2430 /* L4 CORE -> SR1 interface */
2431 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2432         {
2433                 .pa_start       = OMAP34XX_SR1_BASE,
2434                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2435                 .flags          = ADDR_TYPE_RT,
2436         },
2437         { }
2438 };
2439
2440 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2441         .master         = &omap3xxx_l4_core_hwmod,
2442         .slave          = &omap34xx_sr1_hwmod,
2443         .clk            = "sr_l4_ick",
2444         .addr           = omap3_sr1_addr_space,
2445         .user           = OCP_USER_MPU,
2446 };
2447
2448 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2449         .master         = &omap3xxx_l4_core_hwmod,
2450         .slave          = &omap36xx_sr1_hwmod,
2451         .clk            = "sr_l4_ick",
2452         .addr           = omap3_sr1_addr_space,
2453         .user           = OCP_USER_MPU,
2454 };
2455
2456 /* L4 CORE -> SR1 interface */
2457 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2458         {
2459                 .pa_start       = OMAP34XX_SR2_BASE,
2460                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2461                 .flags          = ADDR_TYPE_RT,
2462         },
2463         { }
2464 };
2465
2466 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2467         .master         = &omap3xxx_l4_core_hwmod,
2468         .slave          = &omap34xx_sr2_hwmod,
2469         .clk            = "sr_l4_ick",
2470         .addr           = omap3_sr2_addr_space,
2471         .user           = OCP_USER_MPU,
2472 };
2473
2474 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2475         .master         = &omap3xxx_l4_core_hwmod,
2476         .slave          = &omap36xx_sr2_hwmod,
2477         .clk            = "sr_l4_ick",
2478         .addr           = omap3_sr2_addr_space,
2479         .user           = OCP_USER_MPU,
2480 };
2481
2482 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2483         {
2484                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2485                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2486                 .flags          = ADDR_TYPE_RT
2487         },
2488         { }
2489 };
2490
2491 /* l4_core -> usbhsotg  */
2492 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2493         .master         = &omap3xxx_l4_core_hwmod,
2494         .slave          = &omap3xxx_usbhsotg_hwmod,
2495         .clk            = "l4_ick",
2496         .addr           = omap3xxx_usbhsotg_addrs,
2497         .user           = OCP_USER_MPU,
2498 };
2499
2500 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2501         {
2502                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2503                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2504                 .flags          = ADDR_TYPE_RT
2505         },
2506         { }
2507 };
2508
2509 /* l4_core -> usbhsotg  */
2510 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2511         .master         = &omap3xxx_l4_core_hwmod,
2512         .slave          = &am35xx_usbhsotg_hwmod,
2513         .clk            = "hsotgusb_ick",
2514         .addr           = am35xx_usbhsotg_addrs,
2515         .user           = OCP_USER_MPU,
2516 };
2517
2518 /* L4_WKUP -> L4_SEC interface */
2519 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2520         .master = &omap3xxx_l4_wkup_hwmod,
2521         .slave  = &omap3xxx_l4_sec_hwmod,
2522         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2523 };
2524
2525 /* IVA2 <- L3 interface */
2526 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2527         .master         = &omap3xxx_l3_main_hwmod,
2528         .slave          = &omap3xxx_iva_hwmod,
2529         .clk            = "core_l3_ick",
2530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2531 };
2532
2533 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2534         {
2535                 .pa_start       = 0x48318000,
2536                 .pa_end         = 0x48318000 + SZ_1K - 1,
2537                 .flags          = ADDR_TYPE_RT
2538         },
2539         { }
2540 };
2541
2542 /* l4_wkup -> timer1 */
2543 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2544         .master         = &omap3xxx_l4_wkup_hwmod,
2545         .slave          = &omap3xxx_timer1_hwmod,
2546         .clk            = "gpt1_ick",
2547         .addr           = omap3xxx_timer1_addrs,
2548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2549 };
2550
2551 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2552         {
2553                 .pa_start       = 0x49032000,
2554                 .pa_end         = 0x49032000 + SZ_1K - 1,
2555                 .flags          = ADDR_TYPE_RT
2556         },
2557         { }
2558 };
2559
2560 /* l4_per -> timer2 */
2561 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2562         .master         = &omap3xxx_l4_per_hwmod,
2563         .slave          = &omap3xxx_timer2_hwmod,
2564         .clk            = "gpt2_ick",
2565         .addr           = omap3xxx_timer2_addrs,
2566         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2567 };
2568
2569 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2570         {
2571                 .pa_start       = 0x49034000,
2572                 .pa_end         = 0x49034000 + SZ_1K - 1,
2573                 .flags          = ADDR_TYPE_RT
2574         },
2575         { }
2576 };
2577
2578 /* l4_per -> timer3 */
2579 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2580         .master         = &omap3xxx_l4_per_hwmod,
2581         .slave          = &omap3xxx_timer3_hwmod,
2582         .clk            = "gpt3_ick",
2583         .addr           = omap3xxx_timer3_addrs,
2584         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2585 };
2586
2587 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2588         {
2589                 .pa_start       = 0x49036000,
2590                 .pa_end         = 0x49036000 + SZ_1K - 1,
2591                 .flags          = ADDR_TYPE_RT
2592         },
2593         { }
2594 };
2595
2596 /* l4_per -> timer4 */
2597 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2598         .master         = &omap3xxx_l4_per_hwmod,
2599         .slave          = &omap3xxx_timer4_hwmod,
2600         .clk            = "gpt4_ick",
2601         .addr           = omap3xxx_timer4_addrs,
2602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2603 };
2604
2605 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2606         {
2607                 .pa_start       = 0x49038000,
2608                 .pa_end         = 0x49038000 + SZ_1K - 1,
2609                 .flags          = ADDR_TYPE_RT
2610         },
2611         { }
2612 };
2613
2614 /* l4_per -> timer5 */
2615 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2616         .master         = &omap3xxx_l4_per_hwmod,
2617         .slave          = &omap3xxx_timer5_hwmod,
2618         .clk            = "gpt5_ick",
2619         .addr           = omap3xxx_timer5_addrs,
2620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2621 };
2622
2623 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2624         {
2625                 .pa_start       = 0x4903A000,
2626                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2627                 .flags          = ADDR_TYPE_RT
2628         },
2629         { }
2630 };
2631
2632 /* l4_per -> timer6 */
2633 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2634         .master         = &omap3xxx_l4_per_hwmod,
2635         .slave          = &omap3xxx_timer6_hwmod,
2636         .clk            = "gpt6_ick",
2637         .addr           = omap3xxx_timer6_addrs,
2638         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2639 };
2640
2641 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2642         {
2643                 .pa_start       = 0x4903C000,
2644                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2645                 .flags          = ADDR_TYPE_RT
2646         },
2647         { }
2648 };
2649
2650 /* l4_per -> timer7 */
2651 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2652         .master         = &omap3xxx_l4_per_hwmod,
2653         .slave          = &omap3xxx_timer7_hwmod,
2654         .clk            = "gpt7_ick",
2655         .addr           = omap3xxx_timer7_addrs,
2656         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2657 };
2658
2659 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2660         {
2661                 .pa_start       = 0x4903E000,
2662                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2663                 .flags          = ADDR_TYPE_RT
2664         },
2665         { }
2666 };
2667
2668 /* l4_per -> timer8 */
2669 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2670         .master         = &omap3xxx_l4_per_hwmod,
2671         .slave          = &omap3xxx_timer8_hwmod,
2672         .clk            = "gpt8_ick",
2673         .addr           = omap3xxx_timer8_addrs,
2674         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2675 };
2676
2677 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2678         {
2679                 .pa_start       = 0x49040000,
2680                 .pa_end         = 0x49040000 + SZ_1K - 1,
2681                 .flags          = ADDR_TYPE_RT
2682         },
2683         { }
2684 };
2685
2686 /* l4_per -> timer9 */
2687 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2688         .master         = &omap3xxx_l4_per_hwmod,
2689         .slave          = &omap3xxx_timer9_hwmod,
2690         .clk            = "gpt9_ick",
2691         .addr           = omap3xxx_timer9_addrs,
2692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2693 };
2694
2695 /* l4_core -> timer10 */
2696 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2697         .master         = &omap3xxx_l4_core_hwmod,
2698         .slave          = &omap3xxx_timer10_hwmod,
2699         .clk            = "gpt10_ick",
2700         .addr           = omap2_timer10_addrs,
2701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2702 };
2703
2704 /* l4_core -> timer11 */
2705 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2706         .master         = &omap3xxx_l4_core_hwmod,
2707         .slave          = &omap3xxx_timer11_hwmod,
2708         .clk            = "gpt11_ick",
2709         .addr           = omap2_timer11_addrs,
2710         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2711 };
2712
2713 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2714         {
2715                 .pa_start       = 0x48304000,
2716                 .pa_end         = 0x48304000 + SZ_1K - 1,
2717                 .flags          = ADDR_TYPE_RT
2718         },
2719         { }
2720 };
2721
2722 /* l4_core -> timer12 */
2723 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2724         .master         = &omap3xxx_l4_sec_hwmod,
2725         .slave          = &omap3xxx_timer12_hwmod,
2726         .clk            = "gpt12_ick",
2727         .addr           = omap3xxx_timer12_addrs,
2728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2729 };
2730
2731 /* l4_wkup -> wd_timer2 */
2732 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2733         {
2734                 .pa_start       = 0x48314000,
2735                 .pa_end         = 0x4831407f,
2736                 .flags          = ADDR_TYPE_RT
2737         },
2738         { }
2739 };
2740
2741 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2742         .master         = &omap3xxx_l4_wkup_hwmod,
2743         .slave          = &omap3xxx_wd_timer2_hwmod,
2744         .clk            = "wdt2_ick",
2745         .addr           = omap3xxx_wd_timer2_addrs,
2746         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2747 };
2748
2749 /* l4_core -> dss */
2750 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2751         .master         = &omap3xxx_l4_core_hwmod,
2752         .slave          = &omap3430es1_dss_core_hwmod,
2753         .clk            = "dss_ick",
2754         .addr           = omap2_dss_addrs,
2755         .fw = {
2756                 .omap2 = {
2757                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2758                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2759                         .flags  = OMAP_FIREWALL_L4,
2760                 }
2761         },
2762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2763 };
2764
2765 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2766         .master         = &omap3xxx_l4_core_hwmod,
2767         .slave          = &omap3xxx_dss_core_hwmod,
2768         .clk            = "dss_ick",
2769         .addr           = omap2_dss_addrs,
2770         .fw = {
2771                 .omap2 = {
2772                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2773                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2774                         .flags  = OMAP_FIREWALL_L4,
2775                 }
2776         },
2777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2778 };
2779
2780 /* l4_core -> dss_dispc */
2781 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2782         .master         = &omap3xxx_l4_core_hwmod,
2783         .slave          = &omap3xxx_dss_dispc_hwmod,
2784         .clk            = "dss_ick",
2785         .addr           = omap2_dss_dispc_addrs,
2786         .fw = {
2787                 .omap2 = {
2788                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2789                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2790                         .flags  = OMAP_FIREWALL_L4,
2791                 }
2792         },
2793         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2794 };
2795
2796 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2797         {
2798                 .pa_start       = 0x4804FC00,
2799                 .pa_end         = 0x4804FFFF,
2800                 .flags          = ADDR_TYPE_RT
2801         },
2802         { }
2803 };
2804
2805 /* l4_core -> dss_dsi1 */
2806 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2807         .master         = &omap3xxx_l4_core_hwmod,
2808         .slave          = &omap3xxx_dss_dsi1_hwmod,
2809         .clk            = "dss_ick",
2810         .addr           = omap3xxx_dss_dsi1_addrs,
2811         .fw = {
2812                 .omap2 = {
2813                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2814                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2815                         .flags  = OMAP_FIREWALL_L4,
2816                 }
2817         },
2818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2819 };
2820
2821 /* l4_core -> dss_rfbi */
2822 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2823         .master         = &omap3xxx_l4_core_hwmod,
2824         .slave          = &omap3xxx_dss_rfbi_hwmod,
2825         .clk            = "dss_ick",
2826         .addr           = omap2_dss_rfbi_addrs,
2827         .fw = {
2828                 .omap2 = {
2829                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2830                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2831                         .flags  = OMAP_FIREWALL_L4,
2832                 }
2833         },
2834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2835 };
2836
2837 /* l4_core -> dss_venc */
2838 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2839         .master         = &omap3xxx_l4_core_hwmod,
2840         .slave          = &omap3xxx_dss_venc_hwmod,
2841         .clk            = "dss_ick",
2842         .addr           = omap2_dss_venc_addrs,
2843         .fw = {
2844                 .omap2 = {
2845                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2846                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2847                         .flags  = OMAP_FIREWALL_L4,
2848                 }
2849         },
2850         .flags          = OCPIF_SWSUP_IDLE,
2851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2852 };
2853
2854 /* l4_wkup -> gpio1 */
2855 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2856         {
2857                 .pa_start       = 0x48310000,
2858                 .pa_end         = 0x483101ff,
2859                 .flags          = ADDR_TYPE_RT
2860         },
2861         { }
2862 };
2863
2864 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2865         .master         = &omap3xxx_l4_wkup_hwmod,
2866         .slave          = &omap3xxx_gpio1_hwmod,
2867         .addr           = omap3xxx_gpio1_addrs,
2868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2869 };
2870
2871 /* l4_per -> gpio2 */
2872 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2873         {
2874                 .pa_start       = 0x49050000,
2875                 .pa_end         = 0x490501ff,
2876                 .flags          = ADDR_TYPE_RT
2877         },
2878         { }
2879 };
2880
2881 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2882         .master         = &omap3xxx_l4_per_hwmod,
2883         .slave          = &omap3xxx_gpio2_hwmod,
2884         .addr           = omap3xxx_gpio2_addrs,
2885         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2886 };
2887
2888 /* l4_per -> gpio3 */
2889 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2890         {
2891                 .pa_start       = 0x49052000,
2892                 .pa_end         = 0x490521ff,
2893                 .flags          = ADDR_TYPE_RT
2894         },
2895         { }
2896 };
2897
2898 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2899         .master         = &omap3xxx_l4_per_hwmod,
2900         .slave          = &omap3xxx_gpio3_hwmod,
2901         .addr           = omap3xxx_gpio3_addrs,
2902         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2903 };
2904
2905 /*
2906  * 'mmu' class
2907  * The memory management unit performs virtual to physical address translation
2908  * for its requestors.
2909  */
2910
2911 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2912         .rev_offs       = 0x000,
2913         .sysc_offs      = 0x010,
2914         .syss_offs      = 0x014,
2915         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2916                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2917         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2918         .sysc_fields    = &omap_hwmod_sysc_type1,
2919 };
2920
2921 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2922         .name = "mmu",
2923         .sysc = &mmu_sysc,
2924 };
2925
2926 /* mmu isp */
2927
2928 static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
2929         .da_start       = 0x0,
2930         .da_end         = 0xfffff000,
2931         .nr_tlb_entries = 8,
2932 };
2933
2934 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2935 static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
2936         { .irq = 24 },
2937         { .irq = -1 }
2938 };
2939
2940 static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
2941         {
2942                 .pa_start       = 0x480bd400,
2943                 .pa_end         = 0x480bd47f,
2944                 .flags          = ADDR_TYPE_RT,
2945         },
2946         { }
2947 };
2948
2949 /* l4_core -> mmu isp */
2950 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2951         .master         = &omap3xxx_l4_core_hwmod,
2952         .slave          = &omap3xxx_mmu_isp_hwmod,
2953         .addr           = omap3xxx_mmu_isp_addrs,
2954         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2955 };
2956
2957 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2958         .name           = "mmu_isp",
2959         .class          = &omap3xxx_mmu_hwmod_class,
2960         .mpu_irqs       = omap3xxx_mmu_isp_irqs,
2961         .main_clk       = "cam_ick",
2962         .dev_attr       = &mmu_isp_dev_attr,
2963         .flags          = HWMOD_NO_IDLEST,
2964 };
2965
2966 #ifdef CONFIG_OMAP_IOMMU_IVA2
2967
2968 /* mmu iva */
2969
2970 static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
2971         .da_start       = 0x11000000,
2972         .da_end         = 0xfffff000,
2973         .nr_tlb_entries = 32,
2974 };
2975
2976 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2977 static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
2978         { .irq = 28 },
2979         { .irq = -1 }
2980 };
2981
2982 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2983         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2984 };
2985
2986 static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
2987         {
2988                 .pa_start       = 0x5d000000,
2989                 .pa_end         = 0x5d00007f,
2990                 .flags          = ADDR_TYPE_RT,
2991         },
2992         { }
2993 };
2994
2995 /* l3_main -> iva mmu */
2996 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2997         .master         = &omap3xxx_l3_main_hwmod,
2998         .slave          = &omap3xxx_mmu_iva_hwmod,
2999         .addr           = omap3xxx_mmu_iva_addrs,
3000         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3001 };
3002
3003 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
3004         .name           = "mmu_iva",
3005         .class          = &omap3xxx_mmu_hwmod_class,
3006         .mpu_irqs       = omap3xxx_mmu_iva_irqs,
3007         .rst_lines      = omap3xxx_mmu_iva_resets,
3008         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
3009         .main_clk       = "iva2_ck",
3010         .prcm = {
3011                 .omap2 = {
3012                         .module_offs = OMAP3430_IVA2_MOD,
3013                 },
3014         },
3015         .dev_attr       = &mmu_iva_dev_attr,
3016         .flags          = HWMOD_NO_IDLEST,
3017 };
3018
3019 #endif
3020
3021 /* l4_per -> gpio4 */
3022 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
3023         {
3024                 .pa_start       = 0x49054000,
3025                 .pa_end         = 0x490541ff,
3026                 .flags          = ADDR_TYPE_RT
3027         },
3028         { }
3029 };
3030
3031 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
3032         .master         = &omap3xxx_l4_per_hwmod,
3033         .slave          = &omap3xxx_gpio4_hwmod,
3034         .addr           = omap3xxx_gpio4_addrs,
3035         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3036 };
3037
3038 /* l4_per -> gpio5 */
3039 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
3040         {
3041                 .pa_start       = 0x49056000,
3042                 .pa_end         = 0x490561ff,
3043                 .flags          = ADDR_TYPE_RT
3044         },
3045         { }
3046 };
3047
3048 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
3049         .master         = &omap3xxx_l4_per_hwmod,
3050         .slave          = &omap3xxx_gpio5_hwmod,
3051         .addr           = omap3xxx_gpio5_addrs,
3052         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3053 };
3054
3055 /* l4_per -> gpio6 */
3056 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
3057         {
3058                 .pa_start       = 0x49058000,
3059                 .pa_end         = 0x490581ff,
3060                 .flags          = ADDR_TYPE_RT
3061         },
3062         { }
3063 };
3064
3065 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
3066         .master         = &omap3xxx_l4_per_hwmod,
3067         .slave          = &omap3xxx_gpio6_hwmod,
3068         .addr           = omap3xxx_gpio6_addrs,
3069         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3070 };
3071
3072 /* dma_system -> L3 */
3073 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
3074         .master         = &omap3xxx_dma_system_hwmod,
3075         .slave          = &omap3xxx_l3_main_hwmod,
3076         .clk            = "core_l3_ick",
3077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3078 };
3079
3080 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
3081         {
3082                 .pa_start       = 0x48056000,
3083                 .pa_end         = 0x48056fff,
3084                 .flags          = ADDR_TYPE_RT
3085         },
3086         { }
3087 };
3088
3089 /* l4_cfg -> dma_system */
3090 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
3091         .master         = &omap3xxx_l4_core_hwmod,
3092         .slave          = &omap3xxx_dma_system_hwmod,
3093         .clk            = "core_l4_ick",
3094         .addr           = omap3xxx_dma_system_addrs,
3095         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3096 };
3097
3098 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
3099         {
3100                 .name           = "mpu",
3101                 .pa_start       = 0x48074000,
3102                 .pa_end         = 0x480740ff,
3103                 .flags          = ADDR_TYPE_RT
3104         },
3105         { }
3106 };
3107
3108 /* l4_core -> mcbsp1 */
3109 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
3110         .master         = &omap3xxx_l4_core_hwmod,
3111         .slave          = &omap3xxx_mcbsp1_hwmod,
3112         .clk            = "mcbsp1_ick",
3113         .addr           = omap3xxx_mcbsp1_addrs,
3114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3115 };
3116
3117 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
3118         {
3119                 .name           = "mpu",
3120                 .pa_start       = 0x49022000,
3121                 .pa_end         = 0x490220ff,
3122                 .flags          = ADDR_TYPE_RT
3123         },
3124         { }
3125 };
3126
3127 /* l4_per -> mcbsp2 */
3128 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
3129         .master         = &omap3xxx_l4_per_hwmod,
3130         .slave          = &omap3xxx_mcbsp2_hwmod,
3131         .clk            = "mcbsp2_ick",
3132         .addr           = omap3xxx_mcbsp2_addrs,
3133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3134 };
3135
3136 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
3137         {
3138                 .name           = "mpu",
3139                 .pa_start       = 0x49024000,
3140                 .pa_end         = 0x490240ff,
3141                 .flags          = ADDR_TYPE_RT
3142         },
3143         { }
3144 };
3145
3146 /* l4_per -> mcbsp3 */
3147 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
3148         .master         = &omap3xxx_l4_per_hwmod,
3149         .slave          = &omap3xxx_mcbsp3_hwmod,
3150         .clk            = "mcbsp3_ick",
3151         .addr           = omap3xxx_mcbsp3_addrs,
3152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3153 };
3154
3155 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
3156         {
3157                 .name           = "mpu",
3158                 .pa_start       = 0x49026000,
3159                 .pa_end         = 0x490260ff,
3160                 .flags          = ADDR_TYPE_RT
3161         },
3162         { }
3163 };
3164
3165 /* l4_per -> mcbsp4 */
3166 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
3167         .master         = &omap3xxx_l4_per_hwmod,
3168         .slave          = &omap3xxx_mcbsp4_hwmod,
3169         .clk            = "mcbsp4_ick",
3170         .addr           = omap3xxx_mcbsp4_addrs,
3171         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3172 };
3173
3174 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
3175         {
3176                 .name           = "mpu",
3177                 .pa_start       = 0x48096000,
3178                 .pa_end         = 0x480960ff,
3179                 .flags          = ADDR_TYPE_RT
3180         },
3181         { }
3182 };
3183
3184 /* l4_core -> mcbsp5 */
3185 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
3186         .master         = &omap3xxx_l4_core_hwmod,
3187         .slave          = &omap3xxx_mcbsp5_hwmod,
3188         .clk            = "mcbsp5_ick",
3189         .addr           = omap3xxx_mcbsp5_addrs,
3190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3191 };
3192
3193 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
3194         {
3195                 .name           = "sidetone",
3196                 .pa_start       = 0x49028000,
3197                 .pa_end         = 0x490280ff,
3198                 .flags          = ADDR_TYPE_RT
3199         },
3200         { }
3201 };
3202
3203 /* l4_per -> mcbsp2_sidetone */
3204 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
3205         .master         = &omap3xxx_l4_per_hwmod,
3206         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
3207         .clk            = "mcbsp2_ick",
3208         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
3209         .user           = OCP_USER_MPU,
3210 };
3211
3212 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
3213         {
3214                 .name           = "sidetone",
3215                 .pa_start       = 0x4902A000,
3216                 .pa_end         = 0x4902A0ff,
3217                 .flags          = ADDR_TYPE_RT
3218         },
3219         { }
3220 };
3221
3222 /* l4_per -> mcbsp3_sidetone */
3223 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3224         .master         = &omap3xxx_l4_per_hwmod,
3225         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3226         .clk            = "mcbsp3_ick",
3227         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3228         .user           = OCP_USER_MPU,
3229 };
3230
3231 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3232         {
3233                 .pa_start       = 0x48094000,
3234                 .pa_end         = 0x480941ff,
3235                 .flags          = ADDR_TYPE_RT,
3236         },
3237         { }
3238 };
3239
3240 /* l4_core -> mailbox */
3241 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3242         .master         = &omap3xxx_l4_core_hwmod,
3243         .slave          = &omap3xxx_mailbox_hwmod,
3244         .addr           = omap3xxx_mailbox_addrs,
3245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3246 };
3247
3248 /* l4 core -> mcspi1 interface */
3249 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3250         .master         = &omap3xxx_l4_core_hwmod,
3251         .slave          = &omap34xx_mcspi1,
3252         .clk            = "mcspi1_ick",
3253         .addr           = omap2_mcspi1_addr_space,
3254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3255 };
3256
3257 /* l4 core -> mcspi2 interface */
3258 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3259         .master         = &omap3xxx_l4_core_hwmod,
3260         .slave          = &omap34xx_mcspi2,
3261         .clk            = "mcspi2_ick",
3262         .addr           = omap2_mcspi2_addr_space,
3263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3264 };
3265
3266 /* l4 core -> mcspi3 interface */
3267 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3268         .master         = &omap3xxx_l4_core_hwmod,
3269         .slave          = &omap34xx_mcspi3,
3270         .clk            = "mcspi3_ick",
3271         .addr           = omap2430_mcspi3_addr_space,
3272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3273 };
3274
3275 /* l4 core -> mcspi4 interface */
3276 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3277         {
3278                 .pa_start       = 0x480ba000,
3279                 .pa_end         = 0x480ba0ff,
3280                 .flags          = ADDR_TYPE_RT,
3281         },
3282         { }
3283 };
3284
3285 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3286         .master         = &omap3xxx_l4_core_hwmod,
3287         .slave          = &omap34xx_mcspi4,
3288         .clk            = "mcspi4_ick",
3289         .addr           = omap34xx_mcspi4_addr_space,
3290         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3291 };
3292
3293 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3294         .master         = &omap3xxx_usb_host_hs_hwmod,
3295         .slave          = &omap3xxx_l3_main_hwmod,
3296         .clk            = "core_l3_ick",
3297         .user           = OCP_USER_MPU,
3298 };
3299
3300 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3301         {
3302                 .name           = "uhh",
3303                 .pa_start       = 0x48064000,
3304                 .pa_end         = 0x480643ff,
3305                 .flags          = ADDR_TYPE_RT
3306         },
3307         {
3308                 .name           = "ohci",
3309                 .pa_start       = 0x48064400,
3310                 .pa_end         = 0x480647ff,
3311         },
3312         {
3313                 .name           = "ehci",
3314                 .pa_start       = 0x48064800,
3315                 .pa_end         = 0x48064cff,
3316         },
3317         {}
3318 };
3319
3320 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3321         .master         = &omap3xxx_l4_core_hwmod,
3322         .slave          = &omap3xxx_usb_host_hs_hwmod,
3323         .clk            = "usbhost_ick",
3324         .addr           = omap3xxx_usb_host_hs_addrs,
3325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3326 };
3327
3328 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3329         {
3330                 .name           = "tll",
3331                 .pa_start       = 0x48062000,
3332                 .pa_end         = 0x48062fff,
3333                 .flags          = ADDR_TYPE_RT
3334         },
3335         {}
3336 };
3337
3338 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3339         .master         = &omap3xxx_l4_core_hwmod,
3340         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3341         .clk            = "usbtll_ick",
3342         .addr           = omap3xxx_usb_tll_hs_addrs,
3343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3344 };
3345
3346 /* l4_core -> hdq1w interface */
3347 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3348         .master         = &omap3xxx_l4_core_hwmod,
3349         .slave          = &omap3xxx_hdq1w_hwmod,
3350         .clk            = "hdq_ick",
3351         .addr           = omap2_hdq1w_addr_space,
3352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3353         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3354 };
3355
3356 /* l4_wkup -> 32ksync_counter */
3357 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3358         {
3359                 .pa_start       = 0x48320000,
3360                 .pa_end         = 0x4832001f,
3361                 .flags          = ADDR_TYPE_RT
3362         },
3363         { }
3364 };
3365
3366 static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
3367         {
3368                 .pa_start       = 0x6e000000,
3369                 .pa_end         = 0x6e000fff,
3370                 .flags          = ADDR_TYPE_RT
3371         },
3372         { }
3373 };
3374
3375 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3376         .master         = &omap3xxx_l4_wkup_hwmod,
3377         .slave          = &omap3xxx_counter_32k_hwmod,
3378         .clk            = "omap_32ksync_ick",
3379         .addr           = omap3xxx_counter_32k_addrs,
3380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3381 };
3382
3383 /* am35xx has Davinci MDIO & EMAC */
3384 static struct omap_hwmod_class am35xx_mdio_class = {
3385         .name = "davinci_mdio",
3386 };
3387
3388 static struct omap_hwmod am35xx_mdio_hwmod = {
3389         .name           = "davinci_mdio",
3390         .class          = &am35xx_mdio_class,
3391         .flags          = HWMOD_NO_IDLEST,
3392 };
3393
3394 /*
3395  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3396  * but this will probably require some additional hwmod core support,
3397  * so is left as a future to-do item.
3398  */
3399 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3400         .master         = &am35xx_mdio_hwmod,
3401         .slave          = &omap3xxx_l3_main_hwmod,
3402         .clk            = "emac_fck",
3403         .user           = OCP_USER_MPU,
3404 };
3405
3406 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3407         {
3408                 .pa_start       = AM35XX_IPSS_MDIO_BASE,
3409                 .pa_end         = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3410                 .flags          = ADDR_TYPE_RT,
3411         },
3412         { }
3413 };
3414
3415 /* l4_core -> davinci mdio  */
3416 /*
3417  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3418  * but this will probably require some additional hwmod core support,
3419  * so is left as a future to-do item.
3420  */
3421 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3422         .master         = &omap3xxx_l4_core_hwmod,
3423         .slave          = &am35xx_mdio_hwmod,
3424         .clk            = "emac_fck",
3425         .addr           = am35xx_mdio_addrs,
3426         .user           = OCP_USER_MPU,
3427 };
3428
3429 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3430         { .name = "rxthresh",   .irq = 67 + OMAP_INTC_START, },
3431         { .name = "rx_pulse",   .irq = 68 + OMAP_INTC_START, },
3432         { .name = "tx_pulse",   .irq = 69 + OMAP_INTC_START },
3433         { .name = "misc_pulse", .irq = 70 + OMAP_INTC_START },
3434         { .irq = -1 },
3435 };
3436
3437 static struct omap_hwmod_class am35xx_emac_class = {
3438         .name = "davinci_emac",
3439 };
3440
3441 static struct omap_hwmod am35xx_emac_hwmod = {
3442         .name           = "davinci_emac",
3443         .mpu_irqs       = am35xx_emac_mpu_irqs,
3444         .class          = &am35xx_emac_class,
3445         .flags          = HWMOD_NO_IDLEST,
3446 };
3447
3448 /* l3_core -> davinci emac interface */
3449 /*
3450  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3451  * but this will probably require some additional hwmod core support,
3452  * so is left as a future to-do item.
3453  */
3454 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3455         .master         = &am35xx_emac_hwmod,
3456         .slave          = &omap3xxx_l3_main_hwmod,
3457         .clk            = "emac_ick",
3458         .user           = OCP_USER_MPU,
3459 };
3460
3461 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3462         {
3463                 .pa_start       = AM35XX_IPSS_EMAC_BASE,
3464                 .pa_end         = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3465                 .flags          = ADDR_TYPE_RT,
3466         },
3467         { }
3468 };
3469
3470 /* l4_core -> davinci emac  */
3471 /*
3472  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3473  * but this will probably require some additional hwmod core support,
3474  * so is left as a future to-do item.
3475  */
3476 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3477         .master         = &omap3xxx_l4_core_hwmod,
3478         .slave          = &am35xx_emac_hwmod,
3479         .clk            = "emac_ick",
3480         .addr           = am35xx_emac_addrs,
3481         .user           = OCP_USER_MPU,
3482 };
3483
3484 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
3485         .master         = &omap3xxx_l3_main_hwmod,
3486         .slave          = &omap3xxx_gpmc_hwmod,
3487         .clk            = "core_l3_ick",
3488         .addr           = omap3xxx_gpmc_addrs,
3489         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3490 };
3491
3492 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3493         &omap3xxx_l3_main__l4_core,
3494         &omap3xxx_l3_main__l4_per,
3495         &omap3xxx_mpu__l3_main,
3496         &omap3xxx_l4_core__l4_wkup,
3497         &omap3xxx_l4_core__mmc3,
3498         &omap3_l4_core__uart1,
3499         &omap3_l4_core__uart2,
3500         &omap3_l4_per__uart3,
3501         &omap3_l4_core__i2c1,
3502         &omap3_l4_core__i2c2,
3503         &omap3_l4_core__i2c3,
3504         &omap3xxx_l4_wkup__l4_sec,
3505         &omap3xxx_l4_wkup__timer1,
3506         &omap3xxx_l4_per__timer2,
3507         &omap3xxx_l4_per__timer3,
3508         &omap3xxx_l4_per__timer4,
3509         &omap3xxx_l4_per__timer5,
3510         &omap3xxx_l4_per__timer6,
3511         &omap3xxx_l4_per__timer7,
3512         &omap3xxx_l4_per__timer8,
3513         &omap3xxx_l4_per__timer9,
3514         &omap3xxx_l4_core__timer10,
3515         &omap3xxx_l4_core__timer11,
3516         &omap3xxx_l4_wkup__wd_timer2,
3517         &omap3xxx_l4_wkup__gpio1,
3518         &omap3xxx_l4_per__gpio2,
3519         &omap3xxx_l4_per__gpio3,
3520         &omap3xxx_l4_per__gpio4,
3521         &omap3xxx_l4_per__gpio5,
3522         &omap3xxx_l4_per__gpio6,
3523         &omap3xxx_dma_system__l3,
3524         &omap3xxx_l4_core__dma_system,
3525         &omap3xxx_l4_core__mcbsp1,
3526         &omap3xxx_l4_per__mcbsp2,
3527         &omap3xxx_l4_per__mcbsp3,
3528         &omap3xxx_l4_per__mcbsp4,
3529         &omap3xxx_l4_core__mcbsp5,
3530         &omap3xxx_l4_per__mcbsp2_sidetone,
3531         &omap3xxx_l4_per__mcbsp3_sidetone,
3532         &omap34xx_l4_core__mcspi1,
3533         &omap34xx_l4_core__mcspi2,
3534         &omap34xx_l4_core__mcspi3,
3535         &omap34xx_l4_core__mcspi4,
3536         &omap3xxx_l4_wkup__counter_32k,
3537         &omap3xxx_l3_main__gpmc,
3538         NULL,
3539 };
3540
3541 /* GP-only hwmod links */
3542 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3543         &omap3xxx_l4_sec__timer12,
3544         NULL
3545 };
3546
3547 /* 3430ES1-only hwmod links */
3548 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3549         &omap3430es1_dss__l3,
3550         &omap3430es1_l4_core__dss,
3551         NULL
3552 };
3553
3554 /* 3430ES2+-only hwmod links */
3555 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3556         &omap3xxx_dss__l3,
3557         &omap3xxx_l4_core__dss,
3558         &omap3xxx_usbhsotg__l3,
3559         &omap3xxx_l4_core__usbhsotg,
3560         &omap3xxx_usb_host_hs__l3_main_2,
3561         &omap3xxx_l4_core__usb_host_hs,
3562         &omap3xxx_l4_core__usb_tll_hs,
3563         NULL
3564 };
3565
3566 /* <= 3430ES3-only hwmod links */
3567 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3568         &omap3xxx_l4_core__pre_es3_mmc1,
3569         &omap3xxx_l4_core__pre_es3_mmc2,
3570         NULL
3571 };
3572
3573 /* 3430ES3+-only hwmod links */
3574 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3575         &omap3xxx_l4_core__es3plus_mmc1,
3576         &omap3xxx_l4_core__es3plus_mmc2,
3577         NULL
3578 };
3579
3580 /* 34xx-only hwmod links (all ES revisions) */
3581 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3582         &omap3xxx_l3__iva,
3583         &omap34xx_l4_core__sr1,
3584         &omap34xx_l4_core__sr2,
3585         &omap3xxx_l4_core__mailbox,
3586         &omap3xxx_l4_core__hdq1w,
3587         &omap3xxx_sad2d__l3,
3588         &omap3xxx_l4_core__mmu_isp,
3589 #ifdef CONFIG_OMAP_IOMMU_IVA2
3590         &omap3xxx_l3_main__mmu_iva,
3591 #endif
3592         NULL
3593 };
3594
3595 /* 36xx-only hwmod links (all ES revisions) */
3596 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3597         &omap3xxx_l3__iva,
3598         &omap36xx_l4_per__uart4,
3599         &omap3xxx_dss__l3,
3600         &omap3xxx_l4_core__dss,
3601         &omap36xx_l4_core__sr1,
3602         &omap36xx_l4_core__sr2,
3603         &omap3xxx_usbhsotg__l3,
3604         &omap3xxx_l4_core__usbhsotg,
3605         &omap3xxx_l4_core__mailbox,
3606         &omap3xxx_usb_host_hs__l3_main_2,
3607         &omap3xxx_l4_core__usb_host_hs,
3608         &omap3xxx_l4_core__usb_tll_hs,
3609         &omap3xxx_l4_core__es3plus_mmc1,
3610         &omap3xxx_l4_core__es3plus_mmc2,
3611         &omap3xxx_l4_core__hdq1w,
3612         &omap3xxx_sad2d__l3,
3613         &omap3xxx_l4_core__mmu_isp,
3614 #ifdef CONFIG_OMAP_IOMMU_IVA2
3615         &omap3xxx_l3_main__mmu_iva,
3616 #endif
3617         NULL
3618 };
3619
3620 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3621         &omap3xxx_dss__l3,
3622         &omap3xxx_l4_core__dss,
3623         &am35xx_usbhsotg__l3,
3624         &am35xx_l4_core__usbhsotg,
3625         &am35xx_l4_core__uart4,
3626         &omap3xxx_usb_host_hs__l3_main_2,
3627         &omap3xxx_l4_core__usb_host_hs,
3628         &omap3xxx_l4_core__usb_tll_hs,
3629         &omap3xxx_l4_core__es3plus_mmc1,
3630         &omap3xxx_l4_core__es3plus_mmc2,
3631         &am35xx_mdio__l3,
3632         &am35xx_l4_core__mdio,
3633         &am35xx_emac__l3,
3634         &am35xx_l4_core__emac,
3635         NULL
3636 };
3637
3638 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3639         &omap3xxx_l4_core__dss_dispc,
3640         &omap3xxx_l4_core__dss_dsi1,
3641         &omap3xxx_l4_core__dss_rfbi,
3642         &omap3xxx_l4_core__dss_venc,
3643         NULL
3644 };
3645
3646 int __init omap3xxx_hwmod_init(void)
3647 {
3648         int r;
3649         struct omap_hwmod_ocp_if **h = NULL;
3650         unsigned int rev;
3651
3652         omap_hwmod_init();
3653
3654         /* Register hwmod links common to all OMAP3 */
3655         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3656         if (r < 0)
3657                 return r;
3658
3659         /* Register GP-only hwmod links. */
3660         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3661                 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3662                 if (r < 0)
3663                         return r;
3664         }
3665
3666         rev = omap_rev();
3667
3668         /*
3669          * Register hwmod links common to individual OMAP3 families, all
3670          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3671          * All possible revisions should be included in this conditional.
3672          */
3673         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3674             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3675             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3676                 h = omap34xx_hwmod_ocp_ifs;
3677         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3678                 h = am35xx_hwmod_ocp_ifs;
3679         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3680                    rev == OMAP3630_REV_ES1_2) {
3681                 h = omap36xx_hwmod_ocp_ifs;
3682         } else {
3683                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3684                 return -EINVAL;
3685         };
3686
3687         r = omap_hwmod_register_links(h);
3688         if (r < 0)
3689                 return r;
3690
3691         /*
3692          * Register hwmod links specific to certain ES levels of a
3693          * particular family of silicon (e.g., 34xx ES1.0)
3694          */
3695         h = NULL;
3696         if (rev == OMAP3430_REV_ES1_0) {
3697                 h = omap3430es1_hwmod_ocp_ifs;
3698         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3699                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3700                    rev == OMAP3430_REV_ES3_1_2) {
3701                 h = omap3430es2plus_hwmod_ocp_ifs;
3702         };
3703
3704         if (h) {
3705                 r = omap_hwmod_register_links(h);
3706                 if (r < 0)
3707                         return r;
3708         }
3709
3710         h = NULL;
3711         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3712             rev == OMAP3430_REV_ES2_1) {
3713                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3714         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3715                    rev == OMAP3430_REV_ES3_1_2) {
3716                 h = omap3430_es3plus_hwmod_ocp_ifs;
3717         };
3718
3719         if (h)
3720                 r = omap_hwmod_register_links(h);
3721         if (r < 0)
3722                 return r;
3723
3724         /*
3725          * DSS code presumes that dss_core hwmod is handled first,
3726          * _before_ any other DSS related hwmods so register common
3727          * DSS hwmod links last to ensure that dss_core is already
3728          * registered.  Otherwise some change things may happen, for
3729          * ex. if dispc is handled before dss_core and DSS is enabled
3730          * in bootloader DISPC will be reset with outputs enabled
3731          * which sometimes leads to unrecoverable L3 error.  XXX The
3732          * long-term fix to this is to ensure hwmods are set up in
3733          * dependency order in the hwmod core code.
3734          */
3735         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3736
3737         return r;
3738 }