2 * Secondary CPU startup routine source file.
4 * Copyright (C) 2009-2014 Texas Instruments, Inc.
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * Interface functions needed for the SMP. This file is based on arm
10 * realview smp platform.
11 * Copyright (c) 2003 ARM Limited.
13 * This program is free software,you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/linkage.h>
19 #include <linux/init.h>
23 /* Physical address needed since MMU not enabled yet on secondary core */
24 #define AUX_CORE_BOOT0_PA 0x48281800
27 * OMAP5 specific entry point for secondary CPU to jump from ROM
28 * code. This routine also provides a holding flag into which
29 * secondary core is held until we're ready for it to initialise.
30 * The primary core will update this flag using a hardware
31 * register AuxCoreBoot0.
33 ENTRY(omap5_secondary_startup)
35 THUMB( adr r9, BSYM(wait) ) @ CPU may be entered in ARM mode.
36 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
37 THUMB( .thumb ) @ switch to Thumb now.
38 wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
41 mrc p15, 0, r4, c0, c0, 5
46 END(omap5_secondary_startup)
48 * OMAP4 specific entry point for secondary CPU to jump from ROM
49 * code. This routine also provides a holding flag into which
50 * secondary core is held until we're ready for it to initialise.
51 * The primary core will update this flag using a hardware
52 * register AuxCoreBoot0.
54 ENTRY(omap4_secondary_startup)
57 smc #0 @ read from AuxCoreBoot0
59 mrc p15, 0, r4, c0, c0, 5
65 * we've been released from the wait loop,secondary_stack
66 * should now contain the SVC stack for this core
69 ENDPROC(omap4_secondary_startup)
71 ENTRY(omap4460_secondary_startup)
72 hold_2: ldr r12,=0x103
74 smc #0 @ read from AuxCoreBoot0
76 mrc p15, 0, r4, c0, c0, 5
82 * GIC distributor control register has changed between
83 * CortexA9 r1pX and r2pX. The Control Register secure
84 * banked version is now composed of 2 bits:
85 * bit 0 == Secure Enable
86 * bit 1 == Non-Secure Enable
87 * The Non-Secure banked register has not changed
88 * Because the ROM Code is based on the r1pX GIC, the CPU1
89 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
90 * The workaround must be:
91 * 1) Before doing the CPU1 wakeup, CPU0 must disable
93 * 2) CPU1 must re-enable the GIC distributor on
96 ldr r1, =OMAP44XX_GIC_DIST_BASE
102 * we've been released from the wait loop,secondary_stack
103 * should now contain the SVC stack for this core
106 ENDPROC(omap4460_secondary_startup)