2 * Mailbox reservation modules for OMAP2/3
4 * Copyright (C) 2006-2009 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/clk.h>
14 #include <linux/err.h>
15 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <plat/mailbox.h>
19 #include <mach/irqs.h>
21 #define MAILBOX_REVISION 0x000
22 #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
23 #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
24 #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
25 #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
26 #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
28 #define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
29 #define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
30 #define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
32 #define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
33 #define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
35 #define MBOX_REG_SIZE 0x120
37 #define OMAP4_MBOX_REG_SIZE 0x130
39 #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
40 #define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
42 static void __iomem *mbox_base;
44 struct omap_mbox2_fifo {
46 unsigned long fifo_stat;
47 unsigned long msg_stat;
50 struct omap_mbox2_priv {
51 struct omap_mbox2_fifo tx_fifo;
52 struct omap_mbox2_fifo rx_fifo;
53 unsigned long irqenable;
54 unsigned long irqstatus;
57 u32 ctx[OMAP4_MBOX_NR_REGS];
58 unsigned long irqdisable;
61 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
62 omap_mbox_type_t irq);
64 static inline unsigned int mbox_read_reg(size_t ofs)
66 return __raw_readl(mbox_base + ofs);
69 static inline void mbox_write_reg(u32 val, size_t ofs)
71 __raw_writel(val, mbox_base + ofs);
74 /* Mailbox H/W preparations */
75 static int omap2_mbox_startup(struct omap_mbox *mbox)
79 pm_runtime_enable(mbox->dev->parent);
80 pm_runtime_get_sync(mbox->dev->parent);
82 l = mbox_read_reg(MAILBOX_REVISION);
83 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
85 omap2_mbox_enable_irq(mbox, IRQ_RX);
90 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
92 pm_runtime_put_sync(mbox->dev->parent);
93 pm_runtime_disable(mbox->dev->parent);
96 /* Mailbox FIFO handle functions */
97 static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
99 struct omap_mbox2_fifo *fifo =
100 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
101 return (mbox_msg_t) mbox_read_reg(fifo->msg);
104 static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
106 struct omap_mbox2_fifo *fifo =
107 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
108 mbox_write_reg(msg, fifo->msg);
111 static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
113 struct omap_mbox2_fifo *fifo =
114 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
115 return (mbox_read_reg(fifo->msg_stat) == 0);
118 static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
120 struct omap_mbox2_fifo *fifo =
121 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
122 return mbox_read_reg(fifo->fifo_stat);
125 /* Mailbox IRQ handle functions */
126 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
127 omap_mbox_type_t irq)
129 struct omap_mbox2_priv *p = mbox->priv;
130 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
132 l = mbox_read_reg(p->irqenable);
134 mbox_write_reg(l, p->irqenable);
137 static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
138 omap_mbox_type_t irq)
140 struct omap_mbox2_priv *p = mbox->priv;
141 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
142 l = mbox_read_reg(p->irqdisable);
144 mbox_write_reg(l, p->irqdisable);
147 static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
148 omap_mbox_type_t irq)
150 struct omap_mbox2_priv *p = mbox->priv;
151 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
153 mbox_write_reg(bit, p->irqstatus);
155 /* Flush posted write for irq status to avoid spurious interrupts */
156 mbox_read_reg(p->irqstatus);
159 static int omap2_mbox_is_irq(struct omap_mbox *mbox,
160 omap_mbox_type_t irq)
162 struct omap_mbox2_priv *p = mbox->priv;
163 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
164 u32 enable = mbox_read_reg(p->irqenable);
165 u32 status = mbox_read_reg(p->irqstatus);
167 return (int)(enable & status & bit);
170 static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
173 struct omap_mbox2_priv *p = mbox->priv;
175 if (cpu_is_omap44xx())
176 nr_regs = OMAP4_MBOX_NR_REGS;
178 nr_regs = MBOX_NR_REGS;
179 for (i = 0; i < nr_regs; i++) {
180 p->ctx[i] = mbox_read_reg(i * sizeof(u32));
182 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
187 static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
190 struct omap_mbox2_priv *p = mbox->priv;
192 if (cpu_is_omap44xx())
193 nr_regs = OMAP4_MBOX_NR_REGS;
195 nr_regs = MBOX_NR_REGS;
196 for (i = 0; i < nr_regs; i++) {
197 mbox_write_reg(p->ctx[i], i * sizeof(u32));
199 dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
204 static struct omap_mbox_ops omap2_mbox_ops = {
205 .type = OMAP_MBOX_TYPE2,
206 .startup = omap2_mbox_startup,
207 .shutdown = omap2_mbox_shutdown,
208 .fifo_read = omap2_mbox_fifo_read,
209 .fifo_write = omap2_mbox_fifo_write,
210 .fifo_empty = omap2_mbox_fifo_empty,
211 .fifo_full = omap2_mbox_fifo_full,
212 .enable_irq = omap2_mbox_enable_irq,
213 .disable_irq = omap2_mbox_disable_irq,
214 .ack_irq = omap2_mbox_ack_irq,
215 .is_irq = omap2_mbox_is_irq,
216 .save_ctx = omap2_mbox_save_ctx,
217 .restore_ctx = omap2_mbox_restore_ctx,
221 * MAILBOX 0: ARM -> DSP,
222 * MAILBOX 1: ARM <- DSP.
223 * MAILBOX 2: ARM -> IVA,
224 * MAILBOX 3: ARM <- IVA.
227 /* FIXME: the following structs should be filled automatically by the user id */
229 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
231 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
233 .msg = MAILBOX_MESSAGE(0),
234 .fifo_stat = MAILBOX_FIFOSTATUS(0),
237 .msg = MAILBOX_MESSAGE(1),
238 .msg_stat = MAILBOX_MSGSTATUS(1),
240 .irqenable = MAILBOX_IRQENABLE(0),
241 .irqstatus = MAILBOX_IRQSTATUS(0),
242 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
243 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
244 .irqdisable = MAILBOX_IRQENABLE(0),
247 struct omap_mbox mbox_dsp_info = {
249 .ops = &omap2_mbox_ops,
250 .priv = &omap2_mbox_dsp_priv,
254 #if defined(CONFIG_ARCH_OMAP3)
255 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
258 #if defined(CONFIG_SOC_OMAP2420)
260 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
262 .msg = MAILBOX_MESSAGE(2),
263 .fifo_stat = MAILBOX_FIFOSTATUS(2),
266 .msg = MAILBOX_MESSAGE(3),
267 .msg_stat = MAILBOX_MSGSTATUS(3),
269 .irqenable = MAILBOX_IRQENABLE(3),
270 .irqstatus = MAILBOX_IRQSTATUS(3),
271 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
272 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
273 .irqdisable = MAILBOX_IRQENABLE(3),
276 static struct omap_mbox mbox_iva_info = {
278 .ops = &omap2_mbox_ops,
279 .priv = &omap2_mbox_iva_priv,
282 struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
285 #if defined(CONFIG_ARCH_OMAP4)
287 static struct omap_mbox2_priv omap2_mbox_1_priv = {
289 .msg = MAILBOX_MESSAGE(0),
290 .fifo_stat = MAILBOX_FIFOSTATUS(0),
293 .msg = MAILBOX_MESSAGE(1),
294 .msg_stat = MAILBOX_MSGSTATUS(1),
296 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
297 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
298 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
299 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
300 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
303 struct omap_mbox mbox_1_info = {
305 .ops = &omap2_mbox_ops,
306 .priv = &omap2_mbox_1_priv,
309 static struct omap_mbox2_priv omap2_mbox_2_priv = {
311 .msg = MAILBOX_MESSAGE(3),
312 .fifo_stat = MAILBOX_FIFOSTATUS(3),
315 .msg = MAILBOX_MESSAGE(2),
316 .msg_stat = MAILBOX_MSGSTATUS(2),
318 .irqenable = OMAP4_MAILBOX_IRQENABLE(0),
319 .irqstatus = OMAP4_MAILBOX_IRQSTATUS(0),
320 .notfull_bit = MAILBOX_IRQ_NOTFULL(3),
321 .newmsg_bit = MAILBOX_IRQ_NEWMSG(2),
322 .irqdisable = OMAP4_MAILBOX_IRQENABLE_CLR(0),
325 struct omap_mbox mbox_2_info = {
327 .ops = &omap2_mbox_ops,
328 .priv = &omap2_mbox_2_priv,
331 struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
334 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
336 struct resource *mem;
338 struct omap_mbox **list;
342 #if defined(CONFIG_ARCH_OMAP3)
343 else if (cpu_is_omap34xx()) {
346 list[0]->irq = platform_get_irq(pdev, 0);
349 #if defined(CONFIG_ARCH_OMAP2)
350 else if (cpu_is_omap2430()) {
353 list[0]->irq = platform_get_irq(pdev, 0);
354 } else if (cpu_is_omap2420()) {
357 list[0]->irq = platform_get_irq_byname(pdev, "dsp");
358 list[1]->irq = platform_get_irq_byname(pdev, "iva");
361 #if defined(CONFIG_ARCH_OMAP4)
362 else if (cpu_is_omap44xx()) {
365 list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
369 pr_err("%s: platform not supported\n", __func__);
373 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
374 mbox_base = ioremap(mem->start, resource_size(mem));
378 ret = omap_mbox_register(&pdev->dev, list);
387 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
389 omap_mbox_unregister();
394 static struct platform_driver omap2_mbox_driver = {
395 .probe = omap2_mbox_probe,
396 .remove = __devexit_p(omap2_mbox_remove),
398 .name = "omap-mailbox",
402 static int __init omap2_mbox_init(void)
404 return platform_driver_register(&omap2_mbox_driver);
407 static void __exit omap2_mbox_exit(void)
409 platform_driver_unregister(&omap2_mbox_driver);
412 module_init(omap2_mbox_init);
413 module_exit(omap2_mbox_exit);
415 MODULE_LICENSE("GPL v2");
416 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
417 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
418 MODULE_AUTHOR("Paul Mundt");
419 MODULE_ALIAS("platform:omap2-mailbox");