2 * linux/arch/arm/mach-omap2/io.c
4 * OMAP2 I/O mapping code
6 * Copyright (C) 2005 Nokia Corporation
7 * Copyright (C) 2007-2009 Texas Instruments
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
23 #include <linux/clk.h>
26 #include <asm/mach/map.h>
28 #include <linux/omap-dma.h>
30 #include "omap_hwmod.h"
34 #include "powerdomain.h"
35 #include "clockdomain.h"
38 #include "clock2xxx.h"
39 #include "clock3xxx.h"
40 #include "clock44xx.h"
52 #include "prcm_mpu44xx.h"
53 #include "prminst44xx.h"
61 * omap_clk_soc_init: points to a function that does the SoC-specific
62 * clock initializations
64 static int (*omap_clk_soc_init)(void);
67 * The machine specific code may provide the extra mapping besides the
68 * default mapping provided here.
71 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
72 static struct map_desc omap24xx_io_desc[] __initdata = {
74 .virtual = L3_24XX_VIRT,
75 .pfn = __phys_to_pfn(L3_24XX_PHYS),
76 .length = L3_24XX_SIZE,
80 .virtual = L4_24XX_VIRT,
81 .pfn = __phys_to_pfn(L4_24XX_PHYS),
82 .length = L4_24XX_SIZE,
87 #ifdef CONFIG_SOC_OMAP2420
88 static struct map_desc omap242x_io_desc[] __initdata = {
90 .virtual = DSP_MEM_2420_VIRT,
91 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
92 .length = DSP_MEM_2420_SIZE,
96 .virtual = DSP_IPI_2420_VIRT,
97 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
98 .length = DSP_IPI_2420_SIZE,
102 .virtual = DSP_MMU_2420_VIRT,
103 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
104 .length = DSP_MMU_2420_SIZE,
111 #ifdef CONFIG_SOC_OMAP2430
112 static struct map_desc omap243x_io_desc[] __initdata = {
114 .virtual = L4_WK_243X_VIRT,
115 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
116 .length = L4_WK_243X_SIZE,
120 .virtual = OMAP243X_GPMC_VIRT,
121 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
122 .length = OMAP243X_GPMC_SIZE,
126 .virtual = OMAP243X_SDRC_VIRT,
127 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
128 .length = OMAP243X_SDRC_SIZE,
132 .virtual = OMAP243X_SMS_VIRT,
133 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
134 .length = OMAP243X_SMS_SIZE,
141 #ifdef CONFIG_ARCH_OMAP3
142 static struct map_desc omap34xx_io_desc[] __initdata = {
144 .virtual = L3_34XX_VIRT,
145 .pfn = __phys_to_pfn(L3_34XX_PHYS),
146 .length = L3_34XX_SIZE,
150 .virtual = L4_34XX_VIRT,
151 .pfn = __phys_to_pfn(L4_34XX_PHYS),
152 .length = L4_34XX_SIZE,
156 .virtual = OMAP34XX_GPMC_VIRT,
157 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
158 .length = OMAP34XX_GPMC_SIZE,
162 .virtual = OMAP343X_SMS_VIRT,
163 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
164 .length = OMAP343X_SMS_SIZE,
168 .virtual = OMAP343X_SDRC_VIRT,
169 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
170 .length = OMAP343X_SDRC_SIZE,
174 .virtual = L4_PER_34XX_VIRT,
175 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
176 .length = L4_PER_34XX_SIZE,
180 .virtual = L4_EMU_34XX_VIRT,
181 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
182 .length = L4_EMU_34XX_SIZE,
188 #ifdef CONFIG_SOC_TI81XX
189 static struct map_desc omapti81xx_io_desc[] __initdata = {
191 .virtual = L4_34XX_VIRT,
192 .pfn = __phys_to_pfn(L4_34XX_PHYS),
193 .length = L4_34XX_SIZE,
199 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
200 static struct map_desc omapam33xx_io_desc[] __initdata = {
202 .virtual = L4_34XX_VIRT,
203 .pfn = __phys_to_pfn(L4_34XX_PHYS),
204 .length = L4_34XX_SIZE,
208 .virtual = L4_WK_AM33XX_VIRT,
209 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
210 .length = L4_WK_AM33XX_SIZE,
216 #ifdef CONFIG_ARCH_OMAP4
217 static struct map_desc omap44xx_io_desc[] __initdata = {
219 .virtual = L3_44XX_VIRT,
220 .pfn = __phys_to_pfn(L3_44XX_PHYS),
221 .length = L3_44XX_SIZE,
225 .virtual = L4_44XX_VIRT,
226 .pfn = __phys_to_pfn(L4_44XX_PHYS),
227 .length = L4_44XX_SIZE,
231 .virtual = L4_PER_44XX_VIRT,
232 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
233 .length = L4_PER_44XX_SIZE,
239 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
240 static struct map_desc omap54xx_io_desc[] __initdata = {
242 .virtual = L3_54XX_VIRT,
243 .pfn = __phys_to_pfn(L3_54XX_PHYS),
244 .length = L3_54XX_SIZE,
248 .virtual = L4_54XX_VIRT,
249 .pfn = __phys_to_pfn(L4_54XX_PHYS),
250 .length = L4_54XX_SIZE,
254 .virtual = L4_WK_54XX_VIRT,
255 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
256 .length = L4_WK_54XX_SIZE,
260 .virtual = L4_PER_54XX_VIRT,
261 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
262 .length = L4_PER_54XX_SIZE,
268 #ifdef CONFIG_SOC_OMAP2420
269 void __init omap242x_map_io(void)
271 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
272 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
276 #ifdef CONFIG_SOC_OMAP2430
277 void __init omap243x_map_io(void)
279 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
280 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
284 #ifdef CONFIG_ARCH_OMAP3
285 void __init omap3_map_io(void)
287 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
291 #ifdef CONFIG_SOC_TI81XX
292 void __init ti81xx_map_io(void)
294 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
298 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
299 void __init am33xx_map_io(void)
301 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
305 #ifdef CONFIG_ARCH_OMAP4
306 void __init omap4_map_io(void)
308 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
309 omap_barriers_init();
313 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
314 void __init omap5_map_io(void)
316 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
317 omap_barriers_init();
321 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
323 * Sets the CORE DPLL3 M2 divider to the same value that it's at
324 * currently. This has the effect of setting the SDRC SDRAM AC timing
325 * registers to the values currently defined by the kernel. Currently
326 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
327 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
328 * or passes along the return value of clk_set_rate().
330 static int __init _omap2_init_reprogram_sdrc(void)
332 struct clk *dpll3_m2_ck;
336 if (!cpu_is_omap34xx())
339 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
340 if (IS_ERR(dpll3_m2_ck))
343 rate = clk_get_rate(dpll3_m2_ck);
344 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
345 v = clk_set_rate(dpll3_m2_ck, rate);
347 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
349 clk_put(dpll3_m2_ck);
354 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
356 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
359 static void __init omap_hwmod_init_postsetup(void)
363 /* Set the default postsetup state for all hwmods */
365 postsetup_state = _HWMOD_STATE_IDLE;
367 postsetup_state = _HWMOD_STATE_ENABLED;
369 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
371 omap_pm_if_early_init();
374 static void __init __maybe_unused omap_common_late_init(void)
376 omap_mux_late_init();
377 omap2_common_pm_late_init();
378 omap_soc_device_init();
381 #ifdef CONFIG_SOC_OMAP2420
382 void __init omap2420_init_early(void)
384 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
385 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
386 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
387 omap2_control_base_init();
388 omap2xxx_check_revision();
391 omap2xxx_voltagedomains_init();
392 omap242x_powerdomains_init();
393 omap242x_clockdomains_init();
394 omap2420_hwmod_init();
395 omap_hwmod_init_postsetup();
396 omap_clk_soc_init = omap2420_dt_clk_init;
397 rate_table = omap2420_rate_table;
400 void __init omap2420_init_late(void)
402 omap_common_late_init();
404 omap2_clk_enable_autoidle_all();
408 #ifdef CONFIG_SOC_OMAP2430
409 void __init omap2430_init_early(void)
411 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
412 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
413 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
414 omap2_control_base_init();
415 omap2xxx_check_revision();
418 omap2xxx_voltagedomains_init();
419 omap243x_powerdomains_init();
420 omap243x_clockdomains_init();
421 omap2430_hwmod_init();
422 omap_hwmod_init_postsetup();
423 omap_clk_soc_init = omap2430_dt_clk_init;
424 rate_table = omap2430_rate_table;
427 void __init omap2430_init_late(void)
429 omap_common_late_init();
431 omap2_clk_enable_autoidle_all();
436 * Currently only board-omap3beagle.c should call this because of the
437 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
439 #ifdef CONFIG_ARCH_OMAP3
440 void __init omap3_init_early(void)
442 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
443 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
444 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
445 /* XXX: remove these once OMAP3 is DT only */
446 if (!of_have_populated_dt()) {
447 omap2_set_globals_control(
448 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), NULL);
449 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
450 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
453 omap2_control_base_init();
454 omap3xxx_check_revision();
455 omap3xxx_check_features();
458 omap3xxx_voltagedomains_init();
459 omap3xxx_powerdomains_init();
460 omap3xxx_clockdomains_init();
461 omap3xxx_hwmod_init();
462 omap_hwmod_init_postsetup();
463 if (!of_have_populated_dt()) {
464 omap3_control_legacy_iomap_init();
466 omap_clk_soc_init = am35xx_clk_legacy_init;
467 else if (cpu_is_omap3630())
468 omap_clk_soc_init = omap36xx_clk_legacy_init;
469 else if (omap_rev() == OMAP3430_REV_ES1_0)
470 omap_clk_soc_init = omap3430es1_clk_legacy_init;
472 omap_clk_soc_init = omap3430_clk_legacy_init;
476 void __init omap3430_init_early(void)
479 if (of_have_populated_dt())
480 omap_clk_soc_init = omap3430_dt_clk_init;
483 void __init omap35xx_init_early(void)
486 if (of_have_populated_dt())
487 omap_clk_soc_init = omap3430_dt_clk_init;
490 void __init omap3630_init_early(void)
493 if (of_have_populated_dt())
494 omap_clk_soc_init = omap3630_dt_clk_init;
497 void __init am35xx_init_early(void)
500 if (of_have_populated_dt())
501 omap_clk_soc_init = am35xx_dt_clk_init;
504 void __init omap3_init_late(void)
506 omap_common_late_init();
508 omap2_clk_enable_autoidle_all();
511 void __init omap3430_init_late(void)
513 omap_common_late_init();
515 omap2_clk_enable_autoidle_all();
518 void __init omap35xx_init_late(void)
520 omap_common_late_init();
522 omap2_clk_enable_autoidle_all();
525 void __init omap3630_init_late(void)
527 omap_common_late_init();
529 omap2_clk_enable_autoidle_all();
532 void __init am35xx_init_late(void)
534 omap_common_late_init();
536 omap2_clk_enable_autoidle_all();
539 void __init ti81xx_init_late(void)
541 omap_common_late_init();
542 omap2_clk_enable_autoidle_all();
546 #ifdef CONFIG_SOC_TI81XX
547 void __init ti814x_init_early(void)
549 omap2_set_globals_tap(TI814X_CLASS,
550 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
551 omap2_control_base_init();
552 omap3xxx_check_revision();
553 ti81xx_check_features();
556 omap3xxx_voltagedomains_init();
557 omap3xxx_powerdomains_init();
558 ti81xx_clockdomains_init();
560 omap_hwmod_init_postsetup();
561 if (of_have_populated_dt())
562 omap_clk_soc_init = ti81xx_dt_clk_init;
565 void __init ti816x_init_early(void)
567 omap2_set_globals_tap(TI816X_CLASS,
568 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
569 omap2_control_base_init();
570 omap3xxx_check_revision();
571 ti81xx_check_features();
574 omap3xxx_voltagedomains_init();
575 omap3xxx_powerdomains_init();
576 ti81xx_clockdomains_init();
578 omap_hwmod_init_postsetup();
579 if (of_have_populated_dt())
580 omap_clk_soc_init = ti81xx_dt_clk_init;
584 #ifdef CONFIG_SOC_AM33XX
585 void __init am33xx_init_early(void)
587 omap2_set_globals_tap(AM335X_CLASS,
588 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
589 omap2_control_base_init();
590 omap3xxx_check_revision();
591 am33xx_check_features();
594 am33xx_powerdomains_init();
595 am33xx_clockdomains_init();
597 omap_hwmod_init_postsetup();
598 omap_clk_soc_init = am33xx_dt_clk_init;
601 void __init am33xx_init_late(void)
603 omap_common_late_init();
607 #ifdef CONFIG_SOC_AM43XX
608 void __init am43xx_init_early(void)
610 omap2_set_globals_tap(AM335X_CLASS,
611 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
612 omap2_control_base_init();
613 omap3xxx_check_revision();
614 am33xx_check_features();
617 am43xx_powerdomains_init();
618 am43xx_clockdomains_init();
620 omap_hwmod_init_postsetup();
621 omap_l2_cache_init();
622 omap_clk_soc_init = am43xx_dt_clk_init;
625 void __init am43xx_init_late(void)
627 omap_common_late_init();
631 #ifdef CONFIG_ARCH_OMAP4
632 void __init omap4430_init_early(void)
634 omap2_set_globals_tap(OMAP443X_CLASS,
635 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
636 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
637 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
638 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
639 omap4xxx_check_revision();
640 omap4xxx_check_features();
643 omap4_pm_init_early();
644 omap44xx_voltagedomains_init();
645 omap44xx_powerdomains_init();
646 omap44xx_clockdomains_init();
647 omap44xx_hwmod_init();
648 omap_hwmod_init_postsetup();
649 omap_l2_cache_init();
650 omap_clk_soc_init = omap4xxx_dt_clk_init;
653 void __init omap4430_init_late(void)
655 omap_common_late_init();
657 omap2_clk_enable_autoidle_all();
661 #ifdef CONFIG_SOC_OMAP5
662 void __init omap5_init_early(void)
664 omap2_set_globals_tap(OMAP54XX_CLASS,
665 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
666 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
667 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
668 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
669 omap4_pm_init_early();
671 omap5xxx_check_revision();
673 omap54xx_voltagedomains_init();
674 omap54xx_powerdomains_init();
675 omap54xx_clockdomains_init();
676 omap54xx_hwmod_init();
677 omap_hwmod_init_postsetup();
678 omap_clk_soc_init = omap5xxx_dt_clk_init;
681 void __init omap5_init_late(void)
683 omap_common_late_init();
685 omap2_clk_enable_autoidle_all();
689 #ifdef CONFIG_SOC_DRA7XX
690 void __init dra7xx_init_early(void)
692 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
693 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
694 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
695 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
696 omap4_pm_init_early();
698 dra7xxx_check_revision();
700 dra7xx_powerdomains_init();
701 dra7xx_clockdomains_init();
703 omap_hwmod_init_postsetup();
704 omap_clk_soc_init = dra7xx_dt_clk_init;
707 void __init dra7xx_init_late(void)
709 omap_common_late_init();
711 omap2_clk_enable_autoidle_all();
716 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
717 struct omap_sdrc_params *sdrc_cs1)
721 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
722 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
723 _omap2_init_reprogram_sdrc();
727 int __init omap_clk_init(void)
731 if (!omap_clk_soc_init)
734 ti_clk_init_features();
736 if (of_have_populated_dt()) {
737 ret = omap_control_init();
741 ret = omap_prcm_init();
747 ti_dt_clk_init_retry_clks();
749 ti_dt_clockdomains_setup();
752 ret = omap_clk_soc_init();