2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
21 #include <linux/random.h>
22 #include <linux/slab.h>
25 #include <linux/sys_soc.h>
28 #include <asm/cputype.h>
37 #define OMAP4_SILICON_TYPE_STANDARD 0x01
38 #define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
40 #define OMAP_SOC_MAX_NAME_LENGTH 16
42 static unsigned int omap_revision;
43 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
44 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
47 unsigned int omap_rev(void)
51 EXPORT_SYMBOL(omap_rev);
57 if (cpu_is_omap24xx()) {
58 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
59 } else if (cpu_is_ti81xx()) {
60 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
61 } else if (soc_is_am33xx() || soc_is_am43xx()) {
62 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
63 } else if (cpu_is_omap34xx()) {
64 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
65 } else if (cpu_is_omap44xx()) {
66 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
67 } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
68 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
69 val &= OMAP5_DEVICETYPE_MASK;
73 pr_err("Cannot detect omap type!\n");
77 val &= OMAP2_DEVICETYPE_MASK;
83 EXPORT_SYMBOL(omap_type);
86 /*----------------------------------------------------------------------------*/
88 #define OMAP_TAP_IDCODE 0x0204
89 #define OMAP_TAP_DIE_ID_0 0x0218
90 #define OMAP_TAP_DIE_ID_1 0x021C
91 #define OMAP_TAP_DIE_ID_2 0x0220
92 #define OMAP_TAP_DIE_ID_3 0x0224
94 #define OMAP_TAP_DIE_ID_44XX_0 0x0200
95 #define OMAP_TAP_DIE_ID_44XX_1 0x0208
96 #define OMAP_TAP_DIE_ID_44XX_2 0x020c
97 #define OMAP_TAP_DIE_ID_44XX_3 0x0210
99 #define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
102 u16 hawkeye; /* Silicon type (Hawkeye id) */
103 u8 dev; /* Device type from production_id reg */
104 u32 type; /* Combined type id copied to omap_revision */
107 /* Register values to detect the OMAP version */
108 static struct omap_id omap_ids[] __initdata = {
109 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
110 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
111 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
112 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
113 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
114 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
117 static void __iomem *tap_base;
118 static u16 tap_prod_id;
120 void omap_get_die_id(struct omap_die_id *odi)
122 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
123 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
124 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
125 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
126 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
130 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
131 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
132 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
133 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
136 static int __init omap_feed_randpool(void)
138 struct omap_die_id odi;
140 /* Throw the die ID into the entropy pool at boot */
141 omap_get_die_id(&odi);
142 add_device_randomness(&odi, sizeof(odi));
145 omap_device_initcall(omap_feed_randpool);
147 void __init omap2xxx_check_revision(void)
153 struct omap_die_id odi;
155 idcode = read_tap_reg(OMAP_TAP_IDCODE);
156 prod_id = read_tap_reg(tap_prod_id);
157 hawkeye = (idcode >> 12) & 0xffff;
158 rev = (idcode >> 28) & 0x0f;
159 dev_type = (prod_id >> 16) & 0x0f;
160 omap_get_die_id(&odi);
162 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
163 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
164 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
165 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
166 odi.id_1, (odi.id_1 >> 28) & 0xf);
167 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
168 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
169 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
172 /* Check hawkeye ids */
173 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
174 if (hawkeye == omap_ids[i].hawkeye)
178 if (i == ARRAY_SIZE(omap_ids)) {
179 printk(KERN_ERR "Unknown OMAP CPU id\n");
183 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
184 if (dev_type == omap_ids[j].dev)
188 if (j == ARRAY_SIZE(omap_ids)) {
189 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
190 omap_ids[i].type >> 16);
194 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
195 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
197 pr_info("%s", soc_name);
198 if ((omap_rev() >> 8) & 0x0f)
199 pr_info("%s", soc_rev);
203 #define OMAP3_SHOW_FEATURE(feat) \
204 if (omap3_has_ ##feat()) \
207 static void __init omap3_cpuinfo(void)
209 const char *cpu_name;
212 * OMAP3430 and OMAP3530 are assumed to be same.
214 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
215 * on available features. Upon detection, update the CPU id
216 * and CPU class bits.
218 if (cpu_is_omap3630()) {
219 cpu_name = "OMAP3630";
220 } else if (soc_is_am35xx()) {
221 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
222 } else if (cpu_is_ti816x()) {
224 } else if (soc_is_am335x()) {
226 } else if (soc_is_am437x()) {
228 } else if (cpu_is_ti814x()) {
230 } else if (omap3_has_iva() && omap3_has_sgx()) {
231 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
232 cpu_name = "OMAP3430/3530";
233 } else if (omap3_has_iva()) {
234 cpu_name = "OMAP3525";
235 } else if (omap3_has_sgx()) {
236 cpu_name = "OMAP3515";
238 cpu_name = "OMAP3503";
241 sprintf(soc_name, "%s", cpu_name);
243 /* Print verbose information */
244 pr_info("%s %s (", soc_name, soc_rev);
246 OMAP3_SHOW_FEATURE(l2cache);
247 OMAP3_SHOW_FEATURE(iva);
248 OMAP3_SHOW_FEATURE(sgx);
249 OMAP3_SHOW_FEATURE(neon);
250 OMAP3_SHOW_FEATURE(isp);
251 OMAP3_SHOW_FEATURE(192mhz_clk);
256 #define OMAP3_CHECK_FEATURE(status,feat) \
257 if (((status & OMAP3_ ##feat## _MASK) \
258 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
259 omap_features |= OMAP3_HAS_ ##feat; \
262 void __init omap3xxx_check_features(void)
268 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
270 OMAP3_CHECK_FEATURE(status, L2CACHE);
271 OMAP3_CHECK_FEATURE(status, IVA);
272 OMAP3_CHECK_FEATURE(status, SGX);
273 OMAP3_CHECK_FEATURE(status, NEON);
274 OMAP3_CHECK_FEATURE(status, ISP);
275 if (cpu_is_omap3630())
276 omap_features |= OMAP3_HAS_192MHZ_CLK;
277 if (cpu_is_omap3430() || cpu_is_omap3630())
278 omap_features |= OMAP3_HAS_IO_WAKEUP;
279 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
280 omap_rev() == OMAP3430_REV_ES3_1_2)
281 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
283 omap_features |= OMAP3_HAS_SDRC;
287 * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
288 * reserved and therefore return 0 when read. Unfortunately,
289 * OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
290 * mean that a feature is present even though it isn't so clear
291 * the incorrectly set feature bits.
294 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
297 * TODO: Get additional info (where applicable)
298 * e.g. Size of L2 cache.
304 void __init omap4xxx_check_features(void)
309 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
311 if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
312 omap_features = OMAP4_HAS_PERF_SILICON;
315 void __init ti81xx_check_features(void)
317 omap_features = OMAP3_HAS_NEON;
321 void __init am33xx_check_features(void)
325 omap_features = OMAP3_HAS_NEON;
327 status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
328 if (status & AM33XX_SGX_MASK)
329 omap_features |= OMAP3_HAS_SGX;
334 void __init omap3xxx_check_revision(void)
342 * We cannot access revision registers on ES1.0.
343 * If the processor type is Cortex-A8 and the revision is 0x0
344 * it means its Cortex r0p0 which is 3430 ES1.0.
346 cpuid = read_cpuid_id();
347 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
348 omap_revision = OMAP3430_REV_ES1_0;
354 * Detection for 34xx ES2.0 and above can be done with just
355 * hawkeye and rev. See TRM 1.5.2 Device Identification.
356 * Note that rev does not map directly to our defined processor
357 * revision numbers as ES1.0 uses value 0.
359 idcode = read_tap_reg(OMAP_TAP_IDCODE);
360 hawkeye = (idcode >> 12) & 0xffff;
361 rev = (idcode >> 28) & 0xff;
365 /* Handle 34xx/35xx devices */
367 case 0: /* Take care of early samples */
369 omap_revision = OMAP3430_REV_ES2_0;
373 omap_revision = OMAP3430_REV_ES2_1;
377 omap_revision = OMAP3430_REV_ES3_0;
381 omap_revision = OMAP3430_REV_ES3_1;
387 /* Use the latest known revision as default */
388 omap_revision = OMAP3430_REV_ES3_1_2;
394 * Handle OMAP/AM 3505/3517 devices
396 * Set the device to be OMAP3517 here. Actual device
397 * is identified later based on the features.
401 omap_revision = AM35XX_REV_ES1_0;
407 omap_revision = AM35XX_REV_ES1_1;
412 /* Handle 36xx devices */
415 case 0: /* Take care of early samples */
416 omap_revision = OMAP3630_REV_ES1_0;
420 omap_revision = OMAP3630_REV_ES1_1;
426 omap_revision = OMAP3630_REV_ES1_2;
433 omap_revision = TI8168_REV_ES1_0;
437 omap_revision = TI8168_REV_ES1_1;
441 omap_revision = TI8168_REV_ES2_0;
447 omap_revision = TI8168_REV_ES2_1;
454 omap_revision = AM335X_REV_ES1_0;
458 omap_revision = AM335X_REV_ES2_0;
464 omap_revision = AM335X_REV_ES2_1;
472 omap_revision = AM437X_REV_ES1_0;
476 omap_revision = AM437X_REV_ES1_1;
482 omap_revision = AM437X_REV_ES1_2;
492 omap_revision = TI8148_REV_ES1_0;
496 omap_revision = TI8148_REV_ES2_0;
502 omap_revision = TI8148_REV_ES2_1;
508 /* Unknown default to latest silicon rev as default */
509 omap_revision = OMAP3630_REV_ES1_2;
511 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
513 sprintf(soc_rev, "ES%s", cpu_rev);
516 void __init omap4xxx_check_revision(void)
523 * The IC rev detection is done with hawkeye and rev.
524 * Note that rev does not map directly to defined processor
525 * revision numbers as ES1.0 uses value 0.
527 idcode = read_tap_reg(OMAP_TAP_IDCODE);
528 hawkeye = (idcode >> 12) & 0xffff;
529 rev = (idcode >> 28) & 0xf;
532 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
533 * Use ARM register to detect the correct ES version
535 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
536 idcode = read_cpuid_id();
537 rev = (idcode & 0xf) - 1;
544 omap_revision = OMAP4430_REV_ES1_0;
548 omap_revision = OMAP4430_REV_ES2_0;
554 omap_revision = OMAP4430_REV_ES2_1;
557 omap_revision = OMAP4430_REV_ES2_2;
561 omap_revision = OMAP4430_REV_ES2_3;
567 omap_revision = OMAP4460_REV_ES1_0;
571 omap_revision = OMAP4460_REV_ES1_1;
579 omap_revision = OMAP4470_REV_ES1_0;
584 /* Unknown default to latest silicon rev as default */
585 omap_revision = OMAP4430_REV_ES2_3;
588 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
589 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
590 (omap_rev() >> 8) & 0xf);
591 pr_info("%s %s\n", soc_name, soc_rev);
594 void __init omap5xxx_check_revision(void)
600 idcode = read_tap_reg(OMAP_TAP_IDCODE);
601 hawkeye = (idcode >> 12) & 0xffff;
602 rev = (idcode >> 28) & 0xff;
607 /* No support for ES1.0 Test chip */
611 omap_revision = OMAP5430_REV_ES2_0;
618 /* No support for ES1.0 Test chip */
622 omap_revision = OMAP5432_REV_ES2_0;
627 /* Unknown default to latest silicon rev as default*/
628 omap_revision = OMAP5430_REV_ES2_0;
631 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
632 sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
634 pr_info("%s %s\n", soc_name, soc_rev);
637 void __init dra7xxx_check_revision(void)
643 idcode = read_tap_reg(OMAP_TAP_IDCODE);
644 hawkeye = (idcode >> 12) & 0xffff;
645 rev = (idcode >> 28) & 0xff;
650 omap_revision = DRA752_REV_ES1_0;
654 omap_revision = DRA752_REV_ES1_1;
661 omap_revision = DRA722_REV_ES1_0;
664 /* If we have no new revisions */
665 omap_revision = DRA722_REV_ES1_0;
671 /* Unknown default to latest silicon rev as default*/
672 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
673 __func__, idcode, hawkeye, rev);
674 omap_revision = DRA752_REV_ES1_1;
677 sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
678 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
679 (omap_rev() >> 8) & 0xf);
681 pr_info("%s %s\n", soc_name, soc_rev);
685 * Set up things for map_io and processor detection later on. Gets called
686 * pretty much first thing from board init. For multi-omap, this gets
687 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
688 * detect the exact revision later on in omap2_detect_revision() once map_io
691 void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
693 omap_revision = class;
696 /* XXX What is this intended to do? */
697 if (cpu_is_omap34xx())
698 tap_prod_id = 0x0210;
700 tap_prod_id = 0x0208;
703 #ifdef CONFIG_SOC_BUS
705 static const char * const omap_types[] = {
706 [OMAP2_DEVICE_TYPE_TEST] = "TST",
707 [OMAP2_DEVICE_TYPE_EMU] = "EMU",
708 [OMAP2_DEVICE_TYPE_SEC] = "HS",
709 [OMAP2_DEVICE_TYPE_GP] = "GP",
710 [OMAP2_DEVICE_TYPE_BAD] = "BAD",
713 static const char * __init omap_get_family(void)
715 if (cpu_is_omap24xx())
716 return kasprintf(GFP_KERNEL, "OMAP2");
717 else if (cpu_is_omap34xx())
718 return kasprintf(GFP_KERNEL, "OMAP3");
719 else if (cpu_is_omap44xx())
720 return kasprintf(GFP_KERNEL, "OMAP4");
721 else if (soc_is_omap54xx())
722 return kasprintf(GFP_KERNEL, "OMAP5");
723 else if (soc_is_am33xx() || soc_is_am335x())
724 return kasprintf(GFP_KERNEL, "AM33xx");
725 else if (soc_is_am43xx())
726 return kasprintf(GFP_KERNEL, "AM43xx");
727 else if (soc_is_dra7xx())
728 return kasprintf(GFP_KERNEL, "DRA7");
730 return kasprintf(GFP_KERNEL, "Unknown");
733 static ssize_t omap_get_type(struct device *dev,
734 struct device_attribute *attr,
737 return sprintf(buf, "%s\n", omap_types[omap_type()]);
740 static struct device_attribute omap_soc_attr =
741 __ATTR(type, S_IRUGO, omap_get_type, NULL);
743 void __init omap_soc_device_init(void)
745 struct device *parent;
746 struct soc_device *soc_dev;
747 struct soc_device_attribute *soc_dev_attr;
749 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
753 soc_dev_attr->machine = soc_name;
754 soc_dev_attr->family = omap_get_family();
755 soc_dev_attr->revision = soc_rev;
757 soc_dev = soc_device_register(soc_dev_attr);
758 if (IS_ERR(soc_dev)) {
763 parent = soc_device_to_device(soc_dev);
764 device_create_file(parent, &omap_soc_attr);
766 #endif /* CONFIG_SOC_BUS */