2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/irq.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/ioport.h>
23 #include <linux/spinlock.h>
25 #include <linux/module.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
29 #include <linux/of_mtd.h>
30 #include <linux/of_device.h>
31 #include <linux/mtd/nand.h>
33 #include <linux/platform_data/mtd-nand-omap2.h>
35 #include <asm/mach-types.h>
39 #include "omap_device.h"
41 #include "gpmc-nand.h"
42 #include "gpmc-onenand.h"
44 #define DEVICE_NAME "omap-gpmc"
46 /* GPMC register offsets */
47 #define GPMC_REVISION 0x00
48 #define GPMC_SYSCONFIG 0x10
49 #define GPMC_SYSSTATUS 0x14
50 #define GPMC_IRQSTATUS 0x18
51 #define GPMC_IRQENABLE 0x1c
52 #define GPMC_TIMEOUT_CONTROL 0x40
53 #define GPMC_ERR_ADDRESS 0x44
54 #define GPMC_ERR_TYPE 0x48
55 #define GPMC_CONFIG 0x50
56 #define GPMC_STATUS 0x54
57 #define GPMC_PREFETCH_CONFIG1 0x1e0
58 #define GPMC_PREFETCH_CONFIG2 0x1e4
59 #define GPMC_PREFETCH_CONTROL 0x1ec
60 #define GPMC_PREFETCH_STATUS 0x1f0
61 #define GPMC_ECC_CONFIG 0x1f4
62 #define GPMC_ECC_CONTROL 0x1f8
63 #define GPMC_ECC_SIZE_CONFIG 0x1fc
64 #define GPMC_ECC1_RESULT 0x200
65 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
67 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
68 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
70 /* GPMC ECC control settings */
71 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
72 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
73 #define GPMC_ECC_CTRL_ECCREG1 0x001
74 #define GPMC_ECC_CTRL_ECCREG2 0x002
75 #define GPMC_ECC_CTRL_ECCREG3 0x003
76 #define GPMC_ECC_CTRL_ECCREG4 0x004
77 #define GPMC_ECC_CTRL_ECCREG5 0x005
78 #define GPMC_ECC_CTRL_ECCREG6 0x006
79 #define GPMC_ECC_CTRL_ECCREG7 0x007
80 #define GPMC_ECC_CTRL_ECCREG8 0x008
81 #define GPMC_ECC_CTRL_ECCREG9 0x009
83 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
84 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
85 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
86 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
87 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
88 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
90 #define GPMC_CS0_OFFSET 0x60
91 #define GPMC_CS_SIZE 0x30
92 #define GPMC_BCH_SIZE 0x10
94 #define GPMC_MEM_START 0x00000000
95 #define GPMC_MEM_END 0x3FFFFFFF
96 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
98 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
99 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
101 #define CS_NUM_SHIFT 24
102 #define ENABLE_PREFETCH (0x1 << 7)
103 #define DMA_MPU_MODE 2
105 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
106 #define GPMC_REVISION_MINOR(l) (l & 0xf)
108 #define GPMC_HAS_WR_ACCESS 0x1
109 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
111 /* XXX: Only NAND irq has been considered,currently these are the only ones used
113 #define GPMC_NR_IRQ 2
115 struct gpmc_client_irq {
120 /* Structure to save gpmc cs context */
121 struct gpmc_cs_config {
133 * Structure to save/restore gpmc context
134 * to support core off on OMAP3
136 struct omap3_gpmc_regs {
141 u32 prefetch_config1;
142 u32 prefetch_config2;
143 u32 prefetch_control;
144 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
147 static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
148 static struct irq_chip gpmc_irq_chip;
149 static unsigned gpmc_irq_start;
151 static struct resource gpmc_mem_root;
152 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
153 static DEFINE_SPINLOCK(gpmc_mem_lock);
154 /* Define chip-selects as reserved by default until probe completes */
155 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
156 static struct device *gpmc_dev;
158 static resource_size_t phys_base, mem_size;
159 static unsigned gpmc_capability;
160 static void __iomem *gpmc_base;
162 static struct clk *gpmc_l3_clk;
164 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
166 static void gpmc_write_reg(int idx, u32 val)
168 __raw_writel(val, gpmc_base + idx);
171 static u32 gpmc_read_reg(int idx)
173 return __raw_readl(gpmc_base + idx);
176 void gpmc_cs_write_reg(int cs, int idx, u32 val)
178 void __iomem *reg_addr;
180 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
181 __raw_writel(val, reg_addr);
184 u32 gpmc_cs_read_reg(int cs, int idx)
186 void __iomem *reg_addr;
188 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
189 return __raw_readl(reg_addr);
192 /* TODO: Add support for gpmc_fck to clock framework and use it */
193 unsigned long gpmc_get_fclk_period(void)
195 unsigned long rate = clk_get_rate(gpmc_l3_clk);
198 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
203 rate = 1000000000 / rate; /* In picoseconds */
208 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
210 unsigned long tick_ps;
212 /* Calculate in picosecs to yield more exact results */
213 tick_ps = gpmc_get_fclk_period();
215 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
218 unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
220 unsigned long tick_ps;
222 /* Calculate in picosecs to yield more exact results */
223 tick_ps = gpmc_get_fclk_period();
225 return (time_ps + tick_ps - 1) / tick_ps;
228 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
230 return ticks * gpmc_get_fclk_period() / 1000;
233 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
235 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
237 return ticks * gpmc_get_fclk_period() / 1000;
240 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
242 return ticks * gpmc_get_fclk_period();
245 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
247 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
249 return ticks * gpmc_get_fclk_period();
252 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
256 l = gpmc_cs_read_reg(cs, reg);
261 gpmc_cs_write_reg(cs, reg, l);
264 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
266 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
267 GPMC_CONFIG1_TIME_PARA_GRAN,
268 p->time_para_granularity);
269 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
270 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
271 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
272 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
273 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
274 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
275 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
276 GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
277 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
278 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
279 p->cycle2cyclesamecsen);
280 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
281 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
282 p->cycle2cyclediffcsen);
286 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
287 int time, const char *name)
289 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
294 int ticks, mask, nr_bits;
299 ticks = gpmc_ns_to_ticks(time);
300 nr_bits = end_bit - st_bit + 1;
301 if (ticks >= 1 << nr_bits) {
303 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
304 cs, name, time, ticks, 1 << nr_bits);
309 mask = (1 << nr_bits) - 1;
310 l = gpmc_cs_read_reg(cs, reg);
313 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
314 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
315 (l >> st_bit) & mask, time);
317 l &= ~(mask << st_bit);
318 l |= ticks << st_bit;
319 gpmc_cs_write_reg(cs, reg, l);
325 #define GPMC_SET_ONE(reg, st, end, field) \
326 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
327 t->field, #field) < 0) \
330 #define GPMC_SET_ONE(reg, st, end, field) \
331 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
335 int gpmc_calc_divider(unsigned int sync_clk)
340 l = sync_clk + (gpmc_get_fclk_period() - 1);
341 div = l / gpmc_get_fclk_period();
350 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
355 div = gpmc_calc_divider(t->sync_clk);
359 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
360 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
361 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
363 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
364 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
365 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
367 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
368 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
369 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
370 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
372 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
373 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
374 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
376 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
378 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
379 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
381 GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring);
382 GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation);
384 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
385 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
386 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
387 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
389 /* caller is expected to have initialized CONFIG1 to cover
390 * at least sync vs async
392 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
393 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
395 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
396 cs, (div * gpmc_get_fclk_period()) / 1000, div);
400 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
403 gpmc_cs_bool_timings(cs, &t->bool_timings);
408 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
413 mask = (1 << GPMC_SECTION_SHIFT) - size;
414 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
416 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
418 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
419 l |= GPMC_CONFIG7_CSVALID;
420 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
423 static void gpmc_cs_disable_mem(int cs)
427 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
428 l &= ~GPMC_CONFIG7_CSVALID;
429 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
432 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
437 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
438 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
439 mask = (l >> 8) & 0x0f;
440 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
443 static int gpmc_cs_mem_enabled(int cs)
447 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
448 return l & GPMC_CONFIG7_CSVALID;
451 int gpmc_cs_set_reserved(int cs, int reserved)
453 if (cs > GPMC_CS_NUM)
456 gpmc_cs_map &= ~(1 << cs);
457 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
462 int gpmc_cs_reserved(int cs)
464 if (cs > GPMC_CS_NUM)
467 return gpmc_cs_map & (1 << cs);
470 static unsigned long gpmc_mem_align(unsigned long size)
474 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
475 order = GPMC_CHUNK_SHIFT - 1;
484 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
486 struct resource *res = &gpmc_cs_mem[cs];
489 size = gpmc_mem_align(size);
490 spin_lock(&gpmc_mem_lock);
492 res->end = base + size - 1;
493 r = request_resource(&gpmc_mem_root, res);
494 spin_unlock(&gpmc_mem_lock);
499 static int gpmc_cs_delete_mem(int cs)
501 struct resource *res = &gpmc_cs_mem[cs];
504 spin_lock(&gpmc_mem_lock);
505 r = release_resource(&gpmc_cs_mem[cs]);
508 spin_unlock(&gpmc_mem_lock);
513 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
515 struct resource *res = &gpmc_cs_mem[cs];
518 if (cs > GPMC_CS_NUM)
521 size = gpmc_mem_align(size);
522 if (size > (1 << GPMC_SECTION_SHIFT))
525 spin_lock(&gpmc_mem_lock);
526 if (gpmc_cs_reserved(cs)) {
530 if (gpmc_cs_mem_enabled(cs))
531 r = adjust_resource(res, res->start & ~(size - 1), size);
533 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
538 gpmc_cs_enable_mem(cs, res->start, resource_size(res));
540 gpmc_cs_set_reserved(cs, 1);
542 spin_unlock(&gpmc_mem_lock);
545 EXPORT_SYMBOL(gpmc_cs_request);
547 void gpmc_cs_free(int cs)
549 spin_lock(&gpmc_mem_lock);
550 if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
551 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
553 spin_unlock(&gpmc_mem_lock);
556 gpmc_cs_disable_mem(cs);
557 release_resource(&gpmc_cs_mem[cs]);
558 gpmc_cs_set_reserved(cs, 0);
559 spin_unlock(&gpmc_mem_lock);
561 EXPORT_SYMBOL(gpmc_cs_free);
564 * gpmc_cs_configure - write request to configure gpmc
565 * @cs: chip select number
567 * @wval: value to write
568 * @return status of the operation
570 int gpmc_cs_configure(int cs, int cmd, int wval)
576 case GPMC_ENABLE_IRQ:
577 gpmc_write_reg(GPMC_IRQENABLE, wval);
580 case GPMC_SET_IRQ_STATUS:
581 gpmc_write_reg(GPMC_IRQSTATUS, wval);
585 regval = gpmc_read_reg(GPMC_CONFIG);
587 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
589 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
590 gpmc_write_reg(GPMC_CONFIG, regval);
593 case GPMC_CONFIG_RDY_BSY:
594 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
596 regval |= WR_RD_PIN_MONITORING;
598 regval &= ~WR_RD_PIN_MONITORING;
599 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
602 case GPMC_CONFIG_DEV_SIZE:
603 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
605 /* clear 2 target bits */
606 regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
608 /* set the proper value */
609 regval |= GPMC_CONFIG1_DEVICESIZE(wval);
611 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
614 case GPMC_CONFIG_DEV_TYPE:
615 regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
616 regval |= GPMC_CONFIG1_DEVICETYPE(wval);
617 if (wval == GPMC_DEVICETYPE_NOR)
618 regval |= GPMC_CONFIG1_MUXADDDATA;
619 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
623 printk(KERN_ERR "gpmc_configure_cs: Not supported\n");
629 EXPORT_SYMBOL(gpmc_cs_configure);
631 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
635 reg->gpmc_status = gpmc_base + GPMC_STATUS;
636 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
637 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
638 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
639 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
640 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
641 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
642 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
643 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
644 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
645 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
646 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
647 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
648 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
649 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
651 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
652 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
654 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
656 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
658 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
663 int gpmc_get_client_irq(unsigned irq_config)
667 if (hweight32(irq_config) > 1)
670 for (i = 0; i < GPMC_NR_IRQ; i++)
671 if (gpmc_client_irq[i].bitmask & irq_config)
672 return gpmc_client_irq[i].irq;
677 static int gpmc_irq_endis(unsigned irq, bool endis)
682 for (i = 0; i < GPMC_NR_IRQ; i++)
683 if (irq == gpmc_client_irq[i].irq) {
684 regval = gpmc_read_reg(GPMC_IRQENABLE);
686 regval |= gpmc_client_irq[i].bitmask;
688 regval &= ~gpmc_client_irq[i].bitmask;
689 gpmc_write_reg(GPMC_IRQENABLE, regval);
696 static void gpmc_irq_disable(struct irq_data *p)
698 gpmc_irq_endis(p->irq, false);
701 static void gpmc_irq_enable(struct irq_data *p)
703 gpmc_irq_endis(p->irq, true);
706 static void gpmc_irq_noop(struct irq_data *data) { }
708 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
710 static int gpmc_setup_irq(void)
718 gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0);
719 if (IS_ERR_VALUE(gpmc_irq_start)) {
720 pr_err("irq_alloc_descs failed\n");
721 return gpmc_irq_start;
724 gpmc_irq_chip.name = "gpmc";
725 gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret;
726 gpmc_irq_chip.irq_enable = gpmc_irq_enable;
727 gpmc_irq_chip.irq_disable = gpmc_irq_disable;
728 gpmc_irq_chip.irq_shutdown = gpmc_irq_noop;
729 gpmc_irq_chip.irq_ack = gpmc_irq_noop;
730 gpmc_irq_chip.irq_mask = gpmc_irq_noop;
731 gpmc_irq_chip.irq_unmask = gpmc_irq_noop;
733 gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE;
734 gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT;
736 for (i = 0; i < GPMC_NR_IRQ; i++) {
737 gpmc_client_irq[i].irq = gpmc_irq_start + i;
738 irq_set_chip_and_handler(gpmc_client_irq[i].irq,
739 &gpmc_irq_chip, handle_simple_irq);
740 set_irq_flags(gpmc_client_irq[i].irq,
741 IRQF_VALID | IRQF_NOAUTOEN);
744 /* Disable interrupts */
745 gpmc_write_reg(GPMC_IRQENABLE, 0);
747 /* clear interrupts */
748 regval = gpmc_read_reg(GPMC_IRQSTATUS);
749 gpmc_write_reg(GPMC_IRQSTATUS, regval);
751 return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
754 static int gpmc_free_irq(void)
759 free_irq(gpmc_irq, NULL);
761 for (i = 0; i < GPMC_NR_IRQ; i++) {
762 irq_set_handler(gpmc_client_irq[i].irq, NULL);
763 irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
764 irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
767 irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
772 static void gpmc_mem_exit(void)
776 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
777 if (!gpmc_cs_mem_enabled(cs))
779 gpmc_cs_delete_mem(cs);
784 static int gpmc_mem_init(void)
787 unsigned long boot_rom_space = 0;
789 /* never allocate the first page, to facilitate bug detection;
790 * even if we didn't boot from ROM.
792 boot_rom_space = BOOT_ROM_SPACE;
793 /* In apollon the CS0 is mapped as 0x0000 0000 */
794 if (machine_is_omap_apollon())
796 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
797 gpmc_mem_root.end = GPMC_MEM_END;
799 /* Reserve all regions that has been set up by bootloader */
800 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
803 if (!gpmc_cs_mem_enabled(cs))
805 gpmc_cs_get_memconf(cs, &base, &size);
806 rc = gpmc_cs_insert_mem(cs, base, size);
807 if (IS_ERR_VALUE(rc)) {
809 if (gpmc_cs_mem_enabled(cs))
810 gpmc_cs_delete_mem(cs);
818 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
823 div = gpmc_calc_divider(sync_clk);
824 temp = gpmc_ps_to_ticks(time_ps);
825 temp = (temp + div - 1) / div;
826 return gpmc_ticks_to_ps(temp * div);
829 /* XXX: can the cycles be avoided ? */
830 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
831 struct gpmc_device_timings *dev_t)
833 bool mux = dev_t->mux;
837 temp = dev_t->t_avdp_r;
838 /* XXX: mux check required ? */
840 /* XXX: t_avdp not to be required for sync, only added for tusb
841 * this indirectly necessitates requirement of t_avdp_r and
842 * t_avdp_w instead of having a single t_avdp
844 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
845 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
847 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
850 temp = dev_t->t_oeasu; /* XXX: remove this ? */
852 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
853 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
854 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
856 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
859 /* XXX: any scope for improvement ?, by combining oe_on
860 * and clk_activation, need to check whether
861 * access = clk_activation + round to sync clk ?
863 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
864 temp += gpmc_t->clk_activation;
866 temp = max_t(u32, temp, gpmc_t->oe_on +
867 gpmc_ticks_to_ps(dev_t->cyc_oe));
868 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
870 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
871 gpmc_t->cs_rd_off = gpmc_t->oe_off;
874 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
875 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
877 /* XXX: barter t_ce_rdyz with t_cez_r ? */
878 if (dev_t->t_ce_rdyz)
879 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
880 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
885 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
886 struct gpmc_device_timings *dev_t)
888 bool mux = dev_t->mux;
892 temp = dev_t->t_avdp_w;
894 temp = max_t(u32, temp,
895 gpmc_t->clk_activation + dev_t->t_avdh);
896 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
898 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
900 /* wr_data_mux_bus */
901 temp = max_t(u32, dev_t->t_weasu,
902 gpmc_t->clk_activation + dev_t->t_rdyo);
903 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
904 * and in that case remember to handle we_on properly
907 temp = max_t(u32, temp,
908 gpmc_t->adv_wr_off + dev_t->t_aavdh);
909 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
910 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
912 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
915 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
916 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
918 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
921 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
922 gpmc_t->wr_access = gpmc_t->access;
925 temp = gpmc_t->we_on + dev_t->t_wpl;
926 temp = max_t(u32, temp,
927 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
928 temp = max_t(u32, temp,
929 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
930 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
932 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
936 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
937 temp += gpmc_t->wr_access;
938 /* XXX: barter t_ce_rdyz with t_cez_w ? */
939 if (dev_t->t_ce_rdyz)
940 temp = max_t(u32, temp,
941 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
942 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
947 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
948 struct gpmc_device_timings *dev_t)
950 bool mux = dev_t->mux;
954 temp = dev_t->t_avdp_r;
956 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
957 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
960 temp = dev_t->t_oeasu;
962 temp = max_t(u32, temp,
963 gpmc_t->adv_rd_off + dev_t->t_aavdh);
964 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
967 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
968 gpmc_t->oe_on + dev_t->t_oe);
969 temp = max_t(u32, temp,
970 gpmc_t->cs_on + dev_t->t_ce);
971 temp = max_t(u32, temp,
972 gpmc_t->adv_on + dev_t->t_aa);
973 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
975 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
976 gpmc_t->cs_rd_off = gpmc_t->oe_off;
979 temp = max_t(u32, dev_t->t_rd_cycle,
980 gpmc_t->cs_rd_off + dev_t->t_cez_r);
981 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
982 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
987 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
988 struct gpmc_device_timings *dev_t)
990 bool mux = dev_t->mux;
994 temp = dev_t->t_avdp_w;
996 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
997 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
999 /* wr_data_mux_bus */
1000 temp = dev_t->t_weasu;
1002 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1003 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1004 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1006 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1009 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1010 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1012 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1015 temp = gpmc_t->we_on + dev_t->t_wpl;
1016 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1018 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1022 temp = max_t(u32, dev_t->t_wr_cycle,
1023 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1024 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1029 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1030 struct gpmc_device_timings *dev_t)
1034 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1035 gpmc_get_fclk_period();
1037 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1041 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1042 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1044 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1047 if (dev_t->ce_xdelay)
1048 gpmc_t->bool_timings.cs_extra_delay = true;
1049 if (dev_t->avd_xdelay)
1050 gpmc_t->bool_timings.adv_extra_delay = true;
1051 if (dev_t->oe_xdelay)
1052 gpmc_t->bool_timings.oe_extra_delay = true;
1053 if (dev_t->we_xdelay)
1054 gpmc_t->bool_timings.we_extra_delay = true;
1059 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1060 struct gpmc_device_timings *dev_t)
1065 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1068 temp = dev_t->t_avdasu;
1069 if (dev_t->t_ce_avd)
1070 temp = max_t(u32, temp,
1071 gpmc_t->cs_on + dev_t->t_ce_avd);
1072 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1074 if (dev_t->sync_write || dev_t->sync_read)
1075 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1080 /* TODO: remove this function once all peripherals are confirmed to
1081 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1082 * has to be modified to handle timings in ps instead of ns
1084 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1087 t->cs_rd_off /= 1000;
1088 t->cs_wr_off /= 1000;
1090 t->adv_rd_off /= 1000;
1091 t->adv_wr_off /= 1000;
1096 t->page_burst_access /= 1000;
1098 t->rd_cycle /= 1000;
1099 t->wr_cycle /= 1000;
1100 t->bus_turnaround /= 1000;
1101 t->cycle2cycle_delay /= 1000;
1102 t->wait_monitoring /= 1000;
1103 t->clk_activation /= 1000;
1104 t->wr_access /= 1000;
1105 t->wr_data_mux_bus /= 1000;
1108 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1109 struct gpmc_device_timings *dev_t)
1111 memset(gpmc_t, 0, sizeof(*gpmc_t));
1113 gpmc_calc_common_timings(gpmc_t, dev_t);
1115 if (dev_t->sync_read)
1116 gpmc_calc_sync_read_timings(gpmc_t, dev_t);
1118 gpmc_calc_async_read_timings(gpmc_t, dev_t);
1120 if (dev_t->sync_write)
1121 gpmc_calc_sync_write_timings(gpmc_t, dev_t);
1123 gpmc_calc_async_write_timings(gpmc_t, dev_t);
1125 /* TODO: remove, see function definition */
1126 gpmc_convert_ps_to_ns(gpmc_t);
1128 /* Now the GPMC is initialised, unreserve the chip-selects */
1135 static struct of_device_id gpmc_dt_ids[] = {
1136 { .compatible = "ti,omap2420-gpmc" },
1137 { .compatible = "ti,omap2430-gpmc" },
1138 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1139 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1140 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1143 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1145 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1146 struct gpmc_timings *gpmc_t)
1150 memset(gpmc_t, 0, sizeof(*gpmc_t));
1152 /* minimum clock period for syncronous mode */
1153 if (!of_property_read_u32(np, "gpmc,sync-clk", &val))
1154 gpmc_t->sync_clk = val;
1156 /* chip select timtings */
1157 if (!of_property_read_u32(np, "gpmc,cs-on", &val))
1158 gpmc_t->cs_on = val;
1160 if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val))
1161 gpmc_t->cs_rd_off = val;
1163 if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val))
1164 gpmc_t->cs_wr_off = val;
1166 /* ADV signal timings */
1167 if (!of_property_read_u32(np, "gpmc,adv-on", &val))
1168 gpmc_t->adv_on = val;
1170 if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val))
1171 gpmc_t->adv_rd_off = val;
1173 if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val))
1174 gpmc_t->adv_wr_off = val;
1176 /* WE signal timings */
1177 if (!of_property_read_u32(np, "gpmc,we-on", &val))
1178 gpmc_t->we_on = val;
1180 if (!of_property_read_u32(np, "gpmc,we-off", &val))
1181 gpmc_t->we_off = val;
1183 /* OE signal timings */
1184 if (!of_property_read_u32(np, "gpmc,oe-on", &val))
1185 gpmc_t->oe_on = val;
1187 if (!of_property_read_u32(np, "gpmc,oe-off", &val))
1188 gpmc_t->oe_off = val;
1190 /* access and cycle timings */
1191 if (!of_property_read_u32(np, "gpmc,page-burst-access", &val))
1192 gpmc_t->page_burst_access = val;
1194 if (!of_property_read_u32(np, "gpmc,access", &val))
1195 gpmc_t->access = val;
1197 if (!of_property_read_u32(np, "gpmc,rd-cycle", &val))
1198 gpmc_t->rd_cycle = val;
1200 if (!of_property_read_u32(np, "gpmc,wr-cycle", &val))
1201 gpmc_t->wr_cycle = val;
1203 /* only for OMAP3430 */
1204 if (!of_property_read_u32(np, "gpmc,wr-access", &val))
1205 gpmc_t->wr_access = val;
1207 if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val))
1208 gpmc_t->wr_data_mux_bus = val;
1211 #ifdef CONFIG_MTD_NAND
1213 static const char * const nand_ecc_opts[] = {
1214 [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw",
1215 [OMAP_ECC_HAMMING_CODE_HW] = "hw",
1216 [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode",
1217 [OMAP_ECC_BCH4_CODE_HW] = "bch4",
1218 [OMAP_ECC_BCH8_CODE_HW] = "bch8",
1221 static int gpmc_probe_nand_child(struct platform_device *pdev,
1222 struct device_node *child)
1226 struct gpmc_timings gpmc_t;
1227 struct omap_nand_platform_data *gpmc_nand_data;
1229 if (of_property_read_u32(child, "reg", &val) < 0) {
1230 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1235 gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1237 if (!gpmc_nand_data)
1240 gpmc_nand_data->cs = val;
1241 gpmc_nand_data->of_node = child;
1243 if (!of_property_read_string(child, "ti,nand-ecc-opt", &s))
1244 for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++)
1245 if (!strcasecmp(s, nand_ecc_opts[val])) {
1246 gpmc_nand_data->ecc_opt = val;
1250 val = of_get_nand_bus_width(child);
1252 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1254 gpmc_read_timings_dt(child, &gpmc_t);
1255 gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1260 static int gpmc_probe_nand_child(struct platform_device *pdev,
1261 struct device_node *child)
1267 #ifdef CONFIG_MTD_ONENAND
1268 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1269 struct device_node *child)
1272 struct omap_onenand_platform_data *gpmc_onenand_data;
1274 if (of_property_read_u32(child, "reg", &val) < 0) {
1275 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1280 gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1282 if (!gpmc_onenand_data)
1285 gpmc_onenand_data->cs = val;
1286 gpmc_onenand_data->of_node = child;
1287 gpmc_onenand_data->dma_channel = -1;
1289 if (!of_property_read_u32(child, "dma-channel", &val))
1290 gpmc_onenand_data->dma_channel = val;
1292 gpmc_onenand_init(gpmc_onenand_data);
1297 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1298 struct device_node *child)
1304 static int gpmc_probe_dt(struct platform_device *pdev)
1307 struct device_node *child;
1308 const struct of_device_id *of_id =
1309 of_match_device(gpmc_dt_ids, &pdev->dev);
1314 for_each_node_by_name(child, "nand") {
1315 ret = gpmc_probe_nand_child(pdev, child);
1322 for_each_node_by_name(child, "onenand") {
1323 ret = gpmc_probe_onenand_child(pdev, child);
1332 static int gpmc_probe_dt(struct platform_device *pdev)
1338 static int gpmc_probe(struct platform_device *pdev)
1342 struct resource *res;
1344 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1348 phys_base = res->start;
1349 mem_size = resource_size(res);
1351 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
1352 if (IS_ERR(gpmc_base))
1353 return PTR_ERR(gpmc_base);
1355 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1357 dev_warn(&pdev->dev, "Failed to get resource: irq\n");
1359 gpmc_irq = res->start;
1361 gpmc_l3_clk = clk_get(&pdev->dev, "fck");
1362 if (IS_ERR(gpmc_l3_clk)) {
1363 dev_err(&pdev->dev, "error: clk_get\n");
1365 return PTR_ERR(gpmc_l3_clk);
1368 clk_prepare_enable(gpmc_l3_clk);
1370 gpmc_dev = &pdev->dev;
1372 l = gpmc_read_reg(GPMC_REVISION);
1373 if (GPMC_REVISION_MAJOR(l) > 0x4)
1374 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
1375 dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
1376 GPMC_REVISION_MINOR(l));
1378 rc = gpmc_mem_init();
1379 if (IS_ERR_VALUE(rc)) {
1380 clk_disable_unprepare(gpmc_l3_clk);
1381 clk_put(gpmc_l3_clk);
1382 dev_err(gpmc_dev, "failed to reserve memory\n");
1386 if (IS_ERR_VALUE(gpmc_setup_irq()))
1387 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1389 rc = gpmc_probe_dt(pdev);
1391 clk_disable_unprepare(gpmc_l3_clk);
1392 clk_put(gpmc_l3_clk);
1393 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1400 static int gpmc_remove(struct platform_device *pdev)
1408 static struct platform_driver gpmc_driver = {
1409 .probe = gpmc_probe,
1410 .remove = gpmc_remove,
1412 .name = DEVICE_NAME,
1413 .owner = THIS_MODULE,
1414 .of_match_table = of_match_ptr(gpmc_dt_ids),
1418 static __init int gpmc_init(void)
1420 return platform_driver_register(&gpmc_driver);
1423 static __exit void gpmc_exit(void)
1425 platform_driver_unregister(&gpmc_driver);
1429 postcore_initcall(gpmc_init);
1430 module_exit(gpmc_exit);
1432 static int __init omap_gpmc_init(void)
1434 struct omap_hwmod *oh;
1435 struct platform_device *pdev;
1436 char *oh_name = "gpmc";
1439 * if the board boots up with a populated DT, do not
1440 * manually add the device from this initcall
1442 if (of_have_populated_dt())
1445 oh = omap_hwmod_lookup(oh_name);
1447 pr_err("Could not look up %s\n", oh_name);
1451 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
1452 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1454 return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
1456 postcore_initcall(omap_gpmc_init);
1458 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1463 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1468 for (i = 0; i < GPMC_NR_IRQ; i++)
1469 if (regval & gpmc_client_irq[i].bitmask)
1470 generic_handle_irq(gpmc_client_irq[i].irq);
1472 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1477 #ifdef CONFIG_ARCH_OMAP3
1478 static struct omap3_gpmc_regs gpmc_context;
1480 void omap3_gpmc_save_context(void)
1484 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
1485 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
1486 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
1487 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
1488 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
1489 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
1490 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
1491 for (i = 0; i < GPMC_CS_NUM; i++) {
1492 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
1493 if (gpmc_context.cs_context[i].is_valid) {
1494 gpmc_context.cs_context[i].config1 =
1495 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
1496 gpmc_context.cs_context[i].config2 =
1497 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
1498 gpmc_context.cs_context[i].config3 =
1499 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
1500 gpmc_context.cs_context[i].config4 =
1501 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
1502 gpmc_context.cs_context[i].config5 =
1503 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
1504 gpmc_context.cs_context[i].config6 =
1505 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
1506 gpmc_context.cs_context[i].config7 =
1507 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
1512 void omap3_gpmc_restore_context(void)
1516 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
1517 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
1518 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
1519 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
1520 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
1521 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
1522 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
1523 for (i = 0; i < GPMC_CS_NUM; i++) {
1524 if (gpmc_context.cs_context[i].is_valid) {
1525 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
1526 gpmc_context.cs_context[i].config1);
1527 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
1528 gpmc_context.cs_context[i].config2);
1529 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
1530 gpmc_context.cs_context[i].config3);
1531 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
1532 gpmc_context.cs_context[i].config4);
1533 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
1534 gpmc_context.cs_context[i].config5);
1535 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
1536 gpmc_context.cs_context[i].config6);
1537 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
1538 gpmc_context.cs_context[i].config7);
1542 #endif /* CONFIG_ARCH_OMAP3 */