arch/arm/mach-omap2/control.c

   1 /*
   2  * OMAP2/3 System Control Module register access
   3  *
   4  * Copyright (C) 2007, 2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #undef DEBUG
  14
  15 #include <linux/kernel.h>
  16 #include <linux/io.h>
  17 #include <linux/of_address.h>
  18
  19 #include "soc.h"
  20 #include "iomap.h"
  21 #include "common.h"
  22 #include "cm-regbits-34xx.h"
  23 #include "prm-regbits-34xx.h"
  24 #include "prm3xxx.h"
  25 #include "cm3xxx.h"
  26 #include "sdrc.h"
  27 #include "pm.h"
  28 #include "control.h"
  29 #include "clock.h"
  30
  31 /* Used by omap3_ctrl_save_padconf() */
  32 #define START_PADCONF_SAVE              0x2
  33 #define PADCONF_SAVE_DONE               0x1
  34
  35 static void __iomem *omap2_ctrl_base;
  36 static void __iomem *omap4_ctrl_pad_base;
  37
  38 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  39 struct omap3_scratchpad {
  40         u32 boot_config_ptr;
  41         u32 public_restore_ptr;
  42         u32 secure_ram_restore_ptr;
  43         u32 sdrc_module_semaphore;
  44         u32 prcm_block_offset;
  45         u32 sdrc_block_offset;
  46 };
  47
  48 struct omap3_scratchpad_prcm_block {
  49         u32 prm_contents[2];
  50         u32 cm_contents[11];
  51         u32 prcm_block_size;
  52 };
  53
  54 struct omap3_scratchpad_sdrc_block {
  55         u16 sysconfig;
  56         u16 cs_cfg;
  57         u16 sharing;
  58         u16 err_type;
  59         u32 dll_a_ctrl;
  60         u32 dll_b_ctrl;
  61         u32 power;
  62         u32 cs_0;
  63         u32 mcfg_0;
  64         u16 mr_0;
  65         u16 emr_1_0;
  66         u16 emr_2_0;
  67         u16 emr_3_0;
  68         u32 actim_ctrla_0;
  69         u32 actim_ctrlb_0;
  70         u32 rfr_ctrl_0;
  71         u32 cs_1;
  72         u32 mcfg_1;
  73         u16 mr_1;
  74         u16 emr_1_1;
  75         u16 emr_2_1;
  76         u16 emr_3_1;
  77         u32 actim_ctrla_1;
  78         u32 actim_ctrlb_1;
  79         u32 rfr_ctrl_1;
  80         u16 dcdl_1_ctrl;
  81         u16 dcdl_2_ctrl;
  82         u32 flags;
  83         u32 block_size;
  84 };
  85
  86 void *omap3_secure_ram_storage;
  87
  88 /*
  89  * This is used to store ARM registers in SDRAM before attempting
  90  * an MPU OFF. The save and restore happens from the SRAM sleep code.
  91  * The address is stored in scratchpad, so that it can be used
  92  * during the restore path.
  93  */
  94 u32 omap3_arm_context[128];
  95
  96 struct omap3_control_regs {
  97         u32 sysconfig;
  98         u32 devconf0;
  99         u32 mem_dftrw0;
 100         u32 mem_dftrw1;
 101         u32 msuspendmux_0;
 102         u32 msuspendmux_1;
 103         u32 msuspendmux_2;
 104         u32 msuspendmux_3;
 105         u32 msuspendmux_4;
 106         u32 msuspendmux_5;
 107         u32 sec_ctrl;
 108         u32 devconf1;
 109         u32 csirxfe;
 110         u32 iva2_bootaddr;
 111         u32 iva2_bootmod;
 112         u32 debobs_0;
 113         u32 debobs_1;
 114         u32 debobs_2;
 115         u32 debobs_3;
 116         u32 debobs_4;
 117         u32 debobs_5;
 118         u32 debobs_6;
 119         u32 debobs_7;
 120         u32 debobs_8;
 121         u32 prog_io0;
 122         u32 prog_io1;
 123         u32 dss_dpll_spreading;
 124         u32 core_dpll_spreading;
 125         u32 per_dpll_spreading;
 126         u32 usbhost_dpll_spreading;
 127         u32 pbias_lite;
 128         u32 temp_sensor;
 129         u32 sramldo4;
 130         u32 sramldo5;
 131         u32 csi;
 132         u32 padconf_sys_nirq;
 133 };
 134
 135 static struct omap3_control_regs control_context;
 136 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 137
 138 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 139 #define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
 140
 141 void __init omap2_set_globals_control(void __iomem *ctrl,
 142                                       void __iomem *ctrl_pad)
 143 {
 144         omap2_ctrl_base = ctrl;
 145         omap4_ctrl_pad_base = ctrl_pad;
 146 }
 147
 148 u8 omap_ctrl_readb(u16 offset)
 149 {
 150         return readb_relaxed(OMAP_CTRL_REGADDR(offset));
 151 }
 152
 153 u16 omap_ctrl_readw(u16 offset)
 154 {
 155         return readw_relaxed(OMAP_CTRL_REGADDR(offset));
 156 }
 157
 158 u32 omap_ctrl_readl(u16 offset)
 159 {
 160         return readl_relaxed(OMAP_CTRL_REGADDR(offset));
 161 }
 162
 163 void omap_ctrl_writeb(u8 val, u16 offset)
 164 {
 165         writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
 166 }
 167
 168 void omap_ctrl_writew(u16 val, u16 offset)
 169 {
 170         writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
 171 }
 172
 173 void omap_ctrl_writel(u32 val, u16 offset)
 174 {
 175         writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
 176 }
 177
 178 /*
 179  * On OMAP4 control pad are not addressable from control
 180  * core base. So the common omap_ctrl_read/write APIs breaks
 181  * Hence export separate APIs to manage the omap4 pad control
 182  * registers. This APIs will work only for OMAP4
 183  */
 184
 185 u32 omap4_ctrl_pad_readl(u16 offset)
 186 {
 187         return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
 188 }
 189
 190 void omap4_ctrl_pad_writel(u32 val, u16 offset)
 191 {
 192         writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
 193 }
 194
 195 #ifdef CONFIG_ARCH_OMAP3
 196
 197 /**
 198  * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
 199  * @bootmode: 8-bit value to pass to some boot code
 200  *
 201  * Set the bootmode in the scratchpad RAM.  This is used after the
 202  * system restarts.  Not sure what actually uses this - it may be the
 203  * bootloader, rather than the boot ROM - contrary to the preserved
 204  * comment below.  No return value.
 205  */
 206 void omap3_ctrl_write_boot_mode(u8 bootmode)
 207 {
 208         u32 l;
 209
 210         l = ('B' << 24) | ('M' << 16) | bootmode;
 211
 212         /*
 213          * Reserve the first word in scratchpad for communicating
 214          * with the boot ROM. A pointer to a data structure
 215          * describing the boot process can be stored there,
 216          * cf. OMAP34xx TRM, Initialization / Software Booting
 217          * Configuration.
 218          *
 219          * XXX This should use some omap_ctrl_writel()-type function
 220          */
 221         writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
 222 }
 223
 224 #endif
 225
 226 /**
 227  * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
 228  * @bootaddr: physical address of the boot loader
 229  *
 230  * Set boot address for the boot loader of a supported processor
 231  * when a power ON sequence occurs.
 232  */
 233 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
 234 {
 235         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
 236                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
 237                      cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 238                      soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 239                      0;
 240
 241         if (!offset) {
 242                 pr_err("%s: unsupported omap type\n", __func__);
 243                 return;
 244         }
 245
 246         omap_ctrl_writel(bootaddr, offset);
 247 }
 248
 249 /**
 250  * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
 251  * @bootmode: 8-bit value to pass to some boot code
 252  *
 253  * Sets boot mode for the boot loader of a supported processor
 254  * when a power ON sequence occurs.
 255  */
 256 void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
 257 {
 258         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
 259                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
 260                      0;
 261
 262         if (!offset) {
 263                 pr_err("%s: unsupported omap type\n", __func__);
 264                 return;
 265         }
 266
 267         omap_ctrl_writel(bootmode, offset);
 268 }
 269
 270 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 271 /*
 272  * Clears the scratchpad contents in case of cold boot-
 273  * called during bootup
 274  */
 275 void omap3_clear_scratchpad_contents(void)
 276 {
 277         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
 278         void __iomem *v_addr;
 279         u32 offset = 0;
 280
 281         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
 282         if (omap3xxx_prm_clear_global_cold_reset()) {
 283                 for ( ; offset <= max_offset; offset += 0x4)
 284                         writel_relaxed(0x0, (v_addr + offset));
 285         }
 286 }
 287
 288 /* Populate the scratchpad structure with restore structure */
 289 void omap3_save_scratchpad_contents(void)
 290 {
 291         void  __iomem *scratchpad_address;
 292         u32 arm_context_addr;
 293         struct omap3_scratchpad scratchpad_contents;
 294         struct omap3_scratchpad_prcm_block prcm_block_contents;
 295         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
 296
 297         /*
 298          * Populate the Scratchpad contents
 299          *
 300          * The "get_*restore_pointer" functions are used to provide a
 301          * physical restore address where the ROM code jumps while waking
 302          * up from MPU OFF/OSWR state.
 303          * The restore pointer is stored into the scratchpad.
 304          */
 305         scratchpad_contents.boot_config_ptr = 0x0;
 306         if (cpu_is_omap3630())
 307                 scratchpad_contents.public_restore_ptr =
 308                         virt_to_phys(omap3_restore_3630);
 309         else if (omap_rev() != OMAP3430_REV_ES3_0 &&
 310                                         omap_rev() != OMAP3430_REV_ES3_1 &&
 311                                         omap_rev() != OMAP3430_REV_ES3_1_2)
 312                 scratchpad_contents.public_restore_ptr =
 313                         virt_to_phys(omap3_restore);
 314         else
 315                 scratchpad_contents.public_restore_ptr =
 316                         virt_to_phys(omap3_restore_es3);
 317
 318         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 319                 scratchpad_contents.secure_ram_restore_ptr = 0x0;
 320         else
 321                 scratchpad_contents.secure_ram_restore_ptr =
 322                         (u32) __pa(omap3_secure_ram_storage);
 323         scratchpad_contents.sdrc_module_semaphore = 0x0;
 324         scratchpad_contents.prcm_block_offset = 0x2C;
 325         scratchpad_contents.sdrc_block_offset = 0x64;
 326
 327         /* Populate the PRCM block contents */
 328         omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
 329         omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
 330
 331         prcm_block_contents.prcm_block_size = 0x0;
 332
 333         /* Populate the SDRC block contents */
 334         sdrc_block_contents.sysconfig =
 335                         (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
 336         sdrc_block_contents.cs_cfg =
 337                         (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
 338         sdrc_block_contents.sharing =
 339                         (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
 340         sdrc_block_contents.err_type =
 341                         (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
 342         sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
 343         sdrc_block_contents.dll_b_ctrl = 0x0;
 344         /*
 345          * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
 346          * be programed to issue automatic self refresh on timeout
 347          * of AUTO_CNT = 1 prior to any transition to OFF mode.
 348          */
 349         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
 350                         && (omap_rev() >= OMAP3430_REV_ES3_0))
 351                 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
 352                                 ~(SDRC_POWER_AUTOCOUNT_MASK|
 353                                 SDRC_POWER_CLKCTRL_MASK)) |
 354                                 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
 355                                 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
 356         else
 357                 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
 358
 359         sdrc_block_contents.cs_0 = 0x0;
 360         sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
 361         sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
 362         sdrc_block_contents.emr_1_0 = 0x0;
 363         sdrc_block_contents.emr_2_0 = 0x0;
 364         sdrc_block_contents.emr_3_0 = 0x0;
 365         sdrc_block_contents.actim_ctrla_0 =
 366                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
 367         sdrc_block_contents.actim_ctrlb_0 =
 368                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
 369         sdrc_block_contents.rfr_ctrl_0 =
 370                         sdrc_read_reg(SDRC_RFR_CTRL_0);
 371         sdrc_block_contents.cs_1 = 0x0;
 372         sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
 373         sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
 374         sdrc_block_contents.emr_1_1 = 0x0;
 375         sdrc_block_contents.emr_2_1 = 0x0;
 376         sdrc_block_contents.emr_3_1 = 0x0;
 377         sdrc_block_contents.actim_ctrla_1 =
 378                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
 379         sdrc_block_contents.actim_ctrlb_1 =
 380                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
 381         sdrc_block_contents.rfr_ctrl_1 =
 382                         sdrc_read_reg(SDRC_RFR_CTRL_1);
 383         sdrc_block_contents.dcdl_1_ctrl = 0x0;
 384         sdrc_block_contents.dcdl_2_ctrl = 0x0;
 385         sdrc_block_contents.flags = 0x0;
 386         sdrc_block_contents.block_size = 0x0;
 387
 388         arm_context_addr = virt_to_phys(omap3_arm_context);
 389
 390         /* Copy all the contents to the scratchpad location */
 391         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 392         memcpy_toio(scratchpad_address, &scratchpad_contents,
 393                  sizeof(scratchpad_contents));
 394         /* Scratchpad contents being 32 bits, a divide by 4 done here */
 395         memcpy_toio(scratchpad_address +
 396                 scratchpad_contents.prcm_block_offset,
 397                 &prcm_block_contents, sizeof(prcm_block_contents));
 398         memcpy_toio(scratchpad_address +
 399                 scratchpad_contents.sdrc_block_offset,
 400                 &sdrc_block_contents, sizeof(sdrc_block_contents));
 401         /*
 402          * Copies the address of the location in SDRAM where ARM
 403          * registers get saved during a MPU OFF transition.
 404          */
 405         memcpy_toio(scratchpad_address +
 406                 scratchpad_contents.sdrc_block_offset +
 407                 sizeof(sdrc_block_contents), &arm_context_addr, 4);
 408 }
 409
 410 void omap3_control_save_context(void)
 411 {
 412         control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
 413         control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 414         control_context.mem_dftrw0 =
 415                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
 416         control_context.mem_dftrw1 =
 417                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
 418         control_context.msuspendmux_0 =
 419                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
 420         control_context.msuspendmux_1 =
 421                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
 422         control_context.msuspendmux_2 =
 423                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
 424         control_context.msuspendmux_3 =
 425                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
 426         control_context.msuspendmux_4 =
 427                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
 428         control_context.msuspendmux_5 =
 429                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
 430         control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
 431         control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
 432         control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
 433         control_context.iva2_bootaddr =
 434                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
 435         control_context.iva2_bootmod =
 436                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
 437         control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
 438         control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
 439         control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
 440         control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
 441         control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
 442         control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
 443         control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
 444         control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
 445         control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
 446         control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
 447         control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
 448         control_context.dss_dpll_spreading =
 449                         omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 450         control_context.core_dpll_spreading =
 451                         omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 452         control_context.per_dpll_spreading =
 453                         omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
 454         control_context.usbhost_dpll_spreading =
 455                 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 456         control_context.pbias_lite =
 457                         omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
 458         control_context.temp_sensor =
 459                         omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
 460         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
 461         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
 462         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
 463         control_context.padconf_sys_nirq =
 464                 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 465 }
 466
 467 void omap3_control_restore_context(void)
 468 {
 469         omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
 470         omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
 471         omap_ctrl_writel(control_context.mem_dftrw0,
 472                                         OMAP343X_CONTROL_MEM_DFTRW0);
 473         omap_ctrl_writel(control_context.mem_dftrw1,
 474                                         OMAP343X_CONTROL_MEM_DFTRW1);
 475         omap_ctrl_writel(control_context.msuspendmux_0,
 476                                         OMAP2_CONTROL_MSUSPENDMUX_0);
 477         omap_ctrl_writel(control_context.msuspendmux_1,
 478                                         OMAP2_CONTROL_MSUSPENDMUX_1);
 479         omap_ctrl_writel(control_context.msuspendmux_2,
 480                                         OMAP2_CONTROL_MSUSPENDMUX_2);
 481         omap_ctrl_writel(control_context.msuspendmux_3,
 482                                         OMAP2_CONTROL_MSUSPENDMUX_3);
 483         omap_ctrl_writel(control_context.msuspendmux_4,
 484                                         OMAP2_CONTROL_MSUSPENDMUX_4);
 485         omap_ctrl_writel(control_context.msuspendmux_5,
 486                                         OMAP2_CONTROL_MSUSPENDMUX_5);
 487         omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
 488         omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
 489         omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
 490         omap_ctrl_writel(control_context.iva2_bootaddr,
 491                                         OMAP343X_CONTROL_IVA2_BOOTADDR);
 492         omap_ctrl_writel(control_context.iva2_bootmod,
 493                                         OMAP343X_CONTROL_IVA2_BOOTMOD);
 494         omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
 495         omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
 496         omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
 497         omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
 498         omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
 499         omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
 500         omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
 501         omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
 502         omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
 503         omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
 504         omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
 505         omap_ctrl_writel(control_context.dss_dpll_spreading,
 506                                         OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 507         omap_ctrl_writel(control_context.core_dpll_spreading,
 508                                         OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 509         omap_ctrl_writel(control_context.per_dpll_spreading,
 510                                         OMAP343X_CONTROL_PER_DPLL_SPREADING);
 511         omap_ctrl_writel(control_context.usbhost_dpll_spreading,
 512                                 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 513         omap_ctrl_writel(control_context.pbias_lite,
 514                                         OMAP343X_CONTROL_PBIAS_LITE);
 515         omap_ctrl_writel(control_context.temp_sensor,
 516                                         OMAP343X_CONTROL_TEMP_SENSOR);
 517         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
 518         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
 519         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
 520         omap_ctrl_writel(control_context.padconf_sys_nirq,
 521                          OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 522 }
 523
 524 void omap3630_ctrl_disable_rta(void)
 525 {
 526         if (!cpu_is_omap3630())
 527                 return;
 528         omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
 529 }
 530
 531 /**
 532  * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
 533  *
 534  * Tell the SCM to start saving the padconf registers, then wait for
 535  * the process to complete.  Returns 0 unconditionally, although it
 536  * should also eventually be able to return -ETIMEDOUT, if the save
 537  * does not complete.
 538  *
 539  * XXX This function is missing a timeout.  What should it be?
 540  */
 541 int omap3_ctrl_save_padconf(void)
 542 {
 543         u32 cpo;
 544
 545         /* Save the padconf registers */
 546         cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 547         cpo |= START_PADCONF_SAVE;
 548         omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
 549
 550         /* wait for the save to complete */
 551         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 552                  & PADCONF_SAVE_DONE))
 553                 udelay(1);
 554
 555         return 0;
 556 }
 557
 558 /**
 559  * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
 560  *
 561  * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
 562  * force disable IVA2 so that it does not prevent any low-power states.
 563  */
 564 static void __init omap3_ctrl_set_iva_bootmode_idle(void)
 565 {
 566         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 567                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 568 }
 569
 570 /**
 571  * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
 572  *
 573  * Sets up the pads controlling the stacked modem in such way that the
 574  * device can enter idle.
 575  */
 576 static void __init omap3_ctrl_setup_d2d_padconf(void)
 577 {
 578         u16 mask, padconf;
 579
 580         /*
 581          * In a stand alone OMAP3430 where there is not a stacked
 582          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 583          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 584          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
 585          */
 586         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 587         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 588         padconf |= mask;
 589         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 590
 591         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 592         padconf |= mask;
 593         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 594 }
 595
 596 /**
 597  * omap3_ctrl_init - does static initializations for control module
 598  *
 599  * Initializes system control module. This sets up the sysconfig autoidle,
 600  * and sets up modem and iva2 so that they can be idled properly.
 601  */
 602 void __init omap3_ctrl_init(void)
 603 {
 604         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 605
 606         omap3_ctrl_set_iva_bootmode_idle();
 607
 608         omap3_ctrl_setup_d2d_padconf();
 609 }
 610 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 611
 612 struct control_init_data {
 613         int index;
 614         void __iomem *mem;
 615 };
 616
 617 static struct control_init_data ctrl_data = {
 618         .index = TI_CLKM_CTRL,
 619 };
 620
 621 static const struct of_device_id omap_scrm_dt_match_table[] = {
 622         { .compatible = "ti,am3-scrm", .data = &ctrl_data },
 623         { .compatible = "ti,am4-scrm", .data = &ctrl_data },
 624         { .compatible = "ti,omap2-scrm", .data = &ctrl_data },
 625         { .compatible = "ti,omap3-scrm", .data = &ctrl_data },
 626         { .compatible = "ti,dm816-scrm", .data = &ctrl_data },
 627         { }
 628 };
 629
 630 /**
 631  * omap2_control_base_init - initialize iomappings for the control driver
 632  *
 633  * Detects and initializes the iomappings for the control driver, based
 634  * on the DT data. Returns 0 in success, negative error value
 635  * otherwise.
 636  */
 637 int __init omap2_control_base_init(void)
 638 {
 639         struct device_node *np;
 640         const struct of_device_id *match;
 641         struct control_init_data *data;
 642         void __iomem *mem;
 643
 644         for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
 645                 data = (struct control_init_data *)match->data;
 646
 647                 mem = of_iomap(np, 0);
 648                 if (!mem)
 649                         return -ENOMEM;
 650
 651                 omap2_ctrl_base = mem;
 652                 data->mem = mem;
 653         }
 654
 655         return 0;
 656 }
 657
 658 /**
 659  * omap_control_init - low level init for the control driver
 660  *
 661  * Initializes the low level clock infrastructure for control driver.
 662  * Returns 0 in success, negative error value in failure.
 663  */
 664 int __init omap_control_init(void)
 665 {
 666         struct device_node *np;
 667         const struct of_device_id *match;
 668         const struct omap_prcm_init_data *data;
 669         int ret;
 670
 671         for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) {
 672                 data = match->data;
 673
 674                 ret = omap2_clk_provider_init(np, data->index, NULL, data->mem);
 675                 if (ret)
 676                         return ret;
 677         }
 678
 679         return 0;
 680 }
 681
 682 /**
 683  * omap3_control_legacy_iomap_init - legacy iomap init for clock providers
 684  *
 685  * Legacy iomap init for clock provider. Needed only by legacy boot mode,
 686  * where the base addresses are not parsed from DT, but still required
 687  * by the clock driver to be setup properly.
 688  */
 689 void __init omap3_control_legacy_iomap_init(void)
 690 {
 691         omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base);
 692 }