arch/arm/mach-omap2/clock3xxx_data.c

   1 /*
   2  * OMAP3 clock data
   3  *
   4  * Copyright (C) 2007-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2011 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * With many device clock fixes by Kevin Hilman and Jouni Högander
   9  * DPLL bypass clock support added by Roman Tereshonkov
  10  *
  11  */
  12
  13 /*
  14  * Virtual clocks are introduced as convenient tools.
  15  * They are sources for other clocks and not supposed
  16  * to be requested from drivers directly.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/clk.h>
  21 #include <linux/list.h>
  22
  23 #include <plat/hardware.h>
  24 #include <plat/clkdev_omap.h>
  25
  26 #include "iomap.h"
  27 #include "clock.h"
  28 #include "clock3xxx.h"
  29 #include "clock34xx.h"
  30 #include "clock36xx.h"
  31 #include "clock3517.h"
  32 #include "cm2xxx_3xxx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "prm2xxx_3xxx.h"
  35 #include "prm-regbits-34xx.h"
  36 #include "control.h"
  37
  38 /*
  39  * clocks
  40  */
  41
  42 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
  43
  44 /* Maximum DPLL multiplier, divider values for OMAP3 */
  45 #define OMAP3_MAX_DPLL_MULT             2047
  46 #define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
  47 #define OMAP3_MAX_DPLL_DIV              128
  48
  49 /*
  50  * DPLL1 supplies clock to the MPU.
  51  * DPLL2 supplies clock to the IVA2.
  52  * DPLL3 supplies CORE domain clocks.
  53  * DPLL4 supplies peripheral clocks.
  54  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  55  */
  56
  57 /* Forward declarations for DPLL bypass clocks */
  58 static struct clk dpll1_fck;
  59 static struct clk dpll2_fck;
  60
  61 /* PRM CLOCKS */
  62
  63 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  64 static struct clk omap_32k_fck = {
  65         .name           = "omap_32k_fck",
  66         .ops            = &clkops_null,
  67         .rate           = 32768,
  68 };
  69
  70 static struct clk secure_32k_fck = {
  71         .name           = "secure_32k_fck",
  72         .ops            = &clkops_null,
  73         .rate           = 32768,
  74 };
  75
  76 /* Virtual source clocks for osc_sys_ck */
  77 static struct clk virt_12m_ck = {
  78         .name           = "virt_12m_ck",
  79         .ops            = &clkops_null,
  80         .rate           = 12000000,
  81 };
  82
  83 static struct clk virt_13m_ck = {
  84         .name           = "virt_13m_ck",
  85         .ops            = &clkops_null,
  86         .rate           = 13000000,
  87 };
  88
  89 static struct clk virt_16_8m_ck = {
  90         .name           = "virt_16_8m_ck",
  91         .ops            = &clkops_null,
  92         .rate           = 16800000,
  93 };
  94
  95 static struct clk virt_19_2m_ck = {
  96         .name           = "virt_19_2m_ck",
  97         .ops            = &clkops_null,
  98         .rate           = 19200000,
  99 };
 100
 101 static struct clk virt_26m_ck = {
 102         .name           = "virt_26m_ck",
 103         .ops            = &clkops_null,
 104         .rate           = 26000000,
 105 };
 106
 107 static struct clk virt_38_4m_ck = {
 108         .name           = "virt_38_4m_ck",
 109         .ops            = &clkops_null,
 110         .rate           = 38400000,
 111 };
 112
 113 static const struct clksel_rate osc_sys_12m_rates[] = {
 114         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 115         { .div = 0 }
 116 };
 117
 118 static const struct clksel_rate osc_sys_13m_rates[] = {
 119         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 120         { .div = 0 }
 121 };
 122
 123 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 124         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
 125         { .div = 0 }
 126 };
 127
 128 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 129         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 130         { .div = 0 }
 131 };
 132
 133 static const struct clksel_rate osc_sys_26m_rates[] = {
 134         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 135         { .div = 0 }
 136 };
 137
 138 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 139         { .div = 1, .val = 4, .flags = RATE_IN_3XXX },
 140         { .div = 0 }
 141 };
 142
 143 static const struct clksel osc_sys_clksel[] = {
 144         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 145         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 146         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 147         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 148         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 149         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 150         { .parent = NULL },
 151 };
 152
 153 /* Oscillator clock */
 154 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 155 static struct clk osc_sys_ck = {
 156         .name           = "osc_sys_ck",
 157         .ops            = &clkops_null,
 158         .init           = &omap2_init_clksel_parent,
 159         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 160         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 161         .clksel         = osc_sys_clksel,
 162         /* REVISIT: deal with autoextclkmode? */
 163         .recalc         = &omap2_clksel_recalc,
 164 };
 165
 166 static const struct clksel_rate div2_rates[] = {
 167         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 168         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 169         { .div = 0 }
 170 };
 171
 172 static const struct clksel sys_clksel[] = {
 173         { .parent = &osc_sys_ck, .rates = div2_rates },
 174         { .parent = NULL }
 175 };
 176
 177 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 178 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 179 static struct clk sys_ck = {
 180         .name           = "sys_ck",
 181         .ops            = &clkops_null,
 182         .parent         = &osc_sys_ck,
 183         .init           = &omap2_init_clksel_parent,
 184         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 185         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 186         .clksel         = sys_clksel,
 187         .recalc         = &omap2_clksel_recalc,
 188 };
 189
 190 static struct clk sys_altclk = {
 191         .name           = "sys_altclk",
 192         .ops            = &clkops_null,
 193 };
 194
 195 /* Optional external clock input for some McBSPs */
 196 static struct clk mcbsp_clks = {
 197         .name           = "mcbsp_clks",
 198         .ops            = &clkops_null,
 199 };
 200
 201 /* PRM EXTERNAL CLOCK OUTPUT */
 202
 203 static struct clk sys_clkout1 = {
 204         .name           = "sys_clkout1",
 205         .ops            = &clkops_omap2_dflt,
 206         .parent         = &osc_sys_ck,
 207         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 208         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 209         .recalc         = &followparent_recalc,
 210 };
 211
 212 /* DPLLS */
 213
 214 /* CM CLOCKS */
 215
 216 static const struct clksel_rate div16_dpll_rates[] = {
 217         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 218         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 219         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 220         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 221         { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 222         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 223         { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 224         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 225         { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 226         { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 227         { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 228         { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 229         { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 230         { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 231         { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 232         { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 233         { .div = 0 }
 234 };
 235
 236 static const struct clksel_rate dpll4_rates[] = {
 237         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 238         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 239         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
 240         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
 241         { .div = 5, .val = 5, .flags = RATE_IN_3XXX },
 242         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
 243         { .div = 7, .val = 7, .flags = RATE_IN_3XXX },
 244         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
 245         { .div = 9, .val = 9, .flags = RATE_IN_3XXX },
 246         { .div = 10, .val = 10, .flags = RATE_IN_3XXX },
 247         { .div = 11, .val = 11, .flags = RATE_IN_3XXX },
 248         { .div = 12, .val = 12, .flags = RATE_IN_3XXX },
 249         { .div = 13, .val = 13, .flags = RATE_IN_3XXX },
 250         { .div = 14, .val = 14, .flags = RATE_IN_3XXX },
 251         { .div = 15, .val = 15, .flags = RATE_IN_3XXX },
 252         { .div = 16, .val = 16, .flags = RATE_IN_3XXX },
 253         { .div = 17, .val = 17, .flags = RATE_IN_36XX },
 254         { .div = 18, .val = 18, .flags = RATE_IN_36XX },
 255         { .div = 19, .val = 19, .flags = RATE_IN_36XX },
 256         { .div = 20, .val = 20, .flags = RATE_IN_36XX },
 257         { .div = 21, .val = 21, .flags = RATE_IN_36XX },
 258         { .div = 22, .val = 22, .flags = RATE_IN_36XX },
 259         { .div = 23, .val = 23, .flags = RATE_IN_36XX },
 260         { .div = 24, .val = 24, .flags = RATE_IN_36XX },
 261         { .div = 25, .val = 25, .flags = RATE_IN_36XX },
 262         { .div = 26, .val = 26, .flags = RATE_IN_36XX },
 263         { .div = 27, .val = 27, .flags = RATE_IN_36XX },
 264         { .div = 28, .val = 28, .flags = RATE_IN_36XX },
 265         { .div = 29, .val = 29, .flags = RATE_IN_36XX },
 266         { .div = 30, .val = 30, .flags = RATE_IN_36XX },
 267         { .div = 31, .val = 31, .flags = RATE_IN_36XX },
 268         { .div = 32, .val = 32, .flags = RATE_IN_36XX },
 269         { .div = 0 }
 270 };
 271
 272 /* DPLL1 */
 273 /* MPU clock source */
 274 /* Type: DPLL */
 275 static struct dpll_data dpll1_dd = {
 276         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 277         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 278         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 279         .clk_bypass     = &dpll1_fck,
 280         .clk_ref        = &sys_ck,
 281         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
 282         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 283         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 284         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 285         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 286         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 287         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 288         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 289         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
 290         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 291         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
 292         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 293         .min_divider    = 1,
 294         .max_divider    = OMAP3_MAX_DPLL_DIV,
 295 };
 296
 297 static struct clk dpll1_ck = {
 298         .name           = "dpll1_ck",
 299         .ops            = &clkops_omap3_noncore_dpll_ops,
 300         .parent         = &sys_ck,
 301         .dpll_data      = &dpll1_dd,
 302         .round_rate     = &omap2_dpll_round_rate,
 303         .set_rate       = &omap3_noncore_dpll_set_rate,
 304         .clkdm_name     = "dpll1_clkdm",
 305         .recalc         = &omap3_dpll_recalc,
 306 };
 307
 308 /*
 309  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 310  * DPLL isn't bypassed.
 311  */
 312 static struct clk dpll1_x2_ck = {
 313         .name           = "dpll1_x2_ck",
 314         .ops            = &clkops_null,
 315         .parent         = &dpll1_ck,
 316         .clkdm_name     = "dpll1_clkdm",
 317         .recalc         = &omap3_clkoutx2_recalc,
 318 };
 319
 320 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 321 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 322         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 323         { .parent = NULL }
 324 };
 325
 326 /*
 327  * Does not exist in the TRM - needed to separate the M2 divider from
 328  * bypass selection in mpu_ck
 329  */
 330 static struct clk dpll1_x2m2_ck = {
 331         .name           = "dpll1_x2m2_ck",
 332         .ops            = &clkops_null,
 333         .parent         = &dpll1_x2_ck,
 334         .init           = &omap2_init_clksel_parent,
 335         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 336         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 337         .clksel         = div16_dpll1_x2m2_clksel,
 338         .clkdm_name     = "dpll1_clkdm",
 339         .recalc         = &omap2_clksel_recalc,
 340 };
 341
 342 /* DPLL2 */
 343 /* IVA2 clock source */
 344 /* Type: DPLL */
 345
 346 static struct dpll_data dpll2_dd = {
 347         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 348         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 349         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 350         .clk_bypass     = &dpll2_fck,
 351         .clk_ref        = &sys_ck,
 352         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
 353         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 354         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 355         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
 356                                 (1 << DPLL_LOW_POWER_BYPASS),
 357         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 358         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 359         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 360         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
 361         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
 362         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
 363         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
 364         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 365         .min_divider    = 1,
 366         .max_divider    = OMAP3_MAX_DPLL_DIV,
 367 };
 368
 369 static struct clk dpll2_ck = {
 370         .name           = "dpll2_ck",
 371         .ops            = &clkops_omap3_noncore_dpll_ops,
 372         .parent         = &sys_ck,
 373         .dpll_data      = &dpll2_dd,
 374         .round_rate     = &omap2_dpll_round_rate,
 375         .set_rate       = &omap3_noncore_dpll_set_rate,
 376         .clkdm_name     = "dpll2_clkdm",
 377         .recalc         = &omap3_dpll_recalc,
 378 };
 379
 380 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 381         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 382         { .parent = NULL }
 383 };
 384
 385 /*
 386  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 387  * or CLKOUTX2. CLKOUT seems most plausible.
 388  */
 389 static struct clk dpll2_m2_ck = {
 390         .name           = "dpll2_m2_ck",
 391         .ops            = &clkops_null,
 392         .parent         = &dpll2_ck,
 393         .init           = &omap2_init_clksel_parent,
 394         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 395                                           OMAP3430_CM_CLKSEL2_PLL),
 396         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 397         .clksel         = div16_dpll2_m2x2_clksel,
 398         .clkdm_name     = "dpll2_clkdm",
 399         .recalc         = &omap2_clksel_recalc,
 400 };
 401
 402 /*
 403  * DPLL3
 404  * Source clock for all interfaces and for some device fclks
 405  * REVISIT: Also supports fast relock bypass - not included below
 406  */
 407 static struct dpll_data dpll3_dd = {
 408         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 409         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 410         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 411         .clk_bypass     = &sys_ck,
 412         .clk_ref        = &sys_ck,
 413         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
 414         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 415         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 416         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 417         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 418         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 419         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 420         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
 421         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 422         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
 423         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 424         .min_divider    = 1,
 425         .max_divider    = OMAP3_MAX_DPLL_DIV,
 426 };
 427
 428 static struct clk dpll3_ck = {
 429         .name           = "dpll3_ck",
 430         .ops            = &clkops_omap3_core_dpll_ops,
 431         .parent         = &sys_ck,
 432         .dpll_data      = &dpll3_dd,
 433         .round_rate     = &omap2_dpll_round_rate,
 434         .clkdm_name     = "dpll3_clkdm",
 435         .recalc         = &omap3_dpll_recalc,
 436 };
 437
 438 /*
 439  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 440  * DPLL isn't bypassed
 441  */
 442 static struct clk dpll3_x2_ck = {
 443         .name           = "dpll3_x2_ck",
 444         .ops            = &clkops_null,
 445         .parent         = &dpll3_ck,
 446         .clkdm_name     = "dpll3_clkdm",
 447         .recalc         = &omap3_clkoutx2_recalc,
 448 };
 449
 450 static const struct clksel_rate div31_dpll3_rates[] = {
 451         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 452         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
 453         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2PLUS_36XX },
 454         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2PLUS_36XX },
 455         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2PLUS_36XX },
 456         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2PLUS_36XX },
 457         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2PLUS_36XX },
 458         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2PLUS_36XX },
 459         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2PLUS_36XX },
 460         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2PLUS_36XX },
 461         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2PLUS_36XX },
 462         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2PLUS_36XX },
 463         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2PLUS_36XX },
 464         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2PLUS_36XX },
 465         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2PLUS_36XX },
 466         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2PLUS_36XX },
 467         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2PLUS_36XX },
 468         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2PLUS_36XX },
 469         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2PLUS_36XX },
 470         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2PLUS_36XX },
 471         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2PLUS_36XX },
 472         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2PLUS_36XX },
 473         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2PLUS_36XX },
 474         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2PLUS_36XX },
 475         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2PLUS_36XX },
 476         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2PLUS_36XX },
 477         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2PLUS_36XX },
 478         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2PLUS_36XX },
 479         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2PLUS_36XX },
 480         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2PLUS_36XX },
 481         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2PLUS_36XX },
 482         { .div = 0 },
 483 };
 484
 485 static const struct clksel div31_dpll3m2_clksel[] = {
 486         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 487         { .parent = NULL }
 488 };
 489
 490 /* DPLL3 output M2 - primary control point for CORE speed */
 491 static struct clk dpll3_m2_ck = {
 492         .name           = "dpll3_m2_ck",
 493         .ops            = &clkops_null,
 494         .parent         = &dpll3_ck,
 495         .init           = &omap2_init_clksel_parent,
 496         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 497         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 498         .clksel         = div31_dpll3m2_clksel,
 499         .clkdm_name     = "dpll3_clkdm",
 500         .round_rate     = &omap2_clksel_round_rate,
 501         .set_rate       = &omap3_core_dpll_m2_set_rate,
 502         .recalc         = &omap2_clksel_recalc,
 503 };
 504
 505 static struct clk core_ck = {
 506         .name           = "core_ck",
 507         .ops            = &clkops_null,
 508         .parent         = &dpll3_m2_ck,
 509         .recalc         = &followparent_recalc,
 510 };
 511
 512 static struct clk dpll3_m2x2_ck = {
 513         .name           = "dpll3_m2x2_ck",
 514         .ops            = &clkops_null,
 515         .parent         = &dpll3_m2_ck,
 516         .clkdm_name     = "dpll3_clkdm",
 517         .recalc         = &omap3_clkoutx2_recalc,
 518 };
 519
 520 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 521 static const struct clksel div16_dpll3_clksel[] = {
 522         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 523         { .parent = NULL }
 524 };
 525
 526 /* This virtual clock is the source for dpll3_m3x2_ck */
 527 static struct clk dpll3_m3_ck = {
 528         .name           = "dpll3_m3_ck",
 529         .ops            = &clkops_null,
 530         .parent         = &dpll3_ck,
 531         .init           = &omap2_init_clksel_parent,
 532         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 533         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 534         .clksel         = div16_dpll3_clksel,
 535         .clkdm_name     = "dpll3_clkdm",
 536         .recalc         = &omap2_clksel_recalc,
 537 };
 538
 539 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 540 static struct clk dpll3_m3x2_ck = {
 541         .name           = "dpll3_m3x2_ck",
 542         .ops            = &clkops_omap2_dflt_wait,
 543         .parent         = &dpll3_m3_ck,
 544         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 545         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 546         .flags          = INVERT_ENABLE,
 547         .clkdm_name     = "dpll3_clkdm",
 548         .recalc         = &omap3_clkoutx2_recalc,
 549 };
 550
 551 static struct clk emu_core_alwon_ck = {
 552         .name           = "emu_core_alwon_ck",
 553         .ops            = &clkops_null,
 554         .parent         = &dpll3_m3x2_ck,
 555         .clkdm_name     = "dpll3_clkdm",
 556         .recalc         = &followparent_recalc,
 557 };
 558
 559 /* DPLL4 */
 560 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 561 /* Type: DPLL */
 562 static struct dpll_data dpll4_dd;
 563
 564 static struct dpll_data dpll4_dd_34xx __initdata = {
 565         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 566         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 567         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 568         .clk_bypass     = &sys_ck,
 569         .clk_ref        = &sys_ck,
 570         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
 571         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 572         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 573         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 574         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 575         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 576         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 577         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 578         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 579         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 580         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 581         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 582         .min_divider    = 1,
 583         .max_divider    = OMAP3_MAX_DPLL_DIV,
 584 };
 585
 586 static struct dpll_data dpll4_dd_3630 __initdata = {
 587         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 588         .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
 589         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 590         .clk_bypass     = &sys_ck,
 591         .clk_ref        = &sys_ck,
 592         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 593         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 594         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 595         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 596         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 597         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 598         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
 599         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
 600         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 601         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
 602         .dco_mask       = OMAP3630_PERIPH_DPLL_DCO_SEL_MASK,
 603         .sddiv_mask     = OMAP3630_PERIPH_DPLL_SD_DIV_MASK,
 604         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
 605         .min_divider    = 1,
 606         .max_divider    = OMAP3_MAX_DPLL_DIV,
 607         .flags          = DPLL_J_TYPE
 608 };
 609
 610 static struct clk dpll4_ck = {
 611         .name           = "dpll4_ck",
 612         .ops            = &clkops_omap3_noncore_dpll_ops,
 613         .parent         = &sys_ck,
 614         .dpll_data      = &dpll4_dd,
 615         .round_rate     = &omap2_dpll_round_rate,
 616         .set_rate       = &omap3_dpll4_set_rate,
 617         .clkdm_name     = "dpll4_clkdm",
 618         .recalc         = &omap3_dpll_recalc,
 619 };
 620
 621 /*
 622  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 623  * DPLL isn't bypassed --
 624  * XXX does this serve any downstream clocks?
 625  */
 626 static struct clk dpll4_x2_ck = {
 627         .name           = "dpll4_x2_ck",
 628         .ops            = &clkops_null,
 629         .parent         = &dpll4_ck,
 630         .clkdm_name     = "dpll4_clkdm",
 631         .recalc         = &omap3_clkoutx2_recalc,
 632 };
 633
 634 static const struct clksel dpll4_clksel[] = {
 635         { .parent = &dpll4_ck, .rates = dpll4_rates },
 636         { .parent = NULL }
 637 };
 638
 639 /* This virtual clock is the source for dpll4_m2x2_ck */
 640 static struct clk dpll4_m2_ck = {
 641         .name           = "dpll4_m2_ck",
 642         .ops            = &clkops_null,
 643         .parent         = &dpll4_ck,
 644         .init           = &omap2_init_clksel_parent,
 645         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 646         .clksel_mask    = OMAP3630_DIV_96M_MASK,
 647         .clksel         = dpll4_clksel,
 648         .clkdm_name     = "dpll4_clkdm",
 649         .recalc         = &omap2_clksel_recalc,
 650 };
 651
 652 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 653 static struct clk dpll4_m2x2_ck = {
 654         .name           = "dpll4_m2x2_ck",
 655         .ops            = &clkops_omap2_dflt_wait,
 656         .parent         = &dpll4_m2_ck,
 657         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 658         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 659         .flags          = INVERT_ENABLE,
 660         .clkdm_name     = "dpll4_clkdm",
 661         .recalc         = &omap3_clkoutx2_recalc,
 662 };
 663
 664 /*
 665  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
 666  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
 667  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
 668  * CM_96K_(F)CLK.
 669  */
 670
 671 /* Adding 192MHz Clock node needed by SGX */
 672 static struct clk omap_192m_alwon_fck = {
 673         .name           = "omap_192m_alwon_fck",
 674         .ops            = &clkops_null,
 675         .parent         = &dpll4_m2x2_ck,
 676         .recalc         = &followparent_recalc,
 677 };
 678
 679 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
 680         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
 681         { .div = 2, .val = 2, .flags = RATE_IN_36XX },
 682         { .div = 0 }
 683 };
 684
 685 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 686         { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
 687         { .parent = NULL }
 688 };
 689
 690 static const struct clksel_rate omap_96m_dpll_rates[] = {
 691         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 692         { .div = 0 }
 693 };
 694
 695 static const struct clksel_rate omap_96m_sys_rates[] = {
 696         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 697         { .div = 0 }
 698 };
 699
 700 static struct clk omap_96m_alwon_fck = {
 701         .name           = "omap_96m_alwon_fck",
 702         .ops            = &clkops_null,
 703         .parent         = &dpll4_m2x2_ck,
 704         .recalc         = &followparent_recalc,
 705 };
 706
 707 static struct clk omap_96m_alwon_fck_3630 = {
 708         .name           = "omap_96m_alwon_fck",
 709         .parent         = &omap_192m_alwon_fck,
 710         .init           = &omap2_init_clksel_parent,
 711         .ops            = &clkops_null,
 712         .recalc         = &omap2_clksel_recalc,
 713         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
 714         .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
 715         .clksel         = omap_96m_alwon_fck_clksel
 716 };
 717
 718 static struct clk cm_96m_fck = {
 719         .name           = "cm_96m_fck",
 720         .ops            = &clkops_null,
 721         .parent         = &omap_96m_alwon_fck,
 722         .recalc         = &followparent_recalc,
 723 };
 724
 725 static const struct clksel omap_96m_fck_clksel[] = {
 726         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
 727         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
 728         { .parent = NULL }
 729 };
 730
 731 static struct clk omap_96m_fck = {
 732         .name           = "omap_96m_fck",
 733         .ops            = &clkops_null,
 734         .parent         = &sys_ck,
 735         .init           = &omap2_init_clksel_parent,
 736         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 737         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
 738         .clksel         = omap_96m_fck_clksel,
 739         .recalc         = &omap2_clksel_recalc,
 740 };
 741
 742 /* This virtual clock is the source for dpll4_m3x2_ck */
 743 static struct clk dpll4_m3_ck = {
 744         .name           = "dpll4_m3_ck",
 745         .ops            = &clkops_null,
 746         .parent         = &dpll4_ck,
 747         .init           = &omap2_init_clksel_parent,
 748         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 749         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 750         .clksel         = dpll4_clksel,
 751         .clkdm_name     = "dpll4_clkdm",
 752         .recalc         = &omap2_clksel_recalc,
 753 };
 754
 755 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 756 static struct clk dpll4_m3x2_ck = {
 757         .name           = "dpll4_m3x2_ck",
 758         .ops            = &clkops_omap2_dflt_wait,
 759         .parent         = &dpll4_m3_ck,
 760         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 761         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 762         .flags          = INVERT_ENABLE,
 763         .clkdm_name     = "dpll4_clkdm",
 764         .recalc         = &omap3_clkoutx2_recalc,
 765 };
 766
 767 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 768         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 769         { .div = 0 }
 770 };
 771
 772 static const struct clksel_rate omap_54m_alt_rates[] = {
 773         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 774         { .div = 0 }
 775 };
 776
 777 static const struct clksel omap_54m_clksel[] = {
 778         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
 779         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 780         { .parent = NULL }
 781 };
 782
 783 static struct clk omap_54m_fck = {
 784         .name           = "omap_54m_fck",
 785         .ops            = &clkops_null,
 786         .init           = &omap2_init_clksel_parent,
 787         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 788         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
 789         .clksel         = omap_54m_clksel,
 790         .recalc         = &omap2_clksel_recalc,
 791 };
 792
 793 static const struct clksel_rate omap_48m_cm96m_rates[] = {
 794         { .div = 2, .val = 0, .flags = RATE_IN_3XXX },
 795         { .div = 0 }
 796 };
 797
 798 static const struct clksel_rate omap_48m_alt_rates[] = {
 799         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 800         { .div = 0 }
 801 };
 802
 803 static const struct clksel omap_48m_clksel[] = {
 804         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
 805         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 806         { .parent = NULL }
 807 };
 808
 809 static struct clk omap_48m_fck = {
 810         .name           = "omap_48m_fck",
 811         .ops            = &clkops_null,
 812         .init           = &omap2_init_clksel_parent,
 813         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 814         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
 815         .clksel         = omap_48m_clksel,
 816         .recalc         = &omap2_clksel_recalc,
 817 };
 818
 819 static struct clk omap_12m_fck = {
 820         .name           = "omap_12m_fck",
 821         .ops            = &clkops_null,
 822         .parent         = &omap_48m_fck,
 823         .fixed_div      = 4,
 824         .recalc         = &omap_fixed_divisor_recalc,
 825 };
 826
 827 /* This virtual clock is the source for dpll4_m4x2_ck */
 828 static struct clk dpll4_m4_ck = {
 829         .name           = "dpll4_m4_ck",
 830         .ops            = &clkops_null,
 831         .parent         = &dpll4_ck,
 832         .init           = &omap2_init_clksel_parent,
 833         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 834         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 835         .clksel         = dpll4_clksel,
 836         .clkdm_name     = "dpll4_clkdm",
 837         .recalc         = &omap2_clksel_recalc,
 838         .set_rate       = &omap2_clksel_set_rate,
 839         .round_rate     = &omap2_clksel_round_rate,
 840 };
 841
 842 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 843 static struct clk dpll4_m4x2_ck = {
 844         .name           = "dpll4_m4x2_ck",
 845         .ops            = &clkops_omap2_dflt_wait,
 846         .parent         = &dpll4_m4_ck,
 847         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 848         .enable_bit     = OMAP3430_PWRDN_DSS1_SHIFT,
 849         .flags          = INVERT_ENABLE,
 850         .clkdm_name     = "dpll4_clkdm",
 851         .recalc         = &omap3_clkoutx2_recalc,
 852 };
 853
 854 /* This virtual clock is the source for dpll4_m5x2_ck */
 855 static struct clk dpll4_m5_ck = {
 856         .name           = "dpll4_m5_ck",
 857         .ops            = &clkops_null,
 858         .parent         = &dpll4_ck,
 859         .init           = &omap2_init_clksel_parent,
 860         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 861         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 862         .clksel         = dpll4_clksel,
 863         .clkdm_name     = "dpll4_clkdm",
 864         .set_rate       = &omap2_clksel_set_rate,
 865         .round_rate     = &omap2_clksel_round_rate,
 866         .recalc         = &omap2_clksel_recalc,
 867 };
 868
 869 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 870 static struct clk dpll4_m5x2_ck = {
 871         .name           = "dpll4_m5x2_ck",
 872         .ops            = &clkops_omap2_dflt_wait,
 873         .parent         = &dpll4_m5_ck,
 874         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 875         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 876         .flags          = INVERT_ENABLE,
 877         .clkdm_name     = "dpll4_clkdm",
 878         .recalc         = &omap3_clkoutx2_recalc,
 879 };
 880
 881 /* This virtual clock is the source for dpll4_m6x2_ck */
 882 static struct clk dpll4_m6_ck = {
 883         .name           = "dpll4_m6_ck",
 884         .ops            = &clkops_null,
 885         .parent         = &dpll4_ck,
 886         .init           = &omap2_init_clksel_parent,
 887         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 888         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 889         .clksel         = dpll4_clksel,
 890         .clkdm_name     = "dpll4_clkdm",
 891         .recalc         = &omap2_clksel_recalc,
 892 };
 893
 894 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 895 static struct clk dpll4_m6x2_ck = {
 896         .name           = "dpll4_m6x2_ck",
 897         .ops            = &clkops_omap2_dflt_wait,
 898         .parent         = &dpll4_m6_ck,
 899         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 900         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 901         .flags          = INVERT_ENABLE,
 902         .clkdm_name     = "dpll4_clkdm",
 903         .recalc         = &omap3_clkoutx2_recalc,
 904 };
 905
 906 static struct clk emu_per_alwon_ck = {
 907         .name           = "emu_per_alwon_ck",
 908         .ops            = &clkops_null,
 909         .parent         = &dpll4_m6x2_ck,
 910         .clkdm_name     = "dpll4_clkdm",
 911         .recalc         = &followparent_recalc,
 912 };
 913
 914 /* DPLL5 */
 915 /* Supplies 120MHz clock, USIM source clock */
 916 /* Type: DPLL */
 917 /* 3430ES2 only */
 918 static struct dpll_data dpll5_dd = {
 919         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 920         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 921         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 922         .clk_bypass     = &sys_ck,
 923         .clk_ref        = &sys_ck,
 924         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
 925         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 926         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 927         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
 928         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 929         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 930         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 931         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
 932         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
 933         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 934         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 935         .max_multiplier = OMAP3_MAX_DPLL_MULT,
 936         .min_divider    = 1,
 937         .max_divider    = OMAP3_MAX_DPLL_DIV,
 938 };
 939
 940 static struct clk dpll5_ck = {
 941         .name           = "dpll5_ck",
 942         .ops            = &clkops_omap3_noncore_dpll_ops,
 943         .parent         = &sys_ck,
 944         .dpll_data      = &dpll5_dd,
 945         .round_rate     = &omap2_dpll_round_rate,
 946         .set_rate       = &omap3_noncore_dpll_set_rate,
 947         .clkdm_name     = "dpll5_clkdm",
 948         .recalc         = &omap3_dpll_recalc,
 949 };
 950
 951 static const struct clksel div16_dpll5_clksel[] = {
 952         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 953         { .parent = NULL }
 954 };
 955
 956 static struct clk dpll5_m2_ck = {
 957         .name           = "dpll5_m2_ck",
 958         .ops            = &clkops_null,
 959         .parent         = &dpll5_ck,
 960         .init           = &omap2_init_clksel_parent,
 961         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 962         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 963         .clksel         = div16_dpll5_clksel,
 964         .clkdm_name     = "dpll5_clkdm",
 965         .recalc         = &omap2_clksel_recalc,
 966 };
 967
 968 /* CM EXTERNAL CLOCK OUTPUTS */
 969
 970 static const struct clksel_rate clkout2_src_core_rates[] = {
 971         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
 972         { .div = 0 }
 973 };
 974
 975 static const struct clksel_rate clkout2_src_sys_rates[] = {
 976         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
 977         { .div = 0 }
 978 };
 979
 980 static const struct clksel_rate clkout2_src_96m_rates[] = {
 981         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
 982         { .div = 0 }
 983 };
 984
 985 static const struct clksel_rate clkout2_src_54m_rates[] = {
 986         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
 987         { .div = 0 }
 988 };
 989
 990 static const struct clksel clkout2_src_clksel[] = {
 991         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
 992         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
 993         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
 994         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
 995         { .parent = NULL }
 996 };
 997
 998 static struct clk clkout2_src_ck = {
 999         .name           = "clkout2_src_ck",
1000         .ops            = &clkops_omap2_dflt,
1001         .init           = &omap2_init_clksel_parent,
1002         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
1003         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1004         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1005         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1006         .clksel         = clkout2_src_clksel,
1007         .clkdm_name     = "core_clkdm",
1008         .recalc         = &omap2_clksel_recalc,
1009 };
1010
1011 static const struct clksel_rate sys_clkout2_rates[] = {
1012         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1013         { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1014         { .div = 4, .val = 2, .flags = RATE_IN_3XXX },
1015         { .div = 8, .val = 3, .flags = RATE_IN_3XXX },
1016         { .div = 16, .val = 4, .flags = RATE_IN_3XXX },
1017         { .div = 0 },
1018 };
1019
1020 static const struct clksel sys_clkout2_clksel[] = {
1021         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1022         { .parent = NULL },
1023 };
1024
1025 static struct clk sys_clkout2 = {
1026         .name           = "sys_clkout2",
1027         .ops            = &clkops_null,
1028         .init           = &omap2_init_clksel_parent,
1029         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1030         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1031         .clksel         = sys_clkout2_clksel,
1032         .recalc         = &omap2_clksel_recalc,
1033         .round_rate     = &omap2_clksel_round_rate,
1034         .set_rate       = &omap2_clksel_set_rate
1035 };
1036
1037 /* CM OUTPUT CLOCKS */
1038
1039 static struct clk corex2_fck = {
1040         .name           = "corex2_fck",
1041         .ops            = &clkops_null,
1042         .parent         = &dpll3_m2x2_ck,
1043         .recalc         = &followparent_recalc,
1044 };
1045
1046 /* DPLL power domain clock controls */
1047
1048 static const struct clksel_rate div4_rates[] = {
1049         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1050         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1051         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1052         { .div = 0 }
1053 };
1054
1055 static const struct clksel div4_core_clksel[] = {
1056         { .parent = &core_ck, .rates = div4_rates },
1057         { .parent = NULL }
1058 };
1059
1060 /*
1061  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1062  * may be inconsistent here?
1063  */
1064 static struct clk dpll1_fck = {
1065         .name           = "dpll1_fck",
1066         .ops            = &clkops_null,
1067         .parent         = &core_ck,
1068         .init           = &omap2_init_clksel_parent,
1069         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1070         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1071         .clksel         = div4_core_clksel,
1072         .recalc         = &omap2_clksel_recalc,
1073 };
1074
1075 static struct clk mpu_ck = {
1076         .name           = "mpu_ck",
1077         .ops            = &clkops_null,
1078         .parent         = &dpll1_x2m2_ck,
1079         .clkdm_name     = "mpu_clkdm",
1080         .recalc         = &followparent_recalc,
1081 };
1082
1083 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1084 static const struct clksel_rate arm_fck_rates[] = {
1085         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1086         { .div = 2, .val = 1, .flags = RATE_IN_3XXX },
1087         { .div = 0 },
1088 };
1089
1090 static const struct clksel arm_fck_clksel[] = {
1091         { .parent = &mpu_ck, .rates = arm_fck_rates },
1092         { .parent = NULL }
1093 };
1094
1095 static struct clk arm_fck = {
1096         .name           = "arm_fck",
1097         .ops            = &clkops_null,
1098         .parent         = &mpu_ck,
1099         .init           = &omap2_init_clksel_parent,
1100         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1101         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1102         .clksel         = arm_fck_clksel,
1103         .clkdm_name     = "mpu_clkdm",
1104         .recalc         = &omap2_clksel_recalc,
1105 };
1106
1107 /* XXX What about neon_clkdm ? */
1108
1109 /*
1110  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1111  * although it is referenced - so this is a guess
1112  */
1113 static struct clk emu_mpu_alwon_ck = {
1114         .name           = "emu_mpu_alwon_ck",
1115         .ops            = &clkops_null,
1116         .parent         = &mpu_ck,
1117         .recalc         = &followparent_recalc,
1118 };
1119
1120 static struct clk dpll2_fck = {
1121         .name           = "dpll2_fck",
1122         .ops            = &clkops_null,
1123         .parent         = &core_ck,
1124         .init           = &omap2_init_clksel_parent,
1125         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1126         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1127         .clksel         = div4_core_clksel,
1128         .recalc         = &omap2_clksel_recalc,
1129 };
1130
1131 static struct clk iva2_ck = {
1132         .name           = "iva2_ck",
1133         .ops            = &clkops_omap2_dflt_wait,
1134         .parent         = &dpll2_m2_ck,
1135         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1136         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1137         .clkdm_name     = "iva2_clkdm",
1138         .recalc         = &followparent_recalc,
1139 };
1140
1141 /* Common interface clocks */
1142
1143 static const struct clksel div2_core_clksel[] = {
1144         { .parent = &core_ck, .rates = div2_rates },
1145         { .parent = NULL }
1146 };
1147
1148 static struct clk l3_ick = {
1149         .name           = "l3_ick",
1150         .ops            = &clkops_null,
1151         .parent         = &core_ck,
1152         .init           = &omap2_init_clksel_parent,
1153         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1154         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1155         .clksel         = div2_core_clksel,
1156         .clkdm_name     = "core_l3_clkdm",
1157         .recalc         = &omap2_clksel_recalc,
1158 };
1159
1160 static const struct clksel div2_l3_clksel[] = {
1161         { .parent = &l3_ick, .rates = div2_rates },
1162         { .parent = NULL }
1163 };
1164
1165 static struct clk l4_ick = {
1166         .name           = "l4_ick",
1167         .ops            = &clkops_null,
1168         .parent         = &l3_ick,
1169         .init           = &omap2_init_clksel_parent,
1170         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1171         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1172         .clksel         = div2_l3_clksel,
1173         .clkdm_name     = "core_l4_clkdm",
1174         .recalc         = &omap2_clksel_recalc,
1175
1176 };
1177
1178 static const struct clksel div2_l4_clksel[] = {
1179         { .parent = &l4_ick, .rates = div2_rates },
1180         { .parent = NULL }
1181 };
1182
1183 static struct clk rm_ick = {
1184         .name           = "rm_ick",
1185         .ops            = &clkops_null,
1186         .parent         = &l4_ick,
1187         .init           = &omap2_init_clksel_parent,
1188         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1189         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1190         .clksel         = div2_l4_clksel,
1191         .recalc         = &omap2_clksel_recalc,
1192 };
1193
1194 /* GFX power domain */
1195
1196 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1197
1198 static const struct clksel gfx_l3_clksel[] = {
1199         { .parent = &l3_ick, .rates = gfx_l3_rates },
1200         { .parent = NULL }
1201 };
1202
1203 /*
1204  * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
1205  * This interface clock does not have a CM_AUTOIDLE bit
1206  */
1207 static struct clk gfx_l3_ck = {
1208         .name           = "gfx_l3_ck",
1209         .ops            = &clkops_omap2_dflt_wait,
1210         .parent         = &l3_ick,
1211         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1212         .enable_bit     = OMAP_EN_GFX_SHIFT,
1213         .recalc         = &followparent_recalc,
1214 };
1215
1216 static struct clk gfx_l3_fck = {
1217         .name           = "gfx_l3_fck",
1218         .ops            = &clkops_null,
1219         .parent         = &gfx_l3_ck,
1220         .init           = &omap2_init_clksel_parent,
1221         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1222         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1223         .clksel         = gfx_l3_clksel,
1224         .clkdm_name     = "gfx_3430es1_clkdm",
1225         .recalc         = &omap2_clksel_recalc,
1226 };
1227
1228 static struct clk gfx_l3_ick = {
1229         .name           = "gfx_l3_ick",
1230         .ops            = &clkops_null,
1231         .parent         = &gfx_l3_ck,
1232         .clkdm_name     = "gfx_3430es1_clkdm",
1233         .recalc         = &followparent_recalc,
1234 };
1235
1236 static struct clk gfx_cg1_ck = {
1237         .name           = "gfx_cg1_ck",
1238         .ops            = &clkops_omap2_dflt_wait,
1239         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1240         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1241         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1242         .clkdm_name     = "gfx_3430es1_clkdm",
1243         .recalc         = &followparent_recalc,
1244 };
1245
1246 static struct clk gfx_cg2_ck = {
1247         .name           = "gfx_cg2_ck",
1248         .ops            = &clkops_omap2_dflt_wait,
1249         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1250         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1251         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1252         .clkdm_name     = "gfx_3430es1_clkdm",
1253         .recalc         = &followparent_recalc,
1254 };
1255
1256 /* SGX power domain - 3430ES2 only */
1257
1258 static const struct clksel_rate sgx_core_rates[] = {
1259         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1260         { .div = 3, .val = 0, .flags = RATE_IN_3XXX },
1261         { .div = 4, .val = 1, .flags = RATE_IN_3XXX },
1262         { .div = 6, .val = 2, .flags = RATE_IN_3XXX },
1263         { .div = 0 },
1264 };
1265
1266 static const struct clksel_rate sgx_192m_rates[] = {
1267         { .div = 1,  .val = 4, .flags = RATE_IN_36XX },
1268         { .div = 0 },
1269 };
1270
1271 static const struct clksel_rate sgx_corex2_rates[] = {
1272         { .div = 3, .val = 6, .flags = RATE_IN_36XX },
1273         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1274         { .div = 0 },
1275 };
1276
1277 static const struct clksel_rate sgx_96m_rates[] = {
1278         { .div = 1,  .val = 3, .flags = RATE_IN_3XXX },
1279         { .div = 0 },
1280 };
1281
1282 static const struct clksel sgx_clksel[] = {
1283         { .parent = &core_ck,    .rates = sgx_core_rates },
1284         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1285         { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1286         { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1287         { .parent = NULL }
1288 };
1289
1290 static struct clk sgx_fck = {
1291         .name           = "sgx_fck",
1292         .ops            = &clkops_omap2_dflt_wait,
1293         .init           = &omap2_init_clksel_parent,
1294         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1295         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1296         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1297         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1298         .clksel         = sgx_clksel,
1299         .clkdm_name     = "sgx_clkdm",
1300         .recalc         = &omap2_clksel_recalc,
1301         .set_rate       = &omap2_clksel_set_rate,
1302         .round_rate     = &omap2_clksel_round_rate
1303 };
1304
1305 /* This interface clock does not have a CM_AUTOIDLE bit */
1306 static struct clk sgx_ick = {
1307         .name           = "sgx_ick",
1308         .ops            = &clkops_omap2_dflt_wait,
1309         .parent         = &l3_ick,
1310         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1311         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1312         .clkdm_name     = "sgx_clkdm",
1313         .recalc         = &followparent_recalc,
1314 };
1315
1316 /* CORE power domain */
1317
1318 static struct clk d2d_26m_fck = {
1319         .name           = "d2d_26m_fck",
1320         .ops            = &clkops_omap2_dflt_wait,
1321         .parent         = &sys_ck,
1322         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1323         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1324         .clkdm_name     = "d2d_clkdm",
1325         .recalc         = &followparent_recalc,
1326 };
1327
1328 static struct clk modem_fck = {
1329         .name           = "modem_fck",
1330         .ops            = &clkops_omap2_mdmclk_dflt_wait,
1331         .parent         = &sys_ck,
1332         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1333         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
1334         .clkdm_name     = "d2d_clkdm",
1335         .recalc         = &followparent_recalc,
1336 };
1337
1338 static struct clk sad2d_ick = {
1339         .name           = "sad2d_ick",
1340         .ops            = &clkops_omap2_iclk_dflt_wait,
1341         .parent         = &l3_ick,
1342         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1343         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
1344         .clkdm_name     = "d2d_clkdm",
1345         .recalc         = &followparent_recalc,
1346 };
1347
1348 static struct clk mad2d_ick = {
1349         .name           = "mad2d_ick",
1350         .ops            = &clkops_omap2_iclk_dflt_wait,
1351         .parent         = &l3_ick,
1352         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1353         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
1354         .clkdm_name     = "d2d_clkdm",
1355         .recalc         = &followparent_recalc,
1356 };
1357
1358 static const struct clksel omap343x_gpt_clksel[] = {
1359         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1360         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1361         { .parent = NULL}
1362 };
1363
1364 static struct clk gpt10_fck = {
1365         .name           = "gpt10_fck",
1366         .ops            = &clkops_omap2_dflt_wait,
1367         .parent         = &sys_ck,
1368         .init           = &omap2_init_clksel_parent,
1369         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1370         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1371         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1372         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1373         .clksel         = omap343x_gpt_clksel,
1374         .clkdm_name     = "core_l4_clkdm",
1375         .recalc         = &omap2_clksel_recalc,
1376 };
1377
1378 static struct clk gpt11_fck = {
1379         .name           = "gpt11_fck",
1380         .ops            = &clkops_omap2_dflt_wait,
1381         .parent         = &sys_ck,
1382         .init           = &omap2_init_clksel_parent,
1383         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1384         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1385         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1386         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1387         .clksel         = omap343x_gpt_clksel,
1388         .clkdm_name     = "core_l4_clkdm",
1389         .recalc         = &omap2_clksel_recalc,
1390 };
1391
1392 static struct clk cpefuse_fck = {
1393         .name           = "cpefuse_fck",
1394         .ops            = &clkops_omap2_dflt,
1395         .parent         = &sys_ck,
1396         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1397         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1398         .recalc         = &followparent_recalc,
1399 };
1400
1401 static struct clk ts_fck = {
1402         .name           = "ts_fck",
1403         .ops            = &clkops_omap2_dflt,
1404         .parent         = &omap_32k_fck,
1405         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1406         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1407         .recalc         = &followparent_recalc,
1408 };
1409
1410 static struct clk usbtll_fck = {
1411         .name           = "usbtll_fck",
1412         .ops            = &clkops_omap2_dflt_wait,
1413         .parent         = &dpll5_m2_ck,
1414         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1415         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1416         .recalc         = &followparent_recalc,
1417 };
1418
1419 /* CORE 96M FCLK-derived clocks */
1420
1421 static struct clk core_96m_fck = {
1422         .name           = "core_96m_fck",
1423         .ops            = &clkops_null,
1424         .parent         = &omap_96m_fck,
1425         .clkdm_name     = "core_l4_clkdm",
1426         .recalc         = &followparent_recalc,
1427 };
1428
1429 static struct clk mmchs3_fck = {
1430         .name           = "mmchs3_fck",
1431         .ops            = &clkops_omap2_dflt_wait,
1432         .parent         = &core_96m_fck,
1433         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1434         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1435         .clkdm_name     = "core_l4_clkdm",
1436         .recalc         = &followparent_recalc,
1437 };
1438
1439 static struct clk mmchs2_fck = {
1440         .name           = "mmchs2_fck",
1441         .ops            = &clkops_omap2_dflt_wait,
1442         .parent         = &core_96m_fck,
1443         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1444         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1445         .clkdm_name     = "core_l4_clkdm",
1446         .recalc         = &followparent_recalc,
1447 };
1448
1449 static struct clk mspro_fck = {
1450         .name           = "mspro_fck",
1451         .ops            = &clkops_omap2_dflt_wait,
1452         .parent         = &core_96m_fck,
1453         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1454         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1455         .clkdm_name     = "core_l4_clkdm",
1456         .recalc         = &followparent_recalc,
1457 };
1458
1459 static struct clk mmchs1_fck = {
1460         .name           = "mmchs1_fck",
1461         .ops            = &clkops_omap2_dflt_wait,
1462         .parent         = &core_96m_fck,
1463         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1464         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1465         .clkdm_name     = "core_l4_clkdm",
1466         .recalc         = &followparent_recalc,
1467 };
1468
1469 static struct clk i2c3_fck = {
1470         .name           = "i2c3_fck",
1471         .ops            = &clkops_omap2_dflt_wait,
1472         .parent         = &core_96m_fck,
1473         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1474         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1475         .clkdm_name     = "core_l4_clkdm",
1476         .recalc         = &followparent_recalc,
1477 };
1478
1479 static struct clk i2c2_fck = {
1480         .name           = "i2c2_fck",
1481         .ops            = &clkops_omap2_dflt_wait,
1482         .parent         = &core_96m_fck,
1483         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1484         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1485         .clkdm_name     = "core_l4_clkdm",
1486         .recalc         = &followparent_recalc,
1487 };
1488
1489 static struct clk i2c1_fck = {
1490         .name           = "i2c1_fck",
1491         .ops            = &clkops_omap2_dflt_wait,
1492         .parent         = &core_96m_fck,
1493         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1494         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1495         .clkdm_name     = "core_l4_clkdm",
1496         .recalc         = &followparent_recalc,
1497 };
1498
1499 /*
1500  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1501  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1502  */
1503 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1504         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
1505         { .div = 0 }
1506 };
1507
1508 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1509         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1510         { .div = 0 }
1511 };
1512
1513 static const struct clksel mcbsp_15_clksel[] = {
1514         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1515         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1516         { .parent = NULL }
1517 };
1518
1519 static struct clk mcbsp5_fck = {
1520         .name           = "mcbsp5_fck",
1521         .ops            = &clkops_omap2_dflt_wait,
1522         .init           = &omap2_init_clksel_parent,
1523         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1524         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1525         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1526         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1527         .clksel         = mcbsp_15_clksel,
1528         .clkdm_name     = "core_l4_clkdm",
1529         .recalc         = &omap2_clksel_recalc,
1530 };
1531
1532 static struct clk mcbsp1_fck = {
1533         .name           = "mcbsp1_fck",
1534         .ops            = &clkops_omap2_dflt_wait,
1535         .init           = &omap2_init_clksel_parent,
1536         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1537         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1538         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1539         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1540         .clksel         = mcbsp_15_clksel,
1541         .clkdm_name     = "core_l4_clkdm",
1542         .recalc         = &omap2_clksel_recalc,
1543 };
1544
1545 /* CORE_48M_FCK-derived clocks */
1546
1547 static struct clk core_48m_fck = {
1548         .name           = "core_48m_fck",
1549         .ops            = &clkops_null,
1550         .parent         = &omap_48m_fck,
1551         .clkdm_name     = "core_l4_clkdm",
1552         .recalc         = &followparent_recalc,
1553 };
1554
1555 static struct clk mcspi4_fck = {
1556         .name           = "mcspi4_fck",
1557         .ops            = &clkops_omap2_dflt_wait,
1558         .parent         = &core_48m_fck,
1559         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1560         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1561         .recalc         = &followparent_recalc,
1562         .clkdm_name     = "core_l4_clkdm",
1563 };
1564
1565 static struct clk mcspi3_fck = {
1566         .name           = "mcspi3_fck",
1567         .ops            = &clkops_omap2_dflt_wait,
1568         .parent         = &core_48m_fck,
1569         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1570         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1571         .recalc         = &followparent_recalc,
1572         .clkdm_name     = "core_l4_clkdm",
1573 };
1574
1575 static struct clk mcspi2_fck = {
1576         .name           = "mcspi2_fck",
1577         .ops            = &clkops_omap2_dflt_wait,
1578         .parent         = &core_48m_fck,
1579         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1580         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1581         .recalc         = &followparent_recalc,
1582         .clkdm_name     = "core_l4_clkdm",
1583 };
1584
1585 static struct clk mcspi1_fck = {
1586         .name           = "mcspi1_fck",
1587         .ops            = &clkops_omap2_dflt_wait,
1588         .parent         = &core_48m_fck,
1589         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1590         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1591         .recalc         = &followparent_recalc,
1592         .clkdm_name     = "core_l4_clkdm",
1593 };
1594
1595 static struct clk uart2_fck = {
1596         .name           = "uart2_fck",
1597         .ops            = &clkops_omap2_dflt_wait,
1598         .parent         = &core_48m_fck,
1599         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1600         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1601         .clkdm_name     = "core_l4_clkdm",
1602         .recalc         = &followparent_recalc,
1603 };
1604
1605 static struct clk uart1_fck = {
1606         .name           = "uart1_fck",
1607         .ops            = &clkops_omap2_dflt_wait,
1608         .parent         = &core_48m_fck,
1609         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1610         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1611         .clkdm_name     = "core_l4_clkdm",
1612         .recalc         = &followparent_recalc,
1613 };
1614
1615 static struct clk fshostusb_fck = {
1616         .name           = "fshostusb_fck",
1617         .ops            = &clkops_omap2_dflt_wait,
1618         .parent         = &core_48m_fck,
1619         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1620         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1621         .recalc         = &followparent_recalc,
1622 };
1623
1624 /* CORE_12M_FCK based clocks */
1625
1626 static struct clk core_12m_fck = {
1627         .name           = "core_12m_fck",
1628         .ops            = &clkops_null,
1629         .parent         = &omap_12m_fck,
1630         .clkdm_name     = "core_l4_clkdm",
1631         .recalc         = &followparent_recalc,
1632 };
1633
1634 static struct clk hdq_fck = {
1635         .name           = "hdq_fck",
1636         .ops            = &clkops_omap2_dflt_wait,
1637         .parent         = &core_12m_fck,
1638         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1639         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1640         .recalc         = &followparent_recalc,
1641 };
1642
1643 /* DPLL3-derived clock */
1644
1645 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1646         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
1647         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
1648         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
1649         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
1650         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
1651         { .div = 8, .val = 8, .flags = RATE_IN_3XXX },
1652         { .div = 0 }
1653 };
1654
1655 static const struct clksel ssi_ssr_clksel[] = {
1656         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1657         { .parent = NULL }
1658 };
1659
1660 static struct clk ssi_ssr_fck_3430es1 = {
1661         .name           = "ssi_ssr_fck",
1662         .ops            = &clkops_omap2_dflt,
1663         .init           = &omap2_init_clksel_parent,
1664         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1665         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1666         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1667         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1668         .clksel         = ssi_ssr_clksel,
1669         .clkdm_name     = "core_l4_clkdm",
1670         .recalc         = &omap2_clksel_recalc,
1671 };
1672
1673 static struct clk ssi_ssr_fck_3430es2 = {
1674         .name           = "ssi_ssr_fck",
1675         .ops            = &clkops_omap3430es2_ssi_wait,
1676         .init           = &omap2_init_clksel_parent,
1677         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1678         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1679         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1680         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1681         .clksel         = ssi_ssr_clksel,
1682         .clkdm_name     = "core_l4_clkdm",
1683         .recalc         = &omap2_clksel_recalc,
1684 };
1685
1686 static struct clk ssi_sst_fck_3430es1 = {
1687         .name           = "ssi_sst_fck",
1688         .ops            = &clkops_null,
1689         .parent         = &ssi_ssr_fck_3430es1,
1690         .fixed_div      = 2,
1691         .recalc         = &omap_fixed_divisor_recalc,
1692 };
1693
1694 static struct clk ssi_sst_fck_3430es2 = {
1695         .name           = "ssi_sst_fck",
1696         .ops            = &clkops_null,
1697         .parent         = &ssi_ssr_fck_3430es2,
1698         .fixed_div      = 2,
1699         .recalc         = &omap_fixed_divisor_recalc,
1700 };
1701
1702
1703
1704 /* CORE_L3_ICK based clocks */
1705
1706 /*
1707  * XXX must add clk_enable/clk_disable for these if standard code won't
1708  * handle it
1709  */
1710 static struct clk core_l3_ick = {
1711         .name           = "core_l3_ick",
1712         .ops            = &clkops_null,
1713         .parent         = &l3_ick,
1714         .clkdm_name     = "core_l3_clkdm",
1715         .recalc         = &followparent_recalc,
1716 };
1717
1718 static struct clk hsotgusb_ick_3430es1 = {
1719         .name           = "hsotgusb_ick",
1720         .ops            = &clkops_omap2_iclk_dflt,
1721         .parent         = &core_l3_ick,
1722         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1723         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1724         .clkdm_name     = "core_l3_clkdm",
1725         .recalc         = &followparent_recalc,
1726 };
1727
1728 static struct clk hsotgusb_ick_3430es2 = {
1729         .name           = "hsotgusb_ick",
1730         .ops            = &clkops_omap3430es2_iclk_hsotgusb_wait,
1731         .parent         = &core_l3_ick,
1732         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1733         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1734         .clkdm_name     = "core_l3_clkdm",
1735         .recalc         = &followparent_recalc,
1736 };
1737
1738 /* This interface clock does not have a CM_AUTOIDLE bit */
1739 static struct clk sdrc_ick = {
1740         .name           = "sdrc_ick",
1741         .ops            = &clkops_omap2_dflt_wait,
1742         .parent         = &core_l3_ick,
1743         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1744         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1745         .flags          = ENABLE_ON_INIT,
1746         .clkdm_name     = "core_l3_clkdm",
1747         .recalc         = &followparent_recalc,
1748 };
1749
1750 static struct clk gpmc_fck = {
1751         .name           = "gpmc_fck",
1752         .ops            = &clkops_null,
1753         .parent         = &core_l3_ick,
1754         .flags          = ENABLE_ON_INIT, /* huh? */
1755         .clkdm_name     = "core_l3_clkdm",
1756         .recalc         = &followparent_recalc,
1757 };
1758
1759 /* SECURITY_L3_ICK based clocks */
1760
1761 static struct clk security_l3_ick = {
1762         .name           = "security_l3_ick",
1763         .ops            = &clkops_null,
1764         .parent         = &l3_ick,
1765         .recalc         = &followparent_recalc,
1766 };
1767
1768 static struct clk pka_ick = {
1769         .name           = "pka_ick",
1770         .ops            = &clkops_omap2_iclk_dflt_wait,
1771         .parent         = &security_l3_ick,
1772         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1773         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1774         .recalc         = &followparent_recalc,
1775 };
1776
1777 /* CORE_L4_ICK based clocks */
1778
1779 static struct clk core_l4_ick = {
1780         .name           = "core_l4_ick",
1781         .ops            = &clkops_null,
1782         .parent         = &l4_ick,
1783         .clkdm_name     = "core_l4_clkdm",
1784         .recalc         = &followparent_recalc,
1785 };
1786
1787 static struct clk usbtll_ick = {
1788         .name           = "usbtll_ick",
1789         .ops            = &clkops_omap2_iclk_dflt_wait,
1790         .parent         = &core_l4_ick,
1791         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1792         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1793         .clkdm_name     = "core_l4_clkdm",
1794         .recalc         = &followparent_recalc,
1795 };
1796
1797 static struct clk mmchs3_ick = {
1798         .name           = "mmchs3_ick",
1799         .ops            = &clkops_omap2_iclk_dflt_wait,
1800         .parent         = &core_l4_ick,
1801         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1802         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1803         .clkdm_name     = "core_l4_clkdm",
1804         .recalc         = &followparent_recalc,
1805 };
1806
1807 /* Intersystem Communication Registers - chassis mode only */
1808 static struct clk icr_ick = {
1809         .name           = "icr_ick",
1810         .ops            = &clkops_omap2_iclk_dflt_wait,
1811         .parent         = &core_l4_ick,
1812         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1813         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1814         .clkdm_name     = "core_l4_clkdm",
1815         .recalc         = &followparent_recalc,
1816 };
1817
1818 static struct clk aes2_ick = {
1819         .name           = "aes2_ick",
1820         .ops            = &clkops_omap2_iclk_dflt_wait,
1821         .parent         = &core_l4_ick,
1822         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1823         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1824         .clkdm_name     = "core_l4_clkdm",
1825         .recalc         = &followparent_recalc,
1826 };
1827
1828 static struct clk sha12_ick = {
1829         .name           = "sha12_ick",
1830         .ops            = &clkops_omap2_iclk_dflt_wait,
1831         .parent         = &core_l4_ick,
1832         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1833         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1834         .clkdm_name     = "core_l4_clkdm",
1835         .recalc         = &followparent_recalc,
1836 };
1837
1838 static struct clk des2_ick = {
1839         .name           = "des2_ick",
1840         .ops            = &clkops_omap2_iclk_dflt_wait,
1841         .parent         = &core_l4_ick,
1842         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1844         .clkdm_name     = "core_l4_clkdm",
1845         .recalc         = &followparent_recalc,
1846 };
1847
1848 static struct clk mmchs2_ick = {
1849         .name           = "mmchs2_ick",
1850         .ops            = &clkops_omap2_iclk_dflt_wait,
1851         .parent         = &core_l4_ick,
1852         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1854         .clkdm_name     = "core_l4_clkdm",
1855         .recalc         = &followparent_recalc,
1856 };
1857
1858 static struct clk mmchs1_ick = {
1859         .name           = "mmchs1_ick",
1860         .ops            = &clkops_omap2_iclk_dflt_wait,
1861         .parent         = &core_l4_ick,
1862         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1863         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1864         .clkdm_name     = "core_l4_clkdm",
1865         .recalc         = &followparent_recalc,
1866 };
1867
1868 static struct clk mspro_ick = {
1869         .name           = "mspro_ick",
1870         .ops            = &clkops_omap2_iclk_dflt_wait,
1871         .parent         = &core_l4_ick,
1872         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1873         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1874         .clkdm_name     = "core_l4_clkdm",
1875         .recalc         = &followparent_recalc,
1876 };
1877
1878 static struct clk hdq_ick = {
1879         .name           = "hdq_ick",
1880         .ops            = &clkops_omap2_iclk_dflt_wait,
1881         .parent         = &core_l4_ick,
1882         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1883         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1884         .clkdm_name     = "core_l4_clkdm",
1885         .recalc         = &followparent_recalc,
1886 };
1887
1888 static struct clk mcspi4_ick = {
1889         .name           = "mcspi4_ick",
1890         .ops            = &clkops_omap2_iclk_dflt_wait,
1891         .parent         = &core_l4_ick,
1892         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1893         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1894         .clkdm_name     = "core_l4_clkdm",
1895         .recalc         = &followparent_recalc,
1896 };
1897
1898 static struct clk mcspi3_ick = {
1899         .name           = "mcspi3_ick",
1900         .ops            = &clkops_omap2_iclk_dflt_wait,
1901         .parent         = &core_l4_ick,
1902         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1903         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1904         .clkdm_name     = "core_l4_clkdm",
1905         .recalc         = &followparent_recalc,
1906 };
1907
1908 static struct clk mcspi2_ick = {
1909         .name           = "mcspi2_ick",
1910         .ops            = &clkops_omap2_iclk_dflt_wait,
1911         .parent         = &core_l4_ick,
1912         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1913         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1914         .clkdm_name     = "core_l4_clkdm",
1915         .recalc         = &followparent_recalc,
1916 };
1917
1918 static struct clk mcspi1_ick = {
1919         .name           = "mcspi1_ick",
1920         .ops            = &clkops_omap2_iclk_dflt_wait,
1921         .parent         = &core_l4_ick,
1922         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1923         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1924         .clkdm_name     = "core_l4_clkdm",
1925         .recalc         = &followparent_recalc,
1926 };
1927
1928 static struct clk i2c3_ick = {
1929         .name           = "i2c3_ick",
1930         .ops            = &clkops_omap2_iclk_dflt_wait,
1931         .parent         = &core_l4_ick,
1932         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1933         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1934         .clkdm_name     = "core_l4_clkdm",
1935         .recalc         = &followparent_recalc,
1936 };
1937
1938 static struct clk i2c2_ick = {
1939         .name           = "i2c2_ick",
1940         .ops            = &clkops_omap2_iclk_dflt_wait,
1941         .parent         = &core_l4_ick,
1942         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1943         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1944         .clkdm_name     = "core_l4_clkdm",
1945         .recalc         = &followparent_recalc,
1946 };
1947
1948 static struct clk i2c1_ick = {
1949         .name           = "i2c1_ick",
1950         .ops            = &clkops_omap2_iclk_dflt_wait,
1951         .parent         = &core_l4_ick,
1952         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1953         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1954         .clkdm_name     = "core_l4_clkdm",
1955         .recalc         = &followparent_recalc,
1956 };
1957
1958 static struct clk uart2_ick = {
1959         .name           = "uart2_ick",
1960         .ops            = &clkops_omap2_iclk_dflt_wait,
1961         .parent         = &core_l4_ick,
1962         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1963         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1964         .clkdm_name     = "core_l4_clkdm",
1965         .recalc         = &followparent_recalc,
1966 };
1967
1968 static struct clk uart1_ick = {
1969         .name           = "uart1_ick",
1970         .ops            = &clkops_omap2_iclk_dflt_wait,
1971         .parent         = &core_l4_ick,
1972         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1973         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1974         .clkdm_name     = "core_l4_clkdm",
1975         .recalc         = &followparent_recalc,
1976 };
1977
1978 static struct clk gpt11_ick = {
1979         .name           = "gpt11_ick",
1980         .ops            = &clkops_omap2_iclk_dflt_wait,
1981         .parent         = &core_l4_ick,
1982         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1983         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1984         .clkdm_name     = "core_l4_clkdm",
1985         .recalc         = &followparent_recalc,
1986 };
1987
1988 static struct clk gpt10_ick = {
1989         .name           = "gpt10_ick",
1990         .ops            = &clkops_omap2_iclk_dflt_wait,
1991         .parent         = &core_l4_ick,
1992         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1993         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1994         .clkdm_name     = "core_l4_clkdm",
1995         .recalc         = &followparent_recalc,
1996 };
1997
1998 static struct clk mcbsp5_ick = {
1999         .name           = "mcbsp5_ick",
2000         .ops            = &clkops_omap2_iclk_dflt_wait,
2001         .parent         = &core_l4_ick,
2002         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2003         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2004         .clkdm_name     = "core_l4_clkdm",
2005         .recalc         = &followparent_recalc,
2006 };
2007
2008 static struct clk mcbsp1_ick = {
2009         .name           = "mcbsp1_ick",
2010         .ops            = &clkops_omap2_iclk_dflt_wait,
2011         .parent         = &core_l4_ick,
2012         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2013         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2014         .clkdm_name     = "core_l4_clkdm",
2015         .recalc         = &followparent_recalc,
2016 };
2017
2018 static struct clk fac_ick = {
2019         .name           = "fac_ick",
2020         .ops            = &clkops_omap2_iclk_dflt_wait,
2021         .parent         = &core_l4_ick,
2022         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2023         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2024         .clkdm_name     = "core_l4_clkdm",
2025         .recalc         = &followparent_recalc,
2026 };
2027
2028 static struct clk mailboxes_ick = {
2029         .name           = "mailboxes_ick",
2030         .ops            = &clkops_omap2_iclk_dflt_wait,
2031         .parent         = &core_l4_ick,
2032         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2033         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2034         .clkdm_name     = "core_l4_clkdm",
2035         .recalc         = &followparent_recalc,
2036 };
2037
2038 static struct clk omapctrl_ick = {
2039         .name           = "omapctrl_ick",
2040         .ops            = &clkops_omap2_iclk_dflt_wait,
2041         .parent         = &core_l4_ick,
2042         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2043         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2044         .flags          = ENABLE_ON_INIT,
2045         .recalc         = &followparent_recalc,
2046 };
2047
2048 /* SSI_L4_ICK based clocks */
2049
2050 static struct clk ssi_l4_ick = {
2051         .name           = "ssi_l4_ick",
2052         .ops            = &clkops_null,
2053         .parent         = &l4_ick,
2054         .clkdm_name     = "core_l4_clkdm",
2055         .recalc         = &followparent_recalc,
2056 };
2057
2058 static struct clk ssi_ick_3430es1 = {
2059         .name           = "ssi_ick",
2060         .ops            = &clkops_omap2_iclk_dflt,
2061         .parent         = &ssi_l4_ick,
2062         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2063         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2064         .clkdm_name     = "core_l4_clkdm",
2065         .recalc         = &followparent_recalc,
2066 };
2067
2068 static struct clk ssi_ick_3430es2 = {
2069         .name           = "ssi_ick",
2070         .ops            = &clkops_omap3430es2_iclk_ssi_wait,
2071         .parent         = &ssi_l4_ick,
2072         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2073         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2074         .clkdm_name     = "core_l4_clkdm",
2075         .recalc         = &followparent_recalc,
2076 };
2077
2078 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2079  * but l4_ick makes more sense to me */
2080
2081 static const struct clksel usb_l4_clksel[] = {
2082         { .parent = &l4_ick, .rates = div2_rates },
2083         { .parent = NULL },
2084 };
2085
2086 static struct clk usb_l4_ick = {
2087         .name           = "usb_l4_ick",
2088         .ops            = &clkops_omap2_iclk_dflt_wait,
2089         .parent         = &l4_ick,
2090         .init           = &omap2_init_clksel_parent,
2091         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2092         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2093         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2094         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2095         .clksel         = usb_l4_clksel,
2096         .recalc         = &omap2_clksel_recalc,
2097 };
2098
2099 /* SECURITY_L4_ICK2 based clocks */
2100
2101 static struct clk security_l4_ick2 = {
2102         .name           = "security_l4_ick2",
2103         .ops            = &clkops_null,
2104         .parent         = &l4_ick,
2105         .recalc         = &followparent_recalc,
2106 };
2107
2108 static struct clk aes1_ick = {
2109         .name           = "aes1_ick",
2110         .ops            = &clkops_omap2_iclk_dflt_wait,
2111         .parent         = &security_l4_ick2,
2112         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2113         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2114         .recalc         = &followparent_recalc,
2115 };
2116
2117 static struct clk rng_ick = {
2118         .name           = "rng_ick",
2119         .ops            = &clkops_omap2_iclk_dflt_wait,
2120         .parent         = &security_l4_ick2,
2121         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2122         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2123         .recalc         = &followparent_recalc,
2124 };
2125
2126 static struct clk sha11_ick = {
2127         .name           = "sha11_ick",
2128         .ops            = &clkops_omap2_iclk_dflt_wait,
2129         .parent         = &security_l4_ick2,
2130         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2131         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2132         .recalc         = &followparent_recalc,
2133 };
2134
2135 static struct clk des1_ick = {
2136         .name           = "des1_ick",
2137         .ops            = &clkops_omap2_iclk_dflt_wait,
2138         .parent         = &security_l4_ick2,
2139         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2140         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2141         .recalc         = &followparent_recalc,
2142 };
2143
2144 /* DSS */
2145 static struct clk dss1_alwon_fck_3430es1 = {
2146         .name           = "dss1_alwon_fck",
2147         .ops            = &clkops_omap2_dflt,
2148         .parent         = &dpll4_m4x2_ck,
2149         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2150         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2151         .clkdm_name     = "dss_clkdm",
2152         .recalc         = &followparent_recalc,
2153 };
2154
2155 static struct clk dss1_alwon_fck_3430es2 = {
2156         .name           = "dss1_alwon_fck",
2157         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2158         .parent         = &dpll4_m4x2_ck,
2159         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2160         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2161         .clkdm_name     = "dss_clkdm",
2162         .recalc         = &followparent_recalc,
2163 };
2164
2165 static struct clk dss_tv_fck = {
2166         .name           = "dss_tv_fck",
2167         .ops            = &clkops_omap2_dflt,
2168         .parent         = &omap_54m_fck,
2169         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2170         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2171         .clkdm_name     = "dss_clkdm",
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 static struct clk dss_96m_fck = {
2176         .name           = "dss_96m_fck",
2177         .ops            = &clkops_omap2_dflt,
2178         .parent         = &omap_96m_fck,
2179         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2180         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2181         .clkdm_name     = "dss_clkdm",
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 static struct clk dss2_alwon_fck = {
2186         .name           = "dss2_alwon_fck",
2187         .ops            = &clkops_omap2_dflt,
2188         .parent         = &sys_ck,
2189         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2190         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2191         .clkdm_name     = "dss_clkdm",
2192         .recalc         = &followparent_recalc,
2193 };
2194
2195 static struct clk dss_ick_3430es1 = {
2196         /* Handles both L3 and L4 clocks */
2197         .name           = "dss_ick",
2198         .ops            = &clkops_omap2_iclk_dflt,
2199         .parent         = &l4_ick,
2200         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2201         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2202         .clkdm_name     = "dss_clkdm",
2203         .recalc         = &followparent_recalc,
2204 };
2205
2206 static struct clk dss_ick_3430es2 = {
2207         /* Handles both L3 and L4 clocks */
2208         .name           = "dss_ick",
2209         .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2210         .parent         = &l4_ick,
2211         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2212         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2213         .clkdm_name     = "dss_clkdm",
2214         .recalc         = &followparent_recalc,
2215 };
2216
2217 /* CAM */
2218
2219 static struct clk cam_mclk = {
2220         .name           = "cam_mclk",
2221         .ops            = &clkops_omap2_dflt,
2222         .parent         = &dpll4_m5x2_ck,
2223         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2224         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2225         .clkdm_name     = "cam_clkdm",
2226         .recalc         = &followparent_recalc,
2227 };
2228
2229 static struct clk cam_ick = {
2230         /* Handles both L3 and L4 clocks */
2231         .name           = "cam_ick",
2232         .ops            = &clkops_omap2_iclk_dflt,
2233         .parent         = &l4_ick,
2234         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2235         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2236         .clkdm_name     = "cam_clkdm",
2237         .recalc         = &followparent_recalc,
2238 };
2239
2240 static struct clk csi2_96m_fck = {
2241         .name           = "csi2_96m_fck",
2242         .ops            = &clkops_omap2_dflt,
2243         .parent         = &core_96m_fck,
2244         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2245         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2246         .clkdm_name     = "cam_clkdm",
2247         .recalc         = &followparent_recalc,
2248 };
2249
2250 /* USBHOST - 3430ES2 only */
2251
2252 static struct clk usbhost_120m_fck = {
2253         .name           = "usbhost_120m_fck",
2254         .ops            = &clkops_omap2_dflt,
2255         .parent         = &dpll5_m2_ck,
2256         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2257         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2258         .clkdm_name     = "usbhost_clkdm",
2259         .recalc         = &followparent_recalc,
2260 };
2261
2262 static struct clk usbhost_48m_fck = {
2263         .name           = "usbhost_48m_fck",
2264         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2265         .parent         = &omap_48m_fck,
2266         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2267         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2268         .clkdm_name     = "usbhost_clkdm",
2269         .recalc         = &followparent_recalc,
2270 };
2271
2272 static struct clk usbhost_ick = {
2273         /* Handles both L3 and L4 clocks */
2274         .name           = "usbhost_ick",
2275         .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
2276         .parent         = &l4_ick,
2277         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2278         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2279         .clkdm_name     = "usbhost_clkdm",
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 /* WKUP */
2284
2285 static const struct clksel_rate usim_96m_rates[] = {
2286         { .div = 2,  .val = 3, .flags = RATE_IN_3XXX },
2287         { .div = 4,  .val = 4, .flags = RATE_IN_3XXX },
2288         { .div = 8,  .val = 5, .flags = RATE_IN_3XXX },
2289         { .div = 10, .val = 6, .flags = RATE_IN_3XXX },
2290         { .div = 0 },
2291 };
2292
2293 static const struct clksel_rate usim_120m_rates[] = {
2294         { .div = 4,  .val = 7,  .flags = RATE_IN_3XXX },
2295         { .div = 8,  .val = 8,  .flags = RATE_IN_3XXX },
2296         { .div = 16, .val = 9,  .flags = RATE_IN_3XXX },
2297         { .div = 20, .val = 10, .flags = RATE_IN_3XXX },
2298         { .div = 0 },
2299 };
2300
2301 static const struct clksel usim_clksel[] = {
2302         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2303         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2304         { .parent = &sys_ck,            .rates = div2_rates },
2305         { .parent = NULL },
2306 };
2307
2308 /* 3430ES2 only */
2309 static struct clk usim_fck = {
2310         .name           = "usim_fck",
2311         .ops            = &clkops_omap2_dflt_wait,
2312         .init           = &omap2_init_clksel_parent,
2313         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2314         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2315         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2316         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2317         .clksel         = usim_clksel,
2318         .recalc         = &omap2_clksel_recalc,
2319 };
2320
2321 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2322 static struct clk gpt1_fck = {
2323         .name           = "gpt1_fck",
2324         .ops            = &clkops_omap2_dflt_wait,
2325         .init           = &omap2_init_clksel_parent,
2326         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2327         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2328         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2329         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2330         .clksel         = omap343x_gpt_clksel,
2331         .clkdm_name     = "wkup_clkdm",
2332         .recalc         = &omap2_clksel_recalc,
2333 };
2334
2335 static struct clk wkup_32k_fck = {
2336         .name           = "wkup_32k_fck",
2337         .ops            = &clkops_null,
2338         .parent         = &omap_32k_fck,
2339         .clkdm_name     = "wkup_clkdm",
2340         .recalc         = &followparent_recalc,
2341 };
2342
2343 static struct clk gpio1_dbck = {
2344         .name           = "gpio1_dbck",
2345         .ops            = &clkops_omap2_dflt,
2346         .parent         = &wkup_32k_fck,
2347         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2348         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2349         .clkdm_name     = "wkup_clkdm",
2350         .recalc         = &followparent_recalc,
2351 };
2352
2353 static struct clk wdt2_fck = {
2354         .name           = "wdt2_fck",
2355         .ops            = &clkops_omap2_dflt_wait,
2356         .parent         = &wkup_32k_fck,
2357         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2358         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2359         .clkdm_name     = "wkup_clkdm",
2360         .recalc         = &followparent_recalc,
2361 };
2362
2363 static struct clk wkup_l4_ick = {
2364         .name           = "wkup_l4_ick",
2365         .ops            = &clkops_null,
2366         .parent         = &sys_ck,
2367         .clkdm_name     = "wkup_clkdm",
2368         .recalc         = &followparent_recalc,
2369 };
2370
2371 /* 3430ES2 only */
2372 /* Never specifically named in the TRM, so we have to infer a likely name */
2373 static struct clk usim_ick = {
2374         .name           = "usim_ick",
2375         .ops            = &clkops_omap2_iclk_dflt_wait,
2376         .parent         = &wkup_l4_ick,
2377         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2378         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2379         .clkdm_name     = "wkup_clkdm",
2380         .recalc         = &followparent_recalc,
2381 };
2382
2383 static struct clk wdt2_ick = {
2384         .name           = "wdt2_ick",
2385         .ops            = &clkops_omap2_iclk_dflt_wait,
2386         .parent         = &wkup_l4_ick,
2387         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2388         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2389         .clkdm_name     = "wkup_clkdm",
2390         .recalc         = &followparent_recalc,
2391 };
2392
2393 static struct clk wdt1_ick = {
2394         .name           = "wdt1_ick",
2395         .ops            = &clkops_omap2_iclk_dflt_wait,
2396         .parent         = &wkup_l4_ick,
2397         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2398         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2399         .clkdm_name     = "wkup_clkdm",
2400         .recalc         = &followparent_recalc,
2401 };
2402
2403 static struct clk gpio1_ick = {
2404         .name           = "gpio1_ick",
2405         .ops            = &clkops_omap2_iclk_dflt_wait,
2406         .parent         = &wkup_l4_ick,
2407         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2408         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2409         .clkdm_name     = "wkup_clkdm",
2410         .recalc         = &followparent_recalc,
2411 };
2412
2413 static struct clk omap_32ksync_ick = {
2414         .name           = "omap_32ksync_ick",
2415         .ops            = &clkops_omap2_iclk_dflt_wait,
2416         .parent         = &wkup_l4_ick,
2417         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2418         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2419         .clkdm_name     = "wkup_clkdm",
2420         .recalc         = &followparent_recalc,
2421 };
2422
2423 /* XXX This clock no longer exists in 3430 TRM rev F */
2424 static struct clk gpt12_ick = {
2425         .name           = "gpt12_ick",
2426         .ops            = &clkops_omap2_iclk_dflt_wait,
2427         .parent         = &wkup_l4_ick,
2428         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2429         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2430         .clkdm_name     = "wkup_clkdm",
2431         .recalc         = &followparent_recalc,
2432 };
2433
2434 static struct clk gpt1_ick = {
2435         .name           = "gpt1_ick",
2436         .ops            = &clkops_omap2_iclk_dflt_wait,
2437         .parent         = &wkup_l4_ick,
2438         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2439         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2440         .clkdm_name     = "wkup_clkdm",
2441         .recalc         = &followparent_recalc,
2442 };
2443
2444
2445
2446 /* PER clock domain */
2447
2448 static struct clk per_96m_fck = {
2449         .name           = "per_96m_fck",
2450         .ops            = &clkops_null,
2451         .parent         = &omap_96m_alwon_fck,
2452         .clkdm_name     = "per_clkdm",
2453         .recalc         = &followparent_recalc,
2454 };
2455
2456 static struct clk per_48m_fck = {
2457         .name           = "per_48m_fck",
2458         .ops            = &clkops_null,
2459         .parent         = &omap_48m_fck,
2460         .clkdm_name     = "per_clkdm",
2461         .recalc         = &followparent_recalc,
2462 };
2463
2464 static struct clk uart3_fck = {
2465         .name           = "uart3_fck",
2466         .ops            = &clkops_omap2_dflt_wait,
2467         .parent         = &per_48m_fck,
2468         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2469         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2470         .clkdm_name     = "per_clkdm",
2471         .recalc         = &followparent_recalc,
2472 };
2473
2474 static struct clk uart4_fck = {
2475         .name           = "uart4_fck",
2476         .ops            = &clkops_omap2_dflt_wait,
2477         .parent         = &per_48m_fck,
2478         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2479         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2480         .clkdm_name     = "per_clkdm",
2481         .recalc         = &followparent_recalc,
2482 };
2483
2484 static struct clk uart4_fck_am35xx = {
2485         .name           = "uart4_fck",
2486         .ops            = &clkops_omap2_dflt_wait,
2487         .parent         = &per_48m_fck,
2488         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
2489         .enable_bit     = OMAP3430_EN_UART4_SHIFT,
2490         .clkdm_name     = "core_l4_clkdm",
2491         .recalc         = &followparent_recalc,
2492 };
2493
2494 static struct clk gpt2_fck = {
2495         .name           = "gpt2_fck",
2496         .ops            = &clkops_omap2_dflt_wait,
2497         .init           = &omap2_init_clksel_parent,
2498         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2499         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2500         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2501         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2502         .clksel         = omap343x_gpt_clksel,
2503         .clkdm_name     = "per_clkdm",
2504         .recalc         = &omap2_clksel_recalc,
2505 };
2506
2507 static struct clk gpt3_fck = {
2508         .name           = "gpt3_fck",
2509         .ops            = &clkops_omap2_dflt_wait,
2510         .init           = &omap2_init_clksel_parent,
2511         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2512         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2513         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2514         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2515         .clksel         = omap343x_gpt_clksel,
2516         .clkdm_name     = "per_clkdm",
2517         .recalc         = &omap2_clksel_recalc,
2518 };
2519
2520 static struct clk gpt4_fck = {
2521         .name           = "gpt4_fck",
2522         .ops            = &clkops_omap2_dflt_wait,
2523         .init           = &omap2_init_clksel_parent,
2524         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2525         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2526         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2527         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2528         .clksel         = omap343x_gpt_clksel,
2529         .clkdm_name     = "per_clkdm",
2530         .recalc         = &omap2_clksel_recalc,
2531 };
2532
2533 static struct clk gpt5_fck = {
2534         .name           = "gpt5_fck",
2535         .ops            = &clkops_omap2_dflt_wait,
2536         .init           = &omap2_init_clksel_parent,
2537         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2538         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2539         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2540         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2541         .clksel         = omap343x_gpt_clksel,
2542         .clkdm_name     = "per_clkdm",
2543         .recalc         = &omap2_clksel_recalc,
2544 };
2545
2546 static struct clk gpt6_fck = {
2547         .name           = "gpt6_fck",
2548         .ops            = &clkops_omap2_dflt_wait,
2549         .init           = &omap2_init_clksel_parent,
2550         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2551         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2552         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2553         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2554         .clksel         = omap343x_gpt_clksel,
2555         .clkdm_name     = "per_clkdm",
2556         .recalc         = &omap2_clksel_recalc,
2557 };
2558
2559 static struct clk gpt7_fck = {
2560         .name           = "gpt7_fck",
2561         .ops            = &clkops_omap2_dflt_wait,
2562         .init           = &omap2_init_clksel_parent,
2563         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2564         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2565         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2566         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2567         .clksel         = omap343x_gpt_clksel,
2568         .clkdm_name     = "per_clkdm",
2569         .recalc         = &omap2_clksel_recalc,
2570 };
2571
2572 static struct clk gpt8_fck = {
2573         .name           = "gpt8_fck",
2574         .ops            = &clkops_omap2_dflt_wait,
2575         .init           = &omap2_init_clksel_parent,
2576         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2577         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2578         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2579         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2580         .clksel         = omap343x_gpt_clksel,
2581         .clkdm_name     = "per_clkdm",
2582         .recalc         = &omap2_clksel_recalc,
2583 };
2584
2585 static struct clk gpt9_fck = {
2586         .name           = "gpt9_fck",
2587         .ops            = &clkops_omap2_dflt_wait,
2588         .init           = &omap2_init_clksel_parent,
2589         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2590         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2591         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2592         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2593         .clksel         = omap343x_gpt_clksel,
2594         .clkdm_name     = "per_clkdm",
2595         .recalc         = &omap2_clksel_recalc,
2596 };
2597
2598 static struct clk per_32k_alwon_fck = {
2599         .name           = "per_32k_alwon_fck",
2600         .ops            = &clkops_null,
2601         .parent         = &omap_32k_fck,
2602         .clkdm_name     = "per_clkdm",
2603         .recalc         = &followparent_recalc,
2604 };
2605
2606 static struct clk gpio6_dbck = {
2607         .name           = "gpio6_dbck",
2608         .ops            = &clkops_omap2_dflt,
2609         .parent         = &per_32k_alwon_fck,
2610         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2611         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2612         .clkdm_name     = "per_clkdm",
2613         .recalc         = &followparent_recalc,
2614 };
2615
2616 static struct clk gpio5_dbck = {
2617         .name           = "gpio5_dbck",
2618         .ops            = &clkops_omap2_dflt,
2619         .parent         = &per_32k_alwon_fck,
2620         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2621         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2622         .clkdm_name     = "per_clkdm",
2623         .recalc         = &followparent_recalc,
2624 };
2625
2626 static struct clk gpio4_dbck = {
2627         .name           = "gpio4_dbck",
2628         .ops            = &clkops_omap2_dflt,
2629         .parent         = &per_32k_alwon_fck,
2630         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2631         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2632         .clkdm_name     = "per_clkdm",
2633         .recalc         = &followparent_recalc,
2634 };
2635
2636 static struct clk gpio3_dbck = {
2637         .name           = "gpio3_dbck",
2638         .ops            = &clkops_omap2_dflt,
2639         .parent         = &per_32k_alwon_fck,
2640         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2641         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2642         .clkdm_name     = "per_clkdm",
2643         .recalc         = &followparent_recalc,
2644 };
2645
2646 static struct clk gpio2_dbck = {
2647         .name           = "gpio2_dbck",
2648         .ops            = &clkops_omap2_dflt,
2649         .parent         = &per_32k_alwon_fck,
2650         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2651         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2652         .clkdm_name     = "per_clkdm",
2653         .recalc         = &followparent_recalc,
2654 };
2655
2656 static struct clk wdt3_fck = {
2657         .name           = "wdt3_fck",
2658         .ops            = &clkops_omap2_dflt_wait,
2659         .parent         = &per_32k_alwon_fck,
2660         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2661         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2662         .clkdm_name     = "per_clkdm",
2663         .recalc         = &followparent_recalc,
2664 };
2665
2666 static struct clk per_l4_ick = {
2667         .name           = "per_l4_ick",
2668         .ops            = &clkops_null,
2669         .parent         = &l4_ick,
2670         .clkdm_name     = "per_clkdm",
2671         .recalc         = &followparent_recalc,
2672 };
2673
2674 static struct clk gpio6_ick = {
2675         .name           = "gpio6_ick",
2676         .ops            = &clkops_omap2_iclk_dflt_wait,
2677         .parent         = &per_l4_ick,
2678         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2679         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2680         .clkdm_name     = "per_clkdm",
2681         .recalc         = &followparent_recalc,
2682 };
2683
2684 static struct clk gpio5_ick = {
2685         .name           = "gpio5_ick",
2686         .ops            = &clkops_omap2_iclk_dflt_wait,
2687         .parent         = &per_l4_ick,
2688         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2689         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2690         .clkdm_name     = "per_clkdm",
2691         .recalc         = &followparent_recalc,
2692 };
2693
2694 static struct clk gpio4_ick = {
2695         .name           = "gpio4_ick",
2696         .ops            = &clkops_omap2_iclk_dflt_wait,
2697         .parent         = &per_l4_ick,
2698         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2699         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2700         .clkdm_name     = "per_clkdm",
2701         .recalc         = &followparent_recalc,
2702 };
2703
2704 static struct clk gpio3_ick = {
2705         .name           = "gpio3_ick",
2706         .ops            = &clkops_omap2_iclk_dflt_wait,
2707         .parent         = &per_l4_ick,
2708         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2709         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2710         .clkdm_name     = "per_clkdm",
2711         .recalc         = &followparent_recalc,
2712 };
2713
2714 static struct clk gpio2_ick = {
2715         .name           = "gpio2_ick",
2716         .ops            = &clkops_omap2_iclk_dflt_wait,
2717         .parent         = &per_l4_ick,
2718         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2719         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2720         .clkdm_name     = "per_clkdm",
2721         .recalc         = &followparent_recalc,
2722 };
2723
2724 static struct clk wdt3_ick = {
2725         .name           = "wdt3_ick",
2726         .ops            = &clkops_omap2_iclk_dflt_wait,
2727         .parent         = &per_l4_ick,
2728         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2729         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2730         .clkdm_name     = "per_clkdm",
2731         .recalc         = &followparent_recalc,
2732 };
2733
2734 static struct clk uart3_ick = {
2735         .name           = "uart3_ick",
2736         .ops            = &clkops_omap2_iclk_dflt_wait,
2737         .parent         = &per_l4_ick,
2738         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2739         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2740         .clkdm_name     = "per_clkdm",
2741         .recalc         = &followparent_recalc,
2742 };
2743
2744 static struct clk uart4_ick = {
2745         .name           = "uart4_ick",
2746         .ops            = &clkops_omap2_iclk_dflt_wait,
2747         .parent         = &per_l4_ick,
2748         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2749         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
2750         .clkdm_name     = "per_clkdm",
2751         .recalc         = &followparent_recalc,
2752 };
2753
2754 static struct clk gpt9_ick = {
2755         .name           = "gpt9_ick",
2756         .ops            = &clkops_omap2_iclk_dflt_wait,
2757         .parent         = &per_l4_ick,
2758         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2759         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2760         .clkdm_name     = "per_clkdm",
2761         .recalc         = &followparent_recalc,
2762 };
2763
2764 static struct clk gpt8_ick = {
2765         .name           = "gpt8_ick",
2766         .ops            = &clkops_omap2_iclk_dflt_wait,
2767         .parent         = &per_l4_ick,
2768         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2769         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2770         .clkdm_name     = "per_clkdm",
2771         .recalc         = &followparent_recalc,
2772 };
2773
2774 static struct clk gpt7_ick = {
2775         .name           = "gpt7_ick",
2776         .ops            = &clkops_omap2_iclk_dflt_wait,
2777         .parent         = &per_l4_ick,
2778         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2779         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2780         .clkdm_name     = "per_clkdm",
2781         .recalc         = &followparent_recalc,
2782 };
2783
2784 static struct clk gpt6_ick = {
2785         .name           = "gpt6_ick",
2786         .ops            = &clkops_omap2_iclk_dflt_wait,
2787         .parent         = &per_l4_ick,
2788         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2789         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2790         .clkdm_name     = "per_clkdm",
2791         .recalc         = &followparent_recalc,
2792 };
2793
2794 static struct clk gpt5_ick = {
2795         .name           = "gpt5_ick",
2796         .ops            = &clkops_omap2_iclk_dflt_wait,
2797         .parent         = &per_l4_ick,
2798         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2799         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2800         .clkdm_name     = "per_clkdm",
2801         .recalc         = &followparent_recalc,
2802 };
2803
2804 static struct clk gpt4_ick = {
2805         .name           = "gpt4_ick",
2806         .ops            = &clkops_omap2_iclk_dflt_wait,
2807         .parent         = &per_l4_ick,
2808         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2809         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2810         .clkdm_name     = "per_clkdm",
2811         .recalc         = &followparent_recalc,
2812 };
2813
2814 static struct clk gpt3_ick = {
2815         .name           = "gpt3_ick",
2816         .ops            = &clkops_omap2_iclk_dflt_wait,
2817         .parent         = &per_l4_ick,
2818         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2819         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2820         .clkdm_name     = "per_clkdm",
2821         .recalc         = &followparent_recalc,
2822 };
2823
2824 static struct clk gpt2_ick = {
2825         .name           = "gpt2_ick",
2826         .ops            = &clkops_omap2_iclk_dflt_wait,
2827         .parent         = &per_l4_ick,
2828         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2829         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2830         .clkdm_name     = "per_clkdm",
2831         .recalc         = &followparent_recalc,
2832 };
2833
2834 static struct clk mcbsp2_ick = {
2835         .name           = "mcbsp2_ick",
2836         .ops            = &clkops_omap2_iclk_dflt_wait,
2837         .parent         = &per_l4_ick,
2838         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2839         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2840         .clkdm_name     = "per_clkdm",
2841         .recalc         = &followparent_recalc,
2842 };
2843
2844 static struct clk mcbsp3_ick = {
2845         .name           = "mcbsp3_ick",
2846         .ops            = &clkops_omap2_iclk_dflt_wait,
2847         .parent         = &per_l4_ick,
2848         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2849         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2850         .clkdm_name     = "per_clkdm",
2851         .recalc         = &followparent_recalc,
2852 };
2853
2854 static struct clk mcbsp4_ick = {
2855         .name           = "mcbsp4_ick",
2856         .ops            = &clkops_omap2_iclk_dflt_wait,
2857         .parent         = &per_l4_ick,
2858         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2859         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2860         .clkdm_name     = "per_clkdm",
2861         .recalc         = &followparent_recalc,
2862 };
2863
2864 static const struct clksel mcbsp_234_clksel[] = {
2865         { .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
2866         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2867         { .parent = NULL }
2868 };
2869
2870 static struct clk mcbsp2_fck = {
2871         .name           = "mcbsp2_fck",
2872         .ops            = &clkops_omap2_dflt_wait,
2873         .init           = &omap2_init_clksel_parent,
2874         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2875         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2876         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2877         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2878         .clksel         = mcbsp_234_clksel,
2879         .clkdm_name     = "per_clkdm",
2880         .recalc         = &omap2_clksel_recalc,
2881 };
2882
2883 static struct clk mcbsp3_fck = {
2884         .name           = "mcbsp3_fck",
2885         .ops            = &clkops_omap2_dflt_wait,
2886         .init           = &omap2_init_clksel_parent,
2887         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2888         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2889         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2890         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2891         .clksel         = mcbsp_234_clksel,
2892         .clkdm_name     = "per_clkdm",
2893         .recalc         = &omap2_clksel_recalc,
2894 };
2895
2896 static struct clk mcbsp4_fck = {
2897         .name           = "mcbsp4_fck",
2898         .ops            = &clkops_omap2_dflt_wait,
2899         .init           = &omap2_init_clksel_parent,
2900         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2901         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2902         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2903         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2904         .clksel         = mcbsp_234_clksel,
2905         .clkdm_name     = "per_clkdm",
2906         .recalc         = &omap2_clksel_recalc,
2907 };
2908
2909 /* EMU clocks */
2910
2911 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2912
2913 static const struct clksel_rate emu_src_sys_rates[] = {
2914         { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
2915         { .div = 0 },
2916 };
2917
2918 static const struct clksel_rate emu_src_core_rates[] = {
2919         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2920         { .div = 0 },
2921 };
2922
2923 static const struct clksel_rate emu_src_per_rates[] = {
2924         { .div = 1, .val = 2, .flags = RATE_IN_3XXX },
2925         { .div = 0 },
2926 };
2927
2928 static const struct clksel_rate emu_src_mpu_rates[] = {
2929         { .div = 1, .val = 3, .flags = RATE_IN_3XXX },
2930         { .div = 0 },
2931 };
2932
2933 static const struct clksel emu_src_clksel[] = {
2934         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2935         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2936         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2937         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2938         { .parent = NULL },
2939 };
2940
2941 /*
2942  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2943  * to switch the source of some of the EMU clocks.
2944  * XXX Are there CLKEN bits for these EMU clks?
2945  */
2946 static struct clk emu_src_ck = {
2947         .name           = "emu_src_ck",
2948         .ops            = &clkops_null,
2949         .init           = &omap2_init_clksel_parent,
2950         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2951         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2952         .clksel         = emu_src_clksel,
2953         .clkdm_name     = "emu_clkdm",
2954         .recalc         = &omap2_clksel_recalc,
2955 };
2956
2957 static const struct clksel_rate pclk_emu_rates[] = {
2958         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2959         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2960         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
2961         { .div = 6, .val = 6, .flags = RATE_IN_3XXX },
2962         { .div = 0 },
2963 };
2964
2965 static const struct clksel pclk_emu_clksel[] = {
2966         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2967         { .parent = NULL },
2968 };
2969
2970 static struct clk pclk_fck = {
2971         .name           = "pclk_fck",
2972         .ops            = &clkops_null,
2973         .init           = &omap2_init_clksel_parent,
2974         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2975         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2976         .clksel         = pclk_emu_clksel,
2977         .clkdm_name     = "emu_clkdm",
2978         .recalc         = &omap2_clksel_recalc,
2979 };
2980
2981 static const struct clksel_rate pclkx2_emu_rates[] = {
2982         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
2983         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
2984         { .div = 3, .val = 3, .flags = RATE_IN_3XXX },
2985         { .div = 0 },
2986 };
2987
2988 static const struct clksel pclkx2_emu_clksel[] = {
2989         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2990         { .parent = NULL },
2991 };
2992
2993 static struct clk pclkx2_fck = {
2994         .name           = "pclkx2_fck",
2995         .ops            = &clkops_null,
2996         .init           = &omap2_init_clksel_parent,
2997         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2998         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2999         .clksel         = pclkx2_emu_clksel,
3000         .clkdm_name     = "emu_clkdm",
3001         .recalc         = &omap2_clksel_recalc,
3002 };
3003
3004 static const struct clksel atclk_emu_clksel[] = {
3005         { .parent = &emu_src_ck, .rates = div2_rates },
3006         { .parent = NULL },
3007 };
3008
3009 static struct clk atclk_fck = {
3010         .name           = "atclk_fck",
3011         .ops            = &clkops_null,
3012         .init           = &omap2_init_clksel_parent,
3013         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3014         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3015         .clksel         = atclk_emu_clksel,
3016         .clkdm_name     = "emu_clkdm",
3017         .recalc         = &omap2_clksel_recalc,
3018 };
3019
3020 static struct clk traceclk_src_fck = {
3021         .name           = "traceclk_src_fck",
3022         .ops            = &clkops_null,
3023         .init           = &omap2_init_clksel_parent,
3024         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3025         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3026         .clksel         = emu_src_clksel,
3027         .clkdm_name     = "emu_clkdm",
3028         .recalc         = &omap2_clksel_recalc,
3029 };
3030
3031 static const struct clksel_rate traceclk_rates[] = {
3032         { .div = 1, .val = 1, .flags = RATE_IN_3XXX },
3033         { .div = 2, .val = 2, .flags = RATE_IN_3XXX },
3034         { .div = 4, .val = 4, .flags = RATE_IN_3XXX },
3035         { .div = 0 },
3036 };
3037
3038 static const struct clksel traceclk_clksel[] = {
3039         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3040         { .parent = NULL },
3041 };
3042
3043 static struct clk traceclk_fck = {
3044         .name           = "traceclk_fck",
3045         .ops            = &clkops_null,
3046         .init           = &omap2_init_clksel_parent,
3047         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3048         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3049         .clksel         = traceclk_clksel,
3050         .clkdm_name     = "emu_clkdm",
3051         .recalc         = &omap2_clksel_recalc,
3052 };
3053
3054 /* SR clocks */
3055
3056 /* SmartReflex fclk (VDD1) */
3057 static struct clk sr1_fck = {
3058         .name           = "sr1_fck",
3059         .ops            = &clkops_omap2_dflt_wait,
3060         .parent         = &sys_ck,
3061         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3062         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3063         .clkdm_name     = "wkup_clkdm",
3064         .recalc         = &followparent_recalc,
3065 };
3066
3067 /* SmartReflex fclk (VDD2) */
3068 static struct clk sr2_fck = {
3069         .name           = "sr2_fck",
3070         .ops            = &clkops_omap2_dflt_wait,
3071         .parent         = &sys_ck,
3072         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3073         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3074         .clkdm_name     = "wkup_clkdm",
3075         .recalc         = &followparent_recalc,
3076 };
3077
3078 static struct clk sr_l4_ick = {
3079         .name           = "sr_l4_ick",
3080         .ops            = &clkops_null, /* RMK: missing? */
3081         .parent         = &l4_ick,
3082         .clkdm_name     = "core_l4_clkdm",
3083         .recalc         = &followparent_recalc,
3084 };
3085
3086 /* SECURE_32K_FCK clocks */
3087
3088 static struct clk gpt12_fck = {
3089         .name           = "gpt12_fck",
3090         .ops            = &clkops_null,
3091         .parent         = &secure_32k_fck,
3092         .clkdm_name     = "wkup_clkdm",
3093         .recalc         = &followparent_recalc,
3094 };
3095
3096 static struct clk wdt1_fck = {
3097         .name           = "wdt1_fck",
3098         .ops            = &clkops_null,
3099         .parent         = &secure_32k_fck,
3100         .clkdm_name     = "wkup_clkdm",
3101         .recalc         = &followparent_recalc,
3102 };
3103
3104 /* Clocks for AM35XX */
3105 static struct clk ipss_ick = {
3106         .name           = "ipss_ick",
3107         .ops            = &clkops_am35xx_ipss_wait,
3108         .parent         = &core_l3_ick,
3109         .clkdm_name     = "core_l3_clkdm",
3110         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3111         .enable_bit     = AM35XX_EN_IPSS_SHIFT,
3112         .recalc         = &followparent_recalc,
3113 };
3114
3115 static struct clk emac_ick = {
3116         .name           = "emac_ick",
3117         .ops            = &clkops_am35xx_ipss_module_wait,
3118         .parent         = &ipss_ick,
3119         .clkdm_name     = "core_l3_clkdm",
3120         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3121         .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3122         .recalc         = &followparent_recalc,
3123 };
3124
3125 static struct clk rmii_ck = {
3126         .name           = "rmii_ck",
3127         .ops            = &clkops_null,
3128         .rate           = 50000000,
3129 };
3130
3131 static struct clk emac_fck = {
3132         .name           = "emac_fck",
3133         .ops            = &clkops_omap2_dflt,
3134         .parent         = &rmii_ck,
3135         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3136         .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
3137         .recalc         = &followparent_recalc,
3138 };
3139
3140 static struct clk hsotgusb_ick_am35xx = {
3141         .name           = "hsotgusb_ick",
3142         .ops            = &clkops_am35xx_ipss_module_wait,
3143         .parent         = &ipss_ick,
3144         .clkdm_name     = "core_l3_clkdm",
3145         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3146         .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3147         .recalc         = &followparent_recalc,
3148 };
3149
3150 static struct clk hsotgusb_fck_am35xx = {
3151         .name           = "hsotgusb_fck",
3152         .ops            = &clkops_omap2_dflt,
3153         .parent         = &sys_ck,
3154         .clkdm_name     = "core_l3_clkdm",
3155         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3156         .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
3157         .recalc         = &followparent_recalc,
3158 };
3159
3160 static struct clk hecc_ck = {
3161         .name           = "hecc_ck",
3162         .ops            = &clkops_am35xx_ipss_module_wait,
3163         .parent         = &sys_ck,
3164         .clkdm_name     = "core_l3_clkdm",
3165         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3166         .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
3167         .recalc         = &followparent_recalc,
3168 };
3169
3170 static struct clk vpfe_ick = {
3171         .name           = "vpfe_ick",
3172         .ops            = &clkops_am35xx_ipss_module_wait,
3173         .parent         = &ipss_ick,
3174         .clkdm_name     = "core_l3_clkdm",
3175         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3176         .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3177         .recalc         = &followparent_recalc,
3178 };
3179
3180 static struct clk pclk_ck = {
3181         .name           = "pclk_ck",
3182         .ops            = &clkops_null,
3183         .rate           = 27000000,
3184 };
3185
3186 static struct clk vpfe_fck = {
3187         .name           = "vpfe_fck",
3188         .ops            = &clkops_omap2_dflt,
3189         .parent         = &pclk_ck,
3190         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3191         .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
3192         .recalc         = &followparent_recalc,
3193 };
3194
3195 /*
3196  * The UART1/2 functional clock acts as the functional
3197  * clock for UART4. No separate fclk control available.
3198  */
3199 static struct clk uart4_ick_am35xx = {
3200         .name           = "uart4_ick",
3201         .ops            = &clkops_omap2_iclk_dflt_wait,
3202         .parent         = &core_l4_ick,
3203         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3204         .enable_bit     = AM35XX_EN_UART4_SHIFT,
3205         .clkdm_name     = "core_l4_clkdm",
3206         .recalc         = &followparent_recalc,
3207 };
3208
3209 static struct clk dummy_apb_pclk = {
3210         .name           = "apb_pclk",
3211         .ops            = &clkops_null,
3212 };
3213
3214 /*
3215  * clkdev
3216  */
3217
3218 /* XXX At some point we should rename this file to clock3xxx_data.c */
3219 static struct omap_clk omap3xxx_clks[] = {
3220         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
3221         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
3222         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
3223         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
3224         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
3225         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3226         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
3227         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3228         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
3229         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
3230         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
3231         CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3232         CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3233         CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3234         CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3235         CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
3236         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
3237         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
3238         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
3239         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
3240         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3241         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
3242         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
3243         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
3244         CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
3245         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
3246         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
3247         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3248         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
3249         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3250         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3251         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
3252         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
3253         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3254         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3255         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
3256         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
3257         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
3258         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
3259         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
3260         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
3261         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3262         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
3263         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3264         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
3265         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3266         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
3267         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3268         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
3269         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3270         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3271         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3272         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3273         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3274         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
3275         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
3276         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
3277         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
3278         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
3279         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3280         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
3281         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
3282         CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
3283         CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
3284         CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
3285         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
3286         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
3287         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
3288         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
3289         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
3290         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
3291         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_3517 | CK_36XX),
3292         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
3293         CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
3294         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
3295         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
3296         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
3297         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
3298         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3299         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3300         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3301         CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3302         CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
3303         CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
3304         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
3305         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3306         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
3307         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
3308         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
3309         CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
3310         CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
3311         CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
3312         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
3313         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
3314         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
3315         CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
3316         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
3317         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
3318         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
3319         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
3320         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
3321         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3322         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
3323         CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
3324         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
3325         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
3326         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
3327         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
3328         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
3329         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
3330         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
3331         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
3332         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
3333         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
3334         CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
3335         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
3336         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3337         CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3338         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3339         CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
3340         CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
3341         CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
3342         CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
3343         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
3344         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
3345         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
3346         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
3347         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
3348         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
3349         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
3350         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
3351         CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
3352         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
3353         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
3354         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
3355         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
3356         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
3357         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
3358         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
3359         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
3360         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
3361         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
3362         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
3363         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
3364         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
3365         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
3366         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
3367         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
3368         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
3369         CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
3370         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
3371         CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
3372         CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
3373         CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3374         CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
3375         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
3376         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
3377         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
3378         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3379         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
3380         CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
3381         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
3382         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3383         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3384         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3385         CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3386         CLK("usbhs_omap",       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
3387         CLK("usbhs_omap",       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
3388         CLK("usbhs_omap",       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
3389         CLK("usbhs_omap",       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
3390         CLK("usbhs_omap",       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
3391         CLK("usbhs_omap",       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
3392         CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
3393         CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
3394         CLK("usbhs_omap",       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
3395         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
3396         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
3397         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
3398         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
3399         CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
3400         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
3401         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
3402         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
3403         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
3404         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
3405         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3406         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
3407         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
3408         CLK("omap-mcbsp.2",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
3409         CLK("omap-mcbsp.3",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
3410         CLK("omap-mcbsp.4",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
3411         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
3412         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
3413         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
3414         CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
3415         CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_3505 | CK_3517),
3416         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
3417         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
3418         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
3419         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
3420         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
3421         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
3422         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
3423         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
3424         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3425         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
3426         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
3427         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
3428         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
3429         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
3430         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
3431         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
3432         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
3433         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
3434         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
3435         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
3436         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
3437         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
3438         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
3439         CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
3440         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
3441         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
3442         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
3443         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
3444         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
3445         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
3446         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
3447         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
3448         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
3449         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
3450         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
3451         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
3452         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
3453         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
3454         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
3455         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
3456         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
3457         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
3458         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3459         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
3460         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
3461         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
3462         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
3463         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3464         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
3465         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
3466         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
3467         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
3468         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
3469         CLK("davinci_emac",     "emac_clk",     &emac_ick,      CK_AM35XX),
3470         CLK("davinci_emac",     "phy_clk",      &emac_fck,      CK_AM35XX),
3471         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
3472         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
3473         CLK("musb-am35x",       "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
3474         CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
3475         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
3476         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
3477         CLK("omap_timer.1",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3478         CLK("omap_timer.2",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3479         CLK("omap_timer.3",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3480         CLK("omap_timer.4",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3481         CLK("omap_timer.5",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3482         CLK("omap_timer.6",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3483         CLK("omap_timer.7",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3484         CLK("omap_timer.8",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3485         CLK("omap_timer.9",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
3486         CLK("omap_timer.10",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
3487         CLK("omap_timer.11",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
3488         CLK("omap_timer.12",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
3489         CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_3XXX),
3490         CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_3XXX),
3491         CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_3XXX),
3492         CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_3XXX),
3493         CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_3XXX),
3494         CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_3XXX),
3495         CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_3XXX),
3496         CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_3XXX),
3497         CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_3XXX),
3498         CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_3XXX),
3499         CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_3XXX),
3500         CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_3XXX),
3501 };
3502
3503
3504 int __init omap3xxx_clk_init(void)
3505 {
3506         struct omap_clk *c;
3507         u32 cpu_clkflg = 0;
3508
3509         /*
3510          * 3505 must be tested before 3517, since 3517 returns true
3511          * for both AM3517 chips and AM3517 family chips, which
3512          * includes 3505.  Unfortunately there's no obvious family
3513          * test for 3517/3505 :-(
3514          */
3515         if (cpu_is_omap3505()) {
3516                 cpu_mask = RATE_IN_34XX;
3517                 cpu_clkflg = CK_3505;
3518         } else if (cpu_is_omap3517()) {
3519                 cpu_mask = RATE_IN_34XX;
3520                 cpu_clkflg = CK_3517;
3521         } else if (cpu_is_omap3505()) {
3522                 cpu_mask = RATE_IN_34XX;
3523                 cpu_clkflg = CK_3505;
3524         } else if (cpu_is_omap3630()) {
3525                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
3526                 cpu_clkflg = CK_36XX;
3527         } else if (cpu_is_ti816x()) {
3528                 cpu_mask = RATE_IN_TI816X;
3529                 cpu_clkflg = CK_TI816X;
3530         } else if (cpu_is_am33xx()) {
3531                 cpu_mask = RATE_IN_AM33XX;
3532         } else if (cpu_is_ti814x()) {
3533                 cpu_mask = RATE_IN_TI814X;
3534         } else if (cpu_is_omap34xx()) {
3535                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3536                         cpu_mask = RATE_IN_3430ES1;
3537                         cpu_clkflg = CK_3430ES1;
3538                 } else {
3539                         /*
3540                          * Assume that anything that we haven't matched yet
3541                          * has 3430ES2-type clocks.
3542                          */
3543                         cpu_mask = RATE_IN_3430ES2PLUS;
3544                         cpu_clkflg = CK_3430ES2PLUS;
3545                 }
3546         } else {
3547                 WARN(1, "clock: could not identify OMAP3 variant\n");
3548         }
3549
3550         if (omap3_has_192mhz_clk())
3551                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3552
3553         if (cpu_is_omap3630()) {
3554                 /*
3555                  * XXX This type of dynamic rewriting of the clock tree is
3556                  * deprecated and should be revised soon.
3557                  *
3558                  * For 3630: override clkops_omap2_dflt_wait for the
3559                  * clocks affected from PWRDN reset Limitation
3560                  */
3561                 dpll3_m3x2_ck.ops =
3562                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3563                 dpll4_m2x2_ck.ops =
3564                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3565                 dpll4_m3x2_ck.ops =
3566                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3567                 dpll4_m4x2_ck.ops =
3568                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3569                 dpll4_m5x2_ck.ops =
3570                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3571                 dpll4_m6x2_ck.ops =
3572                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3573         }
3574
3575         /*
3576          * XXX This type of dynamic rewriting of the clock tree is
3577          * deprecated and should be revised soon.
3578          */
3579         if (cpu_is_omap3630())
3580                 dpll4_dd = dpll4_dd_3630;
3581         else
3582                 dpll4_dd = dpll4_dd_34xx;
3583
3584         clk_init(&omap2_clk_functions);
3585
3586         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3587              c++)
3588                 clk_preinit(c->lk.clk);
3589
3590         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3591              c++)
3592                 if (c->cpu & cpu_clkflg) {
3593                         clkdev_add(&c->lk);
3594                         clk_register(c->lk.clk);
3595                         omap2_init_clk_clkdm(c->lk.clk);
3596                 }
3597
3598         /* Disable autoidle on all clocks; let the PM code enable it later */
3599         omap_clk_disable_autoidle_all();
3600
3601         recalculate_root_clocks();
3602
3603         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
3604                 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3605                 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3606
3607         /*
3608          * Only enable those clocks we will need, let the drivers
3609          * enable other clocks as necessary
3610          */
3611         clk_enable_init_clocks();
3612
3613         /*
3614          * Lock DPLL5 -- here only until other device init code can
3615          * handle this
3616          */
3617         if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
3618                 omap3_clk_lock_dpll5();
3619
3620         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3621         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3622         arm_fck_p = clk_get(NULL, "arm_fck");
3623
3624         return 0;
3625 }