2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/export.h>
19 #include <linux/list.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/clk-provider.h>
25 #include <linux/bitops.h>
26 #include <linux/regmap.h>
27 #include <linux/of_address.h>
28 #include <linux/bootmem.h>
31 #include <trace/events/power.h>
34 #include "clockdomain.h"
39 #include "cm-regbits-24xx.h"
40 #include "cm-regbits-34xx.h"
44 * MAX_MODULE_ENABLE_WAIT: maximum of number of microseconds to wait
45 * for a module to indicate that it is no longer in idle
47 #define MAX_MODULE_ENABLE_WAIT 100000
51 /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
52 #define OMAP3430_DPLL_FINT_BAND1_MIN 750000
53 #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
54 #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
55 #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
58 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
59 * From device data manual section 4.3 "DPLL and DLL Specifications".
61 #define OMAP3PLUS_DPLL_FINT_MIN 32000
62 #define OMAP3PLUS_DPLL_FINT_MAX 52000000
65 * clkdm_control: if true, then when a clock is enabled in the
66 * hardware, its clockdomain will first be enabled; and when a clock
67 * is disabled in the hardware, its clockdomain will be disabled
70 static bool clkdm_control = true;
73 struct regmap *regmap;
77 static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
79 static void clk_memmap_writel(u32 val, void __iomem *reg)
81 struct clk_omap_reg *r = (struct clk_omap_reg *)®
82 struct clk_iomap *io = clk_memmaps[r->index];
85 regmap_write(io->regmap, r->offset, val);
87 writel_relaxed(val, io->mem + r->offset);
90 static u32 clk_memmap_readl(void __iomem *reg)
93 struct clk_omap_reg *r = (struct clk_omap_reg *)®
94 struct clk_iomap *io = clk_memmaps[r->index];
97 regmap_read(io->regmap, r->offset, &val);
99 val = readl_relaxed(io->mem + r->offset);
104 void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
106 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
107 writel_relaxed(val, reg);
109 clk_memmap_writel(val, reg);
112 u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
114 if (WARN_ON_ONCE(!(clk->flags & MEMMAP_ADDRESSING)))
115 return readl_relaxed(reg);
117 return clk_memmap_readl(reg);
120 static struct ti_clk_ll_ops omap_clk_ll_ops = {
121 .clk_readl = clk_memmap_readl,
122 .clk_writel = clk_memmap_writel,
126 * omap2_clk_provider_init - initialize a clock provider
127 * @match_table: DT device table to match for devices to init
128 * @np: device node pointer for the this clock provider
129 * @index: index for the clock provider
130 + @syscon: syscon regmap pointer
131 * @mem: iomem pointer for the clock provider memory area, only used if
132 * syscon is not provided
134 * Initializes a clock provider module (CM/PRM etc.), registering
135 * the memory mapping at specified index and initializing the
136 * low level driver infrastructure. Returns 0 in success.
138 int __init omap2_clk_provider_init(struct device_node *np, int index,
139 struct regmap *syscon, void __iomem *mem)
141 struct clk_iomap *io;
143 ti_clk_ll_ops = &omap_clk_ll_ops;
145 io = kzalloc(sizeof(*io), GFP_KERNEL);
150 clk_memmaps[index] = io;
152 ti_dt_clk_init_provider(np, index);
158 * omap2_clk_legacy_provider_init - initialize a legacy clock provider
159 * @index: index for the clock provider
160 * @mem: iomem pointer for the clock provider memory area
162 * Initializes a legacy clock provider memory mapping.
164 void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem)
166 struct clk_iomap *io;
168 ti_clk_ll_ops = &omap_clk_ll_ops;
170 io = memblock_virt_alloc(sizeof(*io), 0);
174 clk_memmaps[index] = io;
178 * OMAP2+ specific clock functions
181 /* Private functions */
185 * _wait_idlest_generic - wait for a module to leave the idle state
186 * @clk: module clock to wait for (needed for register offsets)
187 * @reg: virtual address of module IDLEST register
188 * @mask: value to mask against to determine if the module is active
189 * @idlest: idle state indicator (0 or 1) for the clock
190 * @name: name of the clock (for printk)
192 * Wait for a module to leave idle, where its idle-status register is
193 * not inside the CM module. Returns 1 if the module left idle
194 * promptly, or 0 if the module did not leave idle before the timeout
195 * elapsed. XXX Deprecated - should be moved into drivers for the
196 * individual IP block that the IDLEST register exists in.
198 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg,
199 u32 mask, u8 idlest, const char *name)
203 ena = (idlest) ? 0 : mask;
205 omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena),
206 MAX_MODULE_ENABLE_WAIT, i);
208 if (i < MAX_MODULE_ENABLE_WAIT)
209 pr_debug("omap clock: module associated with clock %s ready after %d loops\n",
212 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n",
213 name, MAX_MODULE_ENABLE_WAIT);
215 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
219 * _omap2_module_wait_ready - wait for an OMAP module to leave IDLE
220 * @clk: struct clk * belonging to the module
222 * If the necessary clocks for the OMAP hardware IP block that
223 * corresponds to clock @clk are enabled, then wait for the module to
224 * indicate readiness (i.e., to leave IDLE). This code does not
225 * belong in the clock code and will be moved in the medium term to
226 * module-dependent code. No return value.
228 static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
230 void __iomem *companion_reg, *idlest_reg;
231 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
235 /* Not all modules have multiple clocks that their IDLEST depends on */
236 if (clk->ops->find_companion) {
237 clk->ops->find_companion(clk, &companion_reg, &other_bit);
238 if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit)))
242 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
243 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
245 /* IDLEST register not in the CM module */
246 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
247 idlest_val, __clk_get_name(clk->hw.clk));
249 omap_cm_wait_module_ready(0, prcm_mod, idlest_reg_id,
254 /* Public functions */
257 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
258 * @clk: OMAP clock struct ptr to use
260 * Convert a clockdomain name stored in a struct clk 'clk' into a
261 * clockdomain pointer, and save it into the struct clk. Intended to be
262 * called during clk_register(). No return value.
264 void omap2_init_clk_clkdm(struct clk_hw *hw)
266 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
267 struct clockdomain *clkdm;
268 const char *clk_name;
270 if (!clk->clkdm_name)
273 clk_name = __clk_get_name(hw->clk);
275 clkdm = clkdm_lookup(clk->clkdm_name);
277 pr_debug("clock: associated clk %s to clkdm %s\n",
278 clk_name, clk->clkdm_name);
281 pr_debug("clock: could not associate clk %s to clkdm %s\n",
282 clk_name, clk->clkdm_name);
287 * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
289 * Prevent the OMAP clock code from calling into the clockdomain code
290 * when a hardware clock in that clockdomain is enabled or disabled.
291 * Intended to be called at init time from omap*_clk_init(). No
294 void __init omap2_clk_disable_clkdm_control(void)
296 clkdm_control = false;
300 * omap2_clk_dflt_find_companion - find companion clock to @clk
301 * @clk: struct clk * to find the companion clock of
302 * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
303 * @other_bit: u8 ** to return the companion clock bit shift in
305 * Note: We don't need special code here for INVERT_ENABLE for the
306 * time being since INVERT_ENABLE only applies to clocks enabled by
309 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes it's
310 * just a matter of XORing the bits.
312 * Some clocks don't have companion clocks. For example, modules with
313 * only an interface clock (such as MAILBOXES) don't have a companion
314 * clock. Right now, this code relies on the hardware exporting a bit
315 * in the correct companion register that indicates that the
316 * nonexistent 'companion clock' is active. Future patches will
317 * associate this type of code with per-module data structures to
318 * avoid this issue, and remove the casts. No return value.
320 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
321 void __iomem **other_reg, u8 *other_bit)
326 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
327 * it's just a matter of XORing the bits.
329 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
331 *other_reg = (__force void __iomem *)r;
332 *other_bit = clk->enable_bit;
336 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
337 * @clk: struct clk * to find IDLEST info for
338 * @idlest_reg: void __iomem ** to return the CM_IDLEST va in
339 * @idlest_bit: u8 * to return the CM_IDLEST bit shift in
340 * @idlest_val: u8 * to return the idle status indicator
342 * Return the CM_IDLEST register address and bit shift corresponding
343 * to the module that "owns" this clock. This default code assumes
344 * that the CM_IDLEST bit shift is the CM_*CLKEN bit shift, and that
345 * the IDLEST register address ID corresponds to the CM_*CLKEN
346 * register address ID (e.g., that CM_FCLKEN2 corresponds to
347 * CM_IDLEST2). This is not true for all modules. No return value.
349 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
350 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val)
354 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
355 *idlest_reg = (__force void __iomem *)r;
356 *idlest_bit = clk->enable_bit;
359 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
360 * 34xx reverses this, just to keep us on our toes
361 * AM35xx uses both, depending on the module.
363 *idlest_val = ti_clk_get_features()->cm_idlest_val;
367 * omap2_dflt_clk_enable - enable a clock in the hardware
368 * @hw: struct clk_hw * of the clock to enable
370 * Enable the clock @hw in the hardware. We first call into the OMAP
371 * clockdomain code to "enable" the corresponding clockdomain if this
372 * is the first enabled user of the clockdomain. Then program the
373 * hardware to enable the clock. Then wait for the IP block that uses
374 * this clock to leave idle (if applicable). Returns the error value
375 * from clkdm_clk_enable() if it terminated with an error, or -EINVAL
376 * if @hw has a null clock enable_reg, or zero upon success.
378 int omap2_dflt_clk_enable(struct clk_hw *hw)
380 struct clk_hw_omap *clk;
384 clk = to_clk_hw_omap(hw);
386 if (clkdm_control && clk->clkdm) {
387 ret = clkdm_clk_enable(clk->clkdm, hw->clk);
389 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n",
390 __func__, __clk_get_name(hw->clk),
391 clk->clkdm->name, ret);
396 if (unlikely(clk->enable_reg == NULL)) {
397 pr_err("%s: %s missing enable_reg\n", __func__,
398 __clk_get_name(hw->clk));
403 /* FIXME should not have INVERT_ENABLE bit here */
404 v = omap2_clk_readl(clk, clk->enable_reg);
405 if (clk->flags & INVERT_ENABLE)
406 v &= ~(1 << clk->enable_bit);
408 v |= (1 << clk->enable_bit);
409 omap2_clk_writel(v, clk, clk->enable_reg);
410 v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */
412 if (clk->ops && clk->ops->find_idlest)
413 _omap2_module_wait_ready(clk);
418 if (clkdm_control && clk->clkdm)
419 clkdm_clk_disable(clk->clkdm, hw->clk);
424 * omap2_dflt_clk_disable - disable a clock in the hardware
425 * @hw: struct clk_hw * of the clock to disable
427 * Disable the clock @hw in the hardware, and call into the OMAP
428 * clockdomain code to "disable" the corresponding clockdomain if all
429 * clocks/hwmods in that clockdomain are now disabled. No return
432 void omap2_dflt_clk_disable(struct clk_hw *hw)
434 struct clk_hw_omap *clk;
437 clk = to_clk_hw_omap(hw);
438 if (!clk->enable_reg) {
440 * 'independent' here refers to a clock which is not
441 * controlled by its parent.
443 pr_err("%s: independent clock %s has no enable_reg\n",
444 __func__, __clk_get_name(hw->clk));
448 v = omap2_clk_readl(clk, clk->enable_reg);
449 if (clk->flags & INVERT_ENABLE)
450 v |= (1 << clk->enable_bit);
452 v &= ~(1 << clk->enable_bit);
453 omap2_clk_writel(v, clk, clk->enable_reg);
454 /* No OCP barrier needed here since it is a disable operation */
456 if (clkdm_control && clk->clkdm)
457 clkdm_clk_disable(clk->clkdm, hw->clk);
461 * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
462 * @hw: struct clk_hw * of the clock being enabled
464 * Increment the usecount of the clockdomain of the clock pointed to
465 * by @hw; if the usecount is 1, the clockdomain will be "enabled."
466 * Only needed for clocks that don't use omap2_dflt_clk_enable() as
467 * their enable function pointer. Passes along the return value of
468 * clkdm_clk_enable(), -EINVAL if @hw is not associated with a
469 * clockdomain, or 0 if clock framework-based clockdomain control is
472 int omap2_clkops_enable_clkdm(struct clk_hw *hw)
474 struct clk_hw_omap *clk;
477 clk = to_clk_hw_omap(hw);
479 if (unlikely(!clk->clkdm)) {
480 pr_err("%s: %s: no clkdm set ?!\n", __func__,
481 __clk_get_name(hw->clk));
485 if (unlikely(clk->enable_reg))
486 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__,
487 __clk_get_name(hw->clk));
489 if (!clkdm_control) {
490 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
491 __func__, __clk_get_name(hw->clk));
495 ret = clkdm_clk_enable(clk->clkdm, hw->clk);
496 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n",
497 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret);
503 * omap2_clkops_disable_clkdm - decrement usecount on clkdm of @hw
504 * @hw: struct clk_hw * of the clock being disabled
506 * Decrement the usecount of the clockdomain of the clock pointed to
507 * by @hw; if the usecount is 0, the clockdomain will be "disabled."
508 * Only needed for clocks that don't use omap2_dflt_clk_disable() as their
509 * disable function pointer. No return value.
511 void omap2_clkops_disable_clkdm(struct clk_hw *hw)
513 struct clk_hw_omap *clk;
515 clk = to_clk_hw_omap(hw);
517 if (unlikely(!clk->clkdm)) {
518 pr_err("%s: %s: no clkdm set ?!\n", __func__,
519 __clk_get_name(hw->clk));
523 if (unlikely(clk->enable_reg))
524 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__,
525 __clk_get_name(hw->clk));
527 if (!clkdm_control) {
528 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
529 __func__, __clk_get_name(hw->clk));
533 clkdm_clk_disable(clk->clkdm, hw->clk);
537 * omap2_dflt_clk_is_enabled - is clock enabled in the hardware?
538 * @hw: struct clk_hw * to check
540 * Return 1 if the clock represented by @hw is enabled in the
541 * hardware, or 0 otherwise. Intended for use in the struct
542 * clk_ops.is_enabled function pointer.
544 int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
546 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
549 v = omap2_clk_readl(clk, clk->enable_reg);
551 if (clk->flags & INVERT_ENABLE)
552 v ^= BIT(clk->enable_bit);
554 v &= BIT(clk->enable_bit);
559 static int __initdata mpurate;
562 * By default we use the rate set by the bootloader.
563 * You can override this with mpurate= cmdline option.
565 static int __init omap_clk_setup(char *str)
567 get_option(&str, &mpurate);
577 __setup("mpurate=", omap_clk_setup);
579 const struct clk_hw_omap_ops clkhwops_wait = {
580 .find_idlest = omap2_clk_dflt_find_idlest,
581 .find_companion = omap2_clk_dflt_find_companion,
585 * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
586 * @mpurate_ck_name: clk name of the clock to change rate
588 * Change the ARM MPU clock rate to the rate specified on the command
589 * line, if one was specified. @mpurate_ck_name should be
590 * "virt_prcm_set" on OMAP2xxx and "dpll1_ck" on OMAP34xx/OMAP36xx.
591 * XXX Does not handle voltage scaling - on OMAP2xxx this is currently
592 * handled by the virt_prcm_set clock, but this should be handled by
593 * the OPP layer. XXX This is intended to be handled by the OPP layer
594 * code in the near future and should be removed from the clock code.
595 * Returns -EINVAL if 'mpurate' is zero or if clk_set_rate() rejects
596 * the rate, -ENOENT if the struct clk referred to by @mpurate_ck_name
597 * cannot be found, or 0 upon success.
599 int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
601 struct clk *mpurate_ck;
607 mpurate_ck = clk_get(NULL, mpurate_ck_name);
608 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
611 r = clk_set_rate(mpurate_ck, mpurate);
613 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
614 mpurate_ck_name, mpurate, r);
626 * omap2_clk_print_new_rates - print summary of current clock tree rates
627 * @hfclkin_ck_name: clk name for the off-chip HF oscillator
628 * @core_ck_name: clk name for the on-chip CORE_CLK
629 * @mpu_ck_name: clk name for the ARM MPU clock
631 * Prints a short message to the console with the HFCLKIN oscillator
632 * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
633 * Called by the boot-time MPU rate switching code. XXX This is intended
634 * to be handled by the OPP layer code in the near future and should be
635 * removed from the clock code. No return value.
637 void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
638 const char *core_ck_name,
639 const char *mpu_ck_name)
641 struct clk *hfclkin_ck, *core_ck, *mpu_ck;
642 unsigned long hfclkin_rate;
644 mpu_ck = clk_get(NULL, mpu_ck_name);
645 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
648 core_ck = clk_get(NULL, core_ck_name);
649 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
652 hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
653 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
656 hfclkin_rate = clk_get_rate(hfclkin_ck);
658 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
659 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
660 (clk_get_rate(core_ck) / 1000000),
661 (clk_get_rate(mpu_ck) / 1000000));
665 * ti_clk_init_features - init clock features struct for the SoC
667 * Initializes the clock features struct based on the SoC type.
669 void __init ti_clk_init_features(void)
671 struct ti_clk_features features = { 0 };
672 /* Fint setup for DPLLs */
673 if (cpu_is_omap3430()) {
674 features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
675 features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
676 features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
677 features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
679 features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
680 features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
683 /* Bypass value setup for DPLLs */
684 if (cpu_is_omap24xx()) {
685 features.dpll_bypass_vals |=
686 (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
687 (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
688 } else if (cpu_is_omap34xx()) {
689 features.dpll_bypass_vals |=
690 (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
691 (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
692 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
693 soc_is_omap54xx() || soc_is_dra7xx()) {
694 features.dpll_bypass_vals |=
695 (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
696 (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
697 (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
700 /* Jitter correction only available on OMAP343X */
701 if (cpu_is_omap343x())
702 features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
704 /* Idlest value for interface clocks.
705 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
706 * 34xx reverses this, just to keep us on our toes
707 * AM35xx uses both, depending on the module.
709 if (cpu_is_omap24xx())
710 features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
711 else if (cpu_is_omap34xx())
712 features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
714 /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
715 if (omap_rev() == OMAP3430_REV_ES1_0)
716 features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
718 ti_clk_setup_features(&features);