arch/arm/mach-omap2/cclock44xx_data.c

   1 /*
   2  * OMAP4 Clock data
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  * Mike Turquette (mturquette@ti.com)
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  *
  16  * XXX Some of the ES1 clocks have been removed/changed; once support
  17  * is added for discriminating clocks by ES level, these should be added back
  18  * in.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/list.h>
  23 #include <linux/clk-private.h>
  24 #include <linux/clkdev.h>
  25 #include <linux/io.h>
  26
  27 #include "soc.h"
  28 #include "iomap.h"
  29 #include "clock.h"
  30 #include "clock44xx.h"
  31 #include "cm1_44xx.h"
  32 #include "cm2_44xx.h"
  33 #include "cm-regbits-44xx.h"
  34 #include "prm44xx.h"
  35 #include "prm-regbits-44xx.h"
  36 #include "control.h"
  37 #include "scrm44xx.h"
  38
  39 /* OMAP4 modulemode control */
  40 #define OMAP4430_MODULEMODE_HWCTRL_SHIFT                0
  41 #define OMAP4430_MODULEMODE_SWCTRL_SHIFT                1
  42
  43 /* Root clocks */
  44
  45 DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
  46
  47 DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
  48
  49 DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
  50                 OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
  51                 0x0, NULL);
  52
  53 DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
  54
  55 DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
  56
  57 DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
  58
  59 DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
  60                 OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
  61                 0x0, NULL);
  62
  63 DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
  64
  65 DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
  66
  67 DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
  68
  69 DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
  70
  71 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
  72
  73 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
  74
  75 DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
  76
  77 DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
  78
  79 static const char *sys_clkin_ck_parents[] = {
  80         "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
  81         "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
  82         "virt_38400000_ck",
  83 };
  84
  85 DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
  86                OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
  87                OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
  88
  89 DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
  90
  91 DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
  92
  93 DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
  94
  95 DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
  96
  97 DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
  98
  99 /* Module clocks and DPLL outputs */
 100
 101 static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
 102         "sys_clkin_ck", "sys_32k_ck",
 103 };
 104
 105 DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
 106                NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
 107                OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
 108
 109 DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
 110                0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
 111                OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
 112
 113 /* DPLL_ABE */
 114 static struct dpll_data dpll_abe_dd = {
 115         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
 116         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
 117         .clk_ref        = &abe_dpll_refclk_mux_ck,
 118         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
 119         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 120         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
 121         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
 122         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 123         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 124         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 125         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 126         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 127         .m4xen_mask     = OMAP4430_DPLL_REGM4XEN_MASK,
 128         .lpmode_mask    = OMAP4430_DPLL_LPMODE_EN_MASK,
 129         .max_multiplier = 2047,
 130         .max_divider    = 128,
 131         .min_divider    = 1,
 132 };
 133
 134
 135 static const char *dpll_abe_ck_parents[] = {
 136         "abe_dpll_refclk_mux_ck",
 137 };
 138
 139 static struct clk dpll_abe_ck;
 140
 141 static const struct clk_ops dpll_abe_ck_ops = {
 142         .enable         = &omap3_noncore_dpll_enable,
 143         .disable        = &omap3_noncore_dpll_disable,
 144         .recalc_rate    = &omap4_dpll_regm4xen_recalc,
 145         .round_rate     = &omap4_dpll_regm4xen_round_rate,
 146         .set_rate       = &omap3_noncore_dpll_set_rate,
 147         .get_parent     = &omap2_init_dpll_parent,
 148 };
 149
 150 static struct clk_hw_omap dpll_abe_ck_hw = {
 151         .hw = {
 152                 .clk = &dpll_abe_ck,
 153         },
 154         .dpll_data      = &dpll_abe_dd,
 155         .ops            = &clkhwops_omap3_dpll,
 156 };
 157
 158 DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
 159
 160 static const char *dpll_abe_x2_ck_parents[] = {
 161         "dpll_abe_ck",
 162 };
 163
 164 static struct clk dpll_abe_x2_ck;
 165
 166 static const struct clk_ops dpll_abe_x2_ck_ops = {
 167         .recalc_rate    = &omap3_clkoutx2_recalc,
 168 };
 169
 170 static struct clk_hw_omap dpll_abe_x2_ck_hw = {
 171         .hw = {
 172                 .clk = &dpll_abe_x2_ck,
 173         },
 174         .flags          = CLOCK_CLKOUTX2,
 175         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 176         .ops            = &clkhwops_omap4_dpllmx,
 177 };
 178
 179 DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
 180
 181 static const struct clk_ops omap_hsdivider_ops = {
 182         .set_rate       = &omap2_clksel_set_rate,
 183         .recalc_rate    = &omap2_clksel_recalc,
 184         .round_rate     = &omap2_clksel_round_rate,
 185 };
 186
 187 DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
 188                           0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
 189                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
 190
 191 DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
 192                         0x0, 1, 8);
 193
 194 DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
 195                    OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
 196                    OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
 197
 198 DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
 199                    OMAP4430_CM1_ABE_AESS_CLKCTRL,
 200                    OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
 201                    OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
 202                    0x0, NULL);
 203
 204 DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
 205                           0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
 206                           OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
 207
 208 static const char *core_hsd_byp_clk_mux_ck_parents[] = {
 209         "sys_clkin_ck", "dpll_abe_m3x2_ck",
 210 };
 211
 212 DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
 213                0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
 214                OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
 215                0x0, NULL);
 216
 217 /* DPLL_CORE */
 218 static struct dpll_data dpll_core_dd = {
 219         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
 220         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
 221         .clk_ref        = &sys_clkin_ck,
 222         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
 223         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 224         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
 225         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
 226         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 227         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 228         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 229         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 230         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 231         .max_multiplier = 2047,
 232         .max_divider    = 128,
 233         .min_divider    = 1,
 234 };
 235
 236
 237 static const char *dpll_core_ck_parents[] = {
 238         "sys_clkin_ck",
 239 };
 240
 241 static struct clk dpll_core_ck;
 242
 243 static const struct clk_ops dpll_core_ck_ops = {
 244         .recalc_rate    = &omap3_dpll_recalc,
 245         .get_parent     = &omap2_init_dpll_parent,
 246 };
 247
 248 static struct clk_hw_omap dpll_core_ck_hw = {
 249         .hw = {
 250                 .clk = &dpll_core_ck,
 251         },
 252         .dpll_data      = &dpll_core_dd,
 253         .ops            = &clkhwops_omap3_dpll,
 254 };
 255
 256 DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
 257
 258 static const char *dpll_core_x2_ck_parents[] = {
 259         "dpll_core_ck",
 260 };
 261
 262 static struct clk dpll_core_x2_ck;
 263
 264 static struct clk_hw_omap dpll_core_x2_ck_hw = {
 265         .hw = {
 266                 .clk = &dpll_core_x2_ck,
 267         },
 268 };
 269
 270 DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
 271
 272 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
 273                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
 274                           OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
 275
 276 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
 277                           OMAP4430_CM_DIV_M2_DPLL_CORE,
 278                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
 279
 280 DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
 281                         2);
 282
 283 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
 284                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
 285                           OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
 286
 287 DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
 288                    OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
 289                    OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
 290
 291 DEFINE_CLK_OMAP_HSDIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck",
 292                           &dpll_core_m5x2_ck, 0x0, OMAP4430_CM_BYPCLK_DPLL_IVA,
 293                           OMAP4430_CLKSEL_0_1_MASK);
 294
 295 DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
 296                    0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
 297                    OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
 298
 299 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
 300                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
 301                           OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
 302
 303 DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
 304                         0x0, 1, 2);
 305
 306 DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
 307                    OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
 308                    OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
 309
 310 static const struct clk_ops dmic_fck_ops = {
 311         .enable         = &omap2_dflt_clk_enable,
 312         .disable        = &omap2_dflt_clk_disable,
 313         .is_enabled     = &omap2_dflt_clk_is_enabled,
 314         .recalc_rate    = &omap2_clksel_recalc,
 315         .get_parent     = &omap2_clksel_find_parent_index,
 316         .set_parent     = &omap2_clksel_set_parent,
 317         .init           = &omap2_init_clk_clkdm,
 318 };
 319
 320 static const char *dpll_core_m3x2_ck_parents[] = {
 321         "dpll_core_x2_ck",
 322 };
 323
 324 static const struct clksel dpll_core_m3x2_div[] = {
 325         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
 326         { .parent = NULL },
 327 };
 328
 329 /* XXX Missing round_rate, set_rate in ops */
 330 DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
 331                          OMAP4430_CM_DIV_M3_DPLL_CORE,
 332                          OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 333                          OMAP4430_CM_DIV_M3_DPLL_CORE,
 334                          OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
 335                          dpll_core_m3x2_ck_parents, dmic_fck_ops);
 336
 337 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
 338                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
 339                           OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
 340
 341 static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
 342         "sys_clkin_ck", "div_iva_hs_clk",
 343 };
 344
 345 DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
 346                0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
 347                OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
 348
 349 /* DPLL_IVA */
 350 static struct dpll_data dpll_iva_dd = {
 351         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
 352         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
 353         .clk_ref        = &sys_clkin_ck,
 354         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
 355         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 356         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
 357         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
 358         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 359         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 360         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 361         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 362         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 363         .max_multiplier = 2047,
 364         .max_divider    = 128,
 365         .min_divider    = 1,
 366 };
 367
 368 static struct clk dpll_iva_ck;
 369
 370 static const struct clk_ops dpll_ck_ops = {
 371         .enable         = &omap3_noncore_dpll_enable,
 372         .disable        = &omap3_noncore_dpll_disable,
 373         .recalc_rate    = &omap3_dpll_recalc,
 374         .round_rate     = &omap2_dpll_round_rate,
 375         .set_rate       = &omap3_noncore_dpll_set_rate,
 376         .get_parent     = &omap2_init_dpll_parent,
 377 };
 378
 379 static struct clk_hw_omap dpll_iva_ck_hw = {
 380         .hw = {
 381                 .clk = &dpll_iva_ck,
 382         },
 383         .dpll_data      = &dpll_iva_dd,
 384         .ops            = &clkhwops_omap3_dpll,
 385 };
 386
 387 DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_core_ck_parents, dpll_ck_ops);
 388
 389 static const char *dpll_iva_x2_ck_parents[] = {
 390         "dpll_iva_ck",
 391 };
 392
 393 static struct clk dpll_iva_x2_ck;
 394
 395 static struct clk_hw_omap dpll_iva_x2_ck_hw = {
 396         .hw = {
 397                 .clk = &dpll_iva_x2_ck,
 398         },
 399 };
 400
 401 DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
 402
 403 DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
 404                           0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
 405                           OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
 406
 407 DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
 408                           0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
 409                           OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
 410
 411 /* DPLL_MPU */
 412 static struct dpll_data dpll_mpu_dd = {
 413         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
 414         .clk_bypass     = &div_mpu_hs_clk,
 415         .clk_ref        = &sys_clkin_ck,
 416         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
 417         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 418         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
 419         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
 420         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 421         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 422         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 423         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 424         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 425         .max_multiplier = 2047,
 426         .max_divider    = 128,
 427         .min_divider    = 1,
 428 };
 429
 430 static struct clk dpll_mpu_ck;
 431
 432 static struct clk_hw_omap dpll_mpu_ck_hw = {
 433         .hw = {
 434                 .clk = &dpll_mpu_ck,
 435         },
 436         .dpll_data      = &dpll_mpu_dd,
 437         .ops            = &clkhwops_omap3_dpll,
 438 };
 439
 440 DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_ck_ops);
 441
 442 DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
 443
 444 DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
 445                           OMAP4430_CM_DIV_M2_DPLL_MPU,
 446                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
 447
 448 DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
 449                         &dpll_abe_m3x2_ck, 0x0, 1, 2);
 450
 451 static const char *per_hsd_byp_clk_mux_ck_parents[] = {
 452         "sys_clkin_ck", "per_hs_clk_div_ck",
 453 };
 454
 455 DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
 456                0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
 457                OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
 458
 459 /* DPLL_PER */
 460 static struct dpll_data dpll_per_dd = {
 461         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
 462         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
 463         .clk_ref        = &sys_clkin_ck,
 464         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
 465         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 466         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
 467         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
 468         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
 469         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
 470         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 471         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 472         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 473         .max_multiplier = 2047,
 474         .max_divider    = 128,
 475         .min_divider    = 1,
 476 };
 477
 478
 479 static struct clk dpll_per_ck;
 480
 481 static struct clk_hw_omap dpll_per_ck_hw = {
 482         .hw = {
 483                 .clk = &dpll_per_ck,
 484         },
 485         .dpll_data      = &dpll_per_dd,
 486         .ops            = &clkhwops_omap3_dpll,
 487 };
 488
 489 DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ck_ops);
 490
 491 DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
 492                    OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
 493                    OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
 494
 495 static const char *dpll_per_x2_ck_parents[] = {
 496         "dpll_per_ck",
 497 };
 498
 499 static struct clk dpll_per_x2_ck;
 500
 501 static struct clk_hw_omap dpll_per_x2_ck_hw = {
 502         .hw = {
 503                 .clk = &dpll_per_x2_ck,
 504         },
 505         .flags          = CLOCK_CLKOUTX2,
 506         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 507         .ops            = &clkhwops_omap4_dpllmx,
 508 };
 509
 510 DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
 511
 512 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
 513                           0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
 514                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
 515
 516 static const char *dpll_per_m3x2_ck_parents[] = {
 517         "dpll_per_x2_ck",
 518 };
 519
 520 static const struct clksel dpll_per_m3x2_div[] = {
 521         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
 522         { .parent = NULL },
 523 };
 524
 525 /* XXX Missing round_rate, set_rate in ops */
 526 DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
 527                          OMAP4430_CM_DIV_M3_DPLL_PER,
 528                          OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
 529                          OMAP4430_CM_DIV_M3_DPLL_PER,
 530                          OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
 531                          dpll_per_m3x2_ck_parents, dmic_fck_ops);
 532
 533 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
 534                           0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
 535                           OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
 536
 537 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
 538                           0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
 539                           OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
 540
 541 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
 542                           0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
 543                           OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
 544
 545 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
 546                           0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
 547                           OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
 548
 549 DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
 550                         &dpll_abe_m3x2_ck, 0x0, 1, 3);
 551
 552 /* DPLL_USB */
 553 static struct dpll_data dpll_usb_dd = {
 554         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
 555         .clk_bypass     = &usb_hs_clk_div_ck,
 556         .flags          = DPLL_J_TYPE,
 557         .clk_ref        = &sys_clkin_ck,
 558         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
 559         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 560         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
 561         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
 562         .mult_mask      = OMAP4430_DPLL_MULT_USB_MASK,
 563         .div1_mask      = OMAP4430_DPLL_DIV_0_7_MASK,
 564         .enable_mask    = OMAP4430_DPLL_EN_MASK,
 565         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
 566         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
 567         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
 568         .max_multiplier = 4095,
 569         .max_divider    = 256,
 570         .min_divider    = 1,
 571 };
 572
 573 static struct clk dpll_usb_ck;
 574
 575 static struct clk_hw_omap dpll_usb_ck_hw = {
 576         .hw = {
 577                 .clk = &dpll_usb_ck,
 578         },
 579         .dpll_data      = &dpll_usb_dd,
 580         .ops            = &clkhwops_omap3_dpll,
 581 };
 582
 583 DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_core_ck_parents, dpll_ck_ops);
 584
 585 static const char *dpll_usb_clkdcoldo_ck_parents[] = {
 586         "dpll_usb_ck",
 587 };
 588
 589 static struct clk dpll_usb_clkdcoldo_ck;
 590
 591 static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
 592 };
 593
 594 static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
 595         .hw = {
 596                 .clk = &dpll_usb_clkdcoldo_ck,
 597         },
 598         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
 599         .ops            = &clkhwops_omap4_dpllmx,
 600 };
 601
 602 DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
 603                   dpll_usb_clkdcoldo_ck_ops);
 604
 605 DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
 606                           OMAP4430_CM_DIV_M2_DPLL_USB,
 607                           OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
 608
 609 static const char *ducati_clk_mux_ck_parents[] = {
 610         "div_core_ck", "dpll_per_m6x2_ck",
 611 };
 612
 613 DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
 614                OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
 615                OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
 616
 617 DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
 618                         0x0, 1, 16);
 619
 620 DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
 621                         1, 4);
 622
 623 DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
 624                         0x0, 1, 8);
 625
 626 static const struct clk_div_table func_48m_fclk_rates[] = {
 627         { .div = 4, .val = 0 },
 628         { .div = 8, .val = 1 },
 629         { .div = 0 },
 630 };
 631 DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
 632                          0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
 633                          OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
 634                          NULL);
 635
 636 DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
 637                         0x0, 1, 4);
 638
 639 static const struct clk_div_table func_64m_fclk_rates[] = {
 640         { .div = 2, .val = 0 },
 641         { .div = 4, .val = 1 },
 642         { .div = 0 },
 643 };
 644 DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
 645                          0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
 646                          OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
 647                          NULL);
 648
 649 static const struct clk_div_table func_96m_fclk_rates[] = {
 650         { .div = 2, .val = 0 },
 651         { .div = 4, .val = 1 },
 652         { .div = 0 },
 653 };
 654 DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
 655                          0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
 656                          OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
 657                          NULL);
 658
 659 static const struct clk_div_table init_60m_fclk_rates[] = {
 660         { .div = 1, .val = 0 },
 661         { .div = 8, .val = 1 },
 662         { .div = 0 },
 663 };
 664 DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
 665                          0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
 666                          OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
 667                          0x0, init_60m_fclk_rates, NULL);
 668
 669 DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
 670                    OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
 671                    OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
 672
 673 DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
 674                    OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
 675                    OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
 676
 677 DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
 678                         0x0, 1, 16);
 679
 680 static const char *l4_wkup_clk_mux_ck_parents[] = {
 681         "sys_clkin_ck", "lp_clk_div_ck",
 682 };
 683
 684 DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
 685                OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
 686                OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
 687
 688 static const struct clk_div_table ocp_abe_iclk_rates[] = {
 689         { .div = 2, .val = 0 },
 690         { .div = 1, .val = 1 },
 691         { .div = 0 },
 692 };
 693 DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
 694                          OMAP4430_CM1_ABE_AESS_CLKCTRL,
 695                          OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
 696                          OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
 697                          0x0, ocp_abe_iclk_rates, NULL);
 698
 699 DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
 700                         0x0, 1, 4);
 701
 702 DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
 703                    OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
 704                    OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
 705
 706 DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
 707                    OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
 708                    OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
 709
 710 static struct clk dbgclk_mux_ck;
 711 DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
 712 DEFINE_STRUCT_CLK(dbgclk_mux_ck, dpll_core_ck_parents,
 713                   dpll_usb_clkdcoldo_ck_ops);
 714
 715 /* Leaf clocks controlled by modules */
 716
 717 DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
 718                 OMAP4430_CM_L4SEC_AES1_CLKCTRL,
 719                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 720
 721 DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
 722                 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
 723                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 724
 725 DEFINE_CLK_GATE(aess_fck, "aess_fclk", &aess_fclk, 0x0,
 726                 OMAP4430_CM1_ABE_AESS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
 727                 0x0, NULL);
 728
 729 DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 730                 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 731                 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
 732
 733 static const struct clk_div_table div_ts_ck_rates[] = {
 734         { .div = 8, .val = 0 },
 735         { .div = 16, .val = 1 },
 736         { .div = 32, .val = 2 },
 737         { .div = 0 },
 738 };
 739 DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
 740                          0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 741                          OMAP4430_CLKSEL_24_25_SHIFT,
 742                          OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
 743                          NULL);
 744
 745 DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
 746                 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 747                 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
 748                 0x0, NULL);
 749
 750 DEFINE_CLK_GATE(des3des_fck, "l4_div_ck", &l4_div_ck, 0x0,
 751                 OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
 752                 OMAP4430_MODULEMODE_SWCTRL_SHIFT,
 753                 0x0, NULL);
 754
 755 static const char *dmic_sync_mux_ck_parents[] = {
 756         "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
 757 };
 758
 759 DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
 760                0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 761                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
 762                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
 763
 764 static const struct clksel func_dmic_abe_gfclk_sel[] = {
 765         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
 766         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
 767         { .parent = &slimbus_clk, .rates = div_1_2_rates },
 768         { .parent = NULL },
 769 };
 770
 771 static const char *dmic_fck_parents[] = {
 772         "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
 773 };
 774
 775 /* Merged func_dmic_abe_gfclk into dmic */
 776 static struct clk dmic_fck;
 777
 778 DEFINE_CLK_OMAP_MUX_GATE(dmic_fck, "abe_clkdm", func_dmic_abe_gfclk_sel,
 779                          OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 780                          OMAP4430_CLKSEL_SOURCE_MASK,
 781                          OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 782                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
 783                          dmic_fck_parents, dmic_fck_ops);
 784
 785 DEFINE_CLK_GATE(dsp_fck, "dpll_iva_m4x2_ck", &dpll_iva_m4x2_ck, 0x0,
 786                 OMAP4430_CM_TESLA_TESLA_CLKCTRL,
 787                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 788
 789 DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
 790                 OMAP4430_CM_DSS_DSS_CLKCTRL,
 791                 OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
 792
 793 DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
 794                 OMAP4430_CM_DSS_DSS_CLKCTRL,
 795                 OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
 796
 797 DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
 798                 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
 799                 0x0, NULL);
 800
 801 DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
 802                 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
 803                 0x0, NULL);
 804
 805 DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
 806                 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
 807                 0x0, NULL);
 808
 809 DEFINE_CLK_GATE(efuse_ctrl_cust_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
 810                 OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
 811                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 812
 813 DEFINE_CLK_GATE(emif1_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
 814                 OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
 815                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 816
 817 DEFINE_CLK_GATE(emif2_fck, "ddrphy_ck", &ddrphy_ck, 0x0,
 818                 OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
 819                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 820
 821 DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
 822                    OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
 823                    OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
 824
 825 DEFINE_CLK_GATE(fpka_fck, "l4_div_ck", &l4_div_ck, 0x0,
 826                 OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
 827                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 828
 829 DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 830                 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
 831                 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
 832
 833 DEFINE_CLK_GATE(gpio1_ick, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, 0x0,
 834                 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
 835                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 836
 837 DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 838                 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
 839                 0x0, NULL);
 840
 841 DEFINE_CLK_GATE(gpio2_ick, "l4_div_ck", &l4_div_ck, 0x0,
 842                 OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
 843                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 844
 845 DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 846                 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
 847                 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
 848
 849 DEFINE_CLK_GATE(gpio3_ick, "l4_div_ck", &l4_div_ck, 0x0,
 850                 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
 851                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 852
 853 DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 854                 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
 855                 0x0, NULL);
 856
 857 DEFINE_CLK_GATE(gpio4_ick, "l4_div_ck", &l4_div_ck, 0x0,
 858                 OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
 859                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 860
 861 DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 862                 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
 863                 0x0, NULL);
 864
 865 DEFINE_CLK_GATE(gpio5_ick, "l4_div_ck", &l4_div_ck, 0x0,
 866                 OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
 867                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 868
 869 DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
 870                 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
 871                 0x0, NULL);
 872
 873 DEFINE_CLK_GATE(gpio6_ick, "l4_div_ck", &l4_div_ck, 0x0,
 874                 OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
 875                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 876
 877 DEFINE_CLK_GATE(gpmc_ick, "l3_div_ck", &l3_div_ck, 0x0,
 878                 OMAP4430_CM_L3_2_GPMC_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
 879                 0x0, NULL);
 880
 881 static const struct clksel sgx_clk_mux_sel[] = {
 882         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
 883         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
 884         { .parent = NULL },
 885 };
 886
 887 static const char *gpu_fck_parents[] = {
 888         "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
 889 };
 890
 891 /* Merged sgx_clk_mux into gpu */
 892 DEFINE_CLK_OMAP_MUX_GATE(gpu_fck, "l3_gfx_clkdm", sgx_clk_mux_sel,
 893                          OMAP4430_CM_GFX_GFX_CLKCTRL,
 894                          OMAP4430_CLKSEL_SGX_FCLK_MASK,
 895                          OMAP4430_CM_GFX_GFX_CLKCTRL,
 896                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
 897                          gpu_fck_parents, dmic_fck_ops);
 898
 899 DEFINE_CLK_GATE(hdq1w_fck, "func_12m_fclk", &func_12m_fclk, 0x0,
 900                 OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
 901                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 902
 903 DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
 904                    OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
 905                    OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
 906                    NULL);
 907
 908 DEFINE_CLK_GATE(i2c1_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
 909                 OMAP4430_CM_L4PER_I2C1_CLKCTRL,
 910                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 911
 912 DEFINE_CLK_GATE(i2c2_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
 913                 OMAP4430_CM_L4PER_I2C2_CLKCTRL,
 914                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 915
 916 DEFINE_CLK_GATE(i2c3_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
 917                 OMAP4430_CM_L4PER_I2C3_CLKCTRL,
 918                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 919
 920 DEFINE_CLK_GATE(i2c4_fck, "func_96m_fclk", &func_96m_fclk, 0x0,
 921                 OMAP4430_CM_L4PER_I2C4_CLKCTRL,
 922                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 923
 924 DEFINE_CLK_GATE(ipu_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
 925                 OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
 926                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 927
 928 DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
 929                 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
 930                 0x0, NULL);
 931
 932 DEFINE_CLK_GATE(iss_fck, "ducati_clk_mux_ck", &ducati_clk_mux_ck, 0x0,
 933                 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
 934                 0x0, NULL);
 935
 936 DEFINE_CLK_GATE(iva_fck, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
 937                 OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
 938                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
 939
 940 DEFINE_CLK_GATE(kbd_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
 941                 OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
 942                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 943
 944 static struct clk l3_instr_ick;
 945
 946 static const char *l3_instr_ick_parent_names[] = {
 947         "l3_div_ck",
 948 };
 949
 950 static const struct clk_ops l3_instr_ick_ops = {
 951         .enable         = &omap2_dflt_clk_enable,
 952         .disable        = &omap2_dflt_clk_disable,
 953         .is_enabled     = &omap2_dflt_clk_is_enabled,
 954         .init           = &omap2_init_clk_clkdm,
 955 };
 956
 957 static struct clk_hw_omap l3_instr_ick_hw = {
 958         .hw = {
 959                 .clk = &l3_instr_ick,
 960         },
 961         .enable_reg     = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
 962         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
 963         .clkdm_name     = "l3_instr_clkdm",
 964 };
 965
 966 DEFINE_STRUCT_CLK(l3_instr_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
 967
 968 static struct clk l3_main_3_ick;
 969 static struct clk_hw_omap l3_main_3_ick_hw = {
 970         .hw = {
 971                 .clk = &l3_main_3_ick,
 972         },
 973         .enable_reg     = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
 974         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
 975         .clkdm_name     = "l3_instr_clkdm",
 976 };
 977
 978 DEFINE_STRUCT_CLK(l3_main_3_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
 979
 980 DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
 981                OMAP4430_CM1_ABE_MCASP_CLKCTRL,
 982                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
 983                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
 984
 985 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
 986         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
 987         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
 988         { .parent = &slimbus_clk, .rates = div_1_2_rates },
 989         { .parent = NULL },
 990 };
 991
 992 static const char *mcasp_fck_parents[] = {
 993         "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
 994 };
 995
 996 /* Merged func_mcasp_abe_gfclk into mcasp */
 997 DEFINE_CLK_OMAP_MUX_GATE(mcasp_fck, "abe_clkdm", func_mcasp_abe_gfclk_sel,
 998                          OMAP4430_CM1_ABE_MCASP_CLKCTRL,
 999                          OMAP4430_CLKSEL_SOURCE_MASK,
1000                          OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1001                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1002                          mcasp_fck_parents, dmic_fck_ops);
1003
1004 DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1005                OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1006                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1007                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1008
1009 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1010         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1011         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1012         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1013         { .parent = NULL },
1014 };
1015
1016 static const char *mcbsp1_fck_parents[] = {
1017         "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1018 };
1019
1020 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1021 DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "abe_clkdm", func_mcbsp1_gfclk_sel,
1022                          OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1023                          OMAP4430_CLKSEL_SOURCE_MASK,
1024                          OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1025                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1026                          mcbsp1_fck_parents, dmic_fck_ops);
1027
1028 DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1029                OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1030                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1031                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1032
1033 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1034         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1035         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1036         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1037         { .parent = NULL },
1038 };
1039
1040 static const char *mcbsp2_fck_parents[] = {
1041         "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1042 };
1043
1044 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1045 DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "abe_clkdm", func_mcbsp2_gfclk_sel,
1046                          OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1047                          OMAP4430_CLKSEL_SOURCE_MASK,
1048                          OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1049                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1050                          mcbsp2_fck_parents, dmic_fck_ops);
1051
1052 DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
1053                OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1054                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1055                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1056
1057 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1058         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1059         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1060         { .parent = &slimbus_clk, .rates = div_1_2_rates },
1061         { .parent = NULL },
1062 };
1063
1064 static const char *mcbsp3_fck_parents[] = {
1065         "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
1066 };
1067
1068 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1069 DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "abe_clkdm", func_mcbsp3_gfclk_sel,
1070                          OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1071                          OMAP4430_CLKSEL_SOURCE_MASK,
1072                          OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1073                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1074                          mcbsp3_fck_parents, dmic_fck_ops);
1075
1076 static const char *mcbsp4_sync_mux_ck_parents[] = {
1077         "func_96m_fclk", "per_abe_nc_fclk",
1078 };
1079
1080 DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
1081                OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1082                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
1083                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
1084
1085 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1086         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1087         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1088         { .parent = NULL },
1089 };
1090
1091 static const char *mcbsp4_fck_parents[] = {
1092         "mcbsp4_sync_mux_ck", "pad_clks_ck",
1093 };
1094
1095 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1096 DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
1097                          OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1098                          OMAP4430_CLKSEL_SOURCE_24_24_MASK,
1099                          OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1100                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1101                          mcbsp4_fck_parents, dmic_fck_ops);
1102
1103 DEFINE_CLK_GATE(mcpdm_fck, "pad_clks_ck", &pad_clks_ck, 0x0,
1104                 OMAP4430_CM1_ABE_PDM_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1105                 0x0, NULL);
1106
1107 DEFINE_CLK_GATE(mcspi1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1108                 OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
1109                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1110
1111 DEFINE_CLK_GATE(mcspi2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1112                 OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
1113                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1114
1115 DEFINE_CLK_GATE(mcspi3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1116                 OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
1117                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1118
1119 DEFINE_CLK_GATE(mcspi4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1120                 OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
1121                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1122
1123 static const struct clksel hsmmc1_fclk_sel[] = {
1124         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1125         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1126         { .parent = NULL },
1127 };
1128
1129 static const char *mmc1_fck_parents[] = {
1130         "func_64m_fclk", "func_96m_fclk",
1131 };
1132
1133 /* Merged hsmmc1_fclk into mmc1 */
1134 DEFINE_CLK_OMAP_MUX_GATE(mmc1_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1135                          OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1136                          OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
1137                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1138                          mmc1_fck_parents, dmic_fck_ops);
1139
1140 /* Merged hsmmc2_fclk into mmc2 */
1141 DEFINE_CLK_OMAP_MUX_GATE(mmc2_fck, "l3_init_clkdm", hsmmc1_fclk_sel,
1142                          OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1143                          OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
1144                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1145                          mmc1_fck_parents, dmic_fck_ops);
1146
1147 DEFINE_CLK_GATE(mmc3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1148                 OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
1149                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1150
1151 DEFINE_CLK_GATE(mmc4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1152                 OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
1153                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1154
1155 DEFINE_CLK_GATE(mmc5_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1156                 OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
1157                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1158
1159 DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1160                 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1161                 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1162
1163 DEFINE_CLK_GATE(ocp2scp_usb_phy_ick, "l4_div_ck", &l4_div_ck, 0x0,
1164                 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1165                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1166
1167 static struct clk ocp_wp_noc_ick;
1168
1169 static struct clk_hw_omap ocp_wp_noc_ick_hw = {
1170         .hw = {
1171                 .clk = &ocp_wp_noc_ick,
1172         },
1173         .enable_reg     = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
1174         .enable_bit     = OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1175         .clkdm_name     = "l3_instr_clkdm",
1176 };
1177
1178 DEFINE_STRUCT_CLK(ocp_wp_noc_ick, l3_instr_ick_parent_names, l3_instr_ick_ops);
1179
1180 DEFINE_CLK_GATE(rng_ick, "l4_div_ck", &l4_div_ck, 0x0,
1181                 OMAP4430_CM_L4SEC_RNG_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1182                 0x0, NULL);
1183
1184 DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1185                 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1186                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1187
1188 DEFINE_CLK_GATE(sl2if_ick, "dpll_iva_m5x2_ck", &dpll_iva_m5x2_ck, 0x0,
1189                 OMAP4430_CM_IVAHD_SL2_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1190                 0x0, NULL);
1191
1192 DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
1193                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1194                 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
1195
1196 DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
1197                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1198                 OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
1199
1200 DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
1201                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1202                 OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
1203
1204 DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
1205                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1206                 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
1207
1208 DEFINE_CLK_GATE(slimbus1_fck, "ocp_abe_iclk", &ocp_abe_iclk, 0x0,
1209                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1210                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1211
1212 DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
1213                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1214                 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
1215
1216 DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
1217                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1218                 OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
1219
1220 DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
1221                 &pad_slimbus_core_clks_ck, 0x0,
1222                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1223                 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
1224
1225 DEFINE_CLK_GATE(slimbus2_fck, "l4_div_ck", &l4_div_ck, 0x0,
1226                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1227                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1228
1229 DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1230                 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1231                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1232
1233 DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1234                 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1235                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1236
1237 DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1238                 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1239                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1240
1241 static const struct clksel dmt1_clk_mux_sel[] = {
1242         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1243         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1244         { .parent = NULL },
1245 };
1246
1247 /* Merged dmt1_clk_mux into timer1 */
1248 DEFINE_CLK_OMAP_MUX_GATE(timer1_fck, "l4_wkup_clkdm", dmt1_clk_mux_sel,
1249                          OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1250                          OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1251                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1252                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1253
1254 /* Merged cm2_dm10_mux into timer10 */
1255 DEFINE_CLK_OMAP_MUX_GATE(timer10_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1256                          OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1257                          OMAP4430_CLKSEL_MASK,
1258                          OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1259                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1260                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1261
1262 /* Merged cm2_dm11_mux into timer11 */
1263 DEFINE_CLK_OMAP_MUX_GATE(timer11_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1264                          OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1265                          OMAP4430_CLKSEL_MASK,
1266                          OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1267                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1268                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1269
1270 /* Merged cm2_dm2_mux into timer2 */
1271 DEFINE_CLK_OMAP_MUX_GATE(timer2_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1272                          OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1273                          OMAP4430_CLKSEL_MASK,
1274                          OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1275                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1276                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1277
1278 /* Merged cm2_dm3_mux into timer3 */
1279 DEFINE_CLK_OMAP_MUX_GATE(timer3_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1280                          OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1281                          OMAP4430_CLKSEL_MASK,
1282                          OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1283                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1284                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1285
1286 /* Merged cm2_dm4_mux into timer4 */
1287 DEFINE_CLK_OMAP_MUX_GATE(timer4_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1288                          OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1289                          OMAP4430_CLKSEL_MASK,
1290                          OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1291                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1292                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1293
1294 static const struct clksel timer5_sync_mux_sel[] = {
1295         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1296         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1297         { .parent = NULL },
1298 };
1299
1300 static const char *timer5_fck_parents[] = {
1301         "syc_clk_div_ck", "sys_32k_ck",
1302 };
1303
1304 /* Merged timer5_sync_mux into timer5 */
1305 DEFINE_CLK_OMAP_MUX_GATE(timer5_fck, "abe_clkdm", timer5_sync_mux_sel,
1306                          OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
1307                          OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1308                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1309                          timer5_fck_parents, dmic_fck_ops);
1310
1311 /* Merged timer6_sync_mux into timer6 */
1312 DEFINE_CLK_OMAP_MUX_GATE(timer6_fck, "abe_clkdm", timer5_sync_mux_sel,
1313                          OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1314                          OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1315                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1316                          timer5_fck_parents, dmic_fck_ops);
1317
1318 /* Merged timer7_sync_mux into timer7 */
1319 DEFINE_CLK_OMAP_MUX_GATE(timer7_fck, "abe_clkdm", timer5_sync_mux_sel,
1320                          OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1321                          OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1322                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1323                          timer5_fck_parents, dmic_fck_ops);
1324
1325 /* Merged timer8_sync_mux into timer8 */
1326 DEFINE_CLK_OMAP_MUX_GATE(timer8_fck, "abe_clkdm", timer5_sync_mux_sel,
1327                          OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1328                          OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1329                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1330                          timer5_fck_parents, dmic_fck_ops);
1331
1332 /* Merged cm2_dm9_mux into timer9 */
1333 DEFINE_CLK_OMAP_MUX_GATE(timer9_fck, "l4_per_clkdm", dmt1_clk_mux_sel,
1334                          OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1335                          OMAP4430_CLKSEL_MASK,
1336                          OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1337                          OMAP4430_MODULEMODE_SWCTRL_SHIFT, NULL,
1338                          abe_dpll_bypass_clk_mux_ck_parents, dmic_fck_ops);
1339
1340 DEFINE_CLK_GATE(uart1_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1341                 OMAP4430_CM_L4PER_UART1_CLKCTRL,
1342                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1343
1344 DEFINE_CLK_GATE(uart2_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1345                 OMAP4430_CM_L4PER_UART2_CLKCTRL,
1346                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1347
1348 DEFINE_CLK_GATE(uart3_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1349                 OMAP4430_CM_L4PER_UART3_CLKCTRL,
1350                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1351
1352 DEFINE_CLK_GATE(uart4_fck, "func_48m_fclk", &func_48m_fclk, 0x0,
1353                 OMAP4430_CM_L4PER_UART4_CLKCTRL,
1354                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1355
1356 static struct clk usb_host_fs_fck;
1357
1358 static const char *usb_host_fs_fck_parent_names[] = {
1359         "func_48mc_fclk",
1360 };
1361
1362 static const struct clk_ops usb_host_fs_fck_ops = {
1363         .enable         = &omap2_dflt_clk_enable,
1364         .disable        = &omap2_dflt_clk_disable,
1365         .is_enabled     = &omap2_dflt_clk_is_enabled,
1366 };
1367
1368 static struct clk_hw_omap usb_host_fs_fck_hw = {
1369         .hw = {
1370                 .clk = &usb_host_fs_fck,
1371         },
1372         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
1373         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1374         .clkdm_name     = "l3_init_clkdm",
1375 };
1376
1377 DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
1378                   usb_host_fs_fck_ops);
1379
1380 static const char *utmi_p1_gfclk_parents[] = {
1381         "init_60m_fclk", "xclk60mhsp1_ck",
1382 };
1383
1384 DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
1385                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1386                OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
1387                0x0, NULL);
1388
1389 DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
1390                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1391                 OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
1392
1393 static const char *utmi_p2_gfclk_parents[] = {
1394         "init_60m_fclk", "xclk60mhsp2_ck",
1395 };
1396
1397 DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
1398                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1399                OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
1400                0x0, NULL);
1401
1402 DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
1403                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1404                 OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
1405
1406 DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1407                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1408                 OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
1409
1410 DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
1411                 &dpll_usb_m2_ck, 0x0,
1412                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1413                 OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
1414
1415 DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
1416                 &init_60m_fclk, 0x0,
1417                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1418                 OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
1419
1420 DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
1421                 &init_60m_fclk, 0x0,
1422                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1423                 OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
1424
1425 DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
1426                 &dpll_usb_m2_ck, 0x0,
1427                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1428                 OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
1429
1430 DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
1431                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1432                 OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
1433
1434 DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
1435                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1436                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1437
1438 static const char *otg_60m_gfclk_parents[] = {
1439         "utmi_phy_clkout_ck", "xclk60motg_ck",
1440 };
1441
1442 DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
1443                OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
1444                OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
1445
1446 DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
1447                 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1448                 OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
1449
1450 DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
1451                 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1452                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1453
1454 DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
1455                 OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
1456                 OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
1457
1458 DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1459                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1460                 OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
1461
1462 DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1463                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1464                 OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
1465
1466 DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1467                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1468                 OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
1469
1470 DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
1471                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1472                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1473
1474 static const struct clk_div_table usim_ck_rates[] = {
1475         { .div = 14, .val = 0 },
1476         { .div = 18, .val = 1 },
1477         { .div = 0 },
1478 };
1479 DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
1480                          OMAP4430_CM_WKUP_USIM_CLKCTRL,
1481                          OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
1482                          0x0, usim_ck_rates, NULL);
1483
1484 DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
1485                 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
1486                 0x0, NULL);
1487
1488 DEFINE_CLK_GATE(usim_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1489                 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_MODULEMODE_HWCTRL_SHIFT,
1490                 0x0, NULL);
1491
1492 DEFINE_CLK_GATE(wd_timer2_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1493                 OMAP4430_CM_WKUP_WDT2_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1494                 0x0, NULL);
1495
1496 DEFINE_CLK_GATE(wd_timer3_fck, "sys_32k_ck", &sys_32k_ck, 0x0,
1497                 OMAP4430_CM1_ABE_WDT3_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1498                 0x0, NULL);
1499
1500 /* Remaining optional clocks */
1501 static const char *pmd_stm_clock_mux_ck_parents[] = {
1502         "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
1503 };
1504
1505 DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1506                OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
1507                OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
1508
1509 DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1510                OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1511                OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
1512                OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
1513
1514 DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
1515                    &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1516                    OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
1517                    OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
1518                    NULL);
1519
1520 static const char *trace_clk_div_ck_parents[] = {
1521         "pmd_trace_clk_mux_ck",
1522 };
1523
1524 static const struct clksel trace_clk_div_div[] = {
1525         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
1526         { .parent = NULL },
1527 };
1528
1529 static struct clk trace_clk_div_ck;
1530
1531 static const struct clk_ops trace_clk_div_ck_ops = {
1532         .recalc_rate    = &omap2_clksel_recalc,
1533         .set_rate       = &omap2_clksel_set_rate,
1534         .round_rate     = &omap2_clksel_round_rate,
1535         .init           = &omap2_init_clk_clkdm,
1536         .enable         = &omap2_clkops_enable_clkdm,
1537         .disable        = &omap2_clkops_disable_clkdm,
1538 };
1539
1540 static struct clk_hw_omap trace_clk_div_ck_hw = {
1541         .hw = {
1542                 .clk = &trace_clk_div_ck,
1543         },
1544         .clkdm_name     = "emu_sys_clkdm",
1545         .clksel         = trace_clk_div_div,
1546         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1547         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
1548 };
1549
1550 DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
1551                   trace_clk_div_ck_ops);
1552
1553 /* SCRM aux clk nodes */
1554
1555 static const struct clksel auxclk_src_sel[] = {
1556         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1557         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
1558         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
1559         { .parent = NULL },
1560 };
1561
1562 static const char *auxclk_src_ck_parents[] = {
1563         "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
1564 };
1565
1566 static const struct clk_ops auxclk_src_ck_ops = {
1567         .enable         = &omap2_dflt_clk_enable,
1568         .disable        = &omap2_dflt_clk_disable,
1569         .is_enabled     = &omap2_dflt_clk_is_enabled,
1570         .recalc_rate    = &omap2_clksel_recalc,
1571         .get_parent     = &omap2_clksel_find_parent_index,
1572 };
1573
1574 DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
1575                          OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
1576                          OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
1577                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1578
1579 DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
1580                    OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1581                    0x0, NULL);
1582
1583 DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
1584                          OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
1585                          OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
1586                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1587
1588 DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
1589                    OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1590                    0x0, NULL);
1591
1592 DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
1593                          OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
1594                          OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
1595                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1596
1597 DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
1598                    OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1599                    0x0, NULL);
1600
1601 DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
1602                          OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
1603                          OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
1604                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1605
1606 DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
1607                    OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1608                    0x0, NULL);
1609
1610 DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
1611                          OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
1612                          OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
1613                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1614
1615 DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
1616                    OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1617                    0x0, NULL);
1618
1619 DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
1620                          OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
1621                          OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
1622                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1623
1624 DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
1625                    OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1626                    0x0, NULL);
1627
1628 static const char *auxclkreq_ck_parents[] = {
1629         "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
1630         "auxclk5_ck",
1631 };
1632
1633 DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
1634                OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1635                0x0, NULL);
1636
1637 DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
1638                OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1639                0x0, NULL);
1640
1641 DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
1642                OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1643                0x0, NULL);
1644
1645 DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
1646                OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1647                0x0, NULL);
1648
1649 DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
1650                OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1651                0x0, NULL);
1652
1653 DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
1654                OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1655                0x0, NULL);
1656
1657 /*
1658  * clkdev
1659  */
1660
1661 static struct omap_clk omap44xx_clks[] = {
1662         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
1663         CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck,       CK_443X),
1664         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
1665         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
1666         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
1667         CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk,       CK_443X),
1668         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
1669         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
1670         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
1671         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
1672         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
1673         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
1674         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
1675         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
1676         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
1677         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
1678         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
1679         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
1680         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
1681         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
1682         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
1683         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
1684         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
1685         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
1686         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
1687         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
1688         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
1689         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
1690         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
1691         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
1692         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
1693         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
1694         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
1695         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
1696         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
1697         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
1698         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
1699         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
1700         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
1701         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
1702         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
1703         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
1704         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
1705         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
1706         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
1707         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
1708         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
1709         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
1710         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
1711         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
1712         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
1713         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
1714         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
1715         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
1716         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
1717         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
1718         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
1719         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
1720         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
1721         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
1722         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
1723         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
1724         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
1725         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
1726         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
1727         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
1728         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
1729         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
1730         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
1731         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
1732         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
1733         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
1734         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
1735         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
1736         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
1737         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
1738         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
1739         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
1740         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
1741         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
1742         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
1743         CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
1744         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
1745         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
1746         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
1747         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
1748         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
1749         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
1750         CLK(NULL,       "aess_fck",                     &aess_fck,      CK_443X),
1751         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
1752         CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
1753         CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
1754         CLK(NULL,       "des3des_fck",                  &des3des_fck,   CK_443X),
1755         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
1756         CLK(NULL,       "dmic_fck",                     &dmic_fck,      CK_443X),
1757         CLK(NULL,       "dsp_fck",                      &dsp_fck,       CK_443X),
1758         CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
1759         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
1760         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
1761         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
1762         CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
1763         CLK("omapdss_dss",      "ick",                  &dss_fck,       CK_443X),
1764         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
1765         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
1766         CLK(NULL,       "emif2_fck",                    &emif2_fck,     CK_443X),
1767         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
1768         CLK(NULL,       "fpka_fck",                     &fpka_fck,      CK_443X),
1769         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
1770         CLK(NULL,       "gpio1_ick",                    &gpio1_ick,     CK_443X),
1771         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
1772         CLK(NULL,       "gpio2_ick",                    &gpio2_ick,     CK_443X),
1773         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
1774         CLK(NULL,       "gpio3_ick",                    &gpio3_ick,     CK_443X),
1775         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
1776         CLK(NULL,       "gpio4_ick",                    &gpio4_ick,     CK_443X),
1777         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
1778         CLK(NULL,       "gpio5_ick",                    &gpio5_ick,     CK_443X),
1779         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
1780         CLK(NULL,       "gpio6_ick",                    &gpio6_ick,     CK_443X),
1781         CLK(NULL,       "gpmc_ick",                     &gpmc_ick,      CK_443X),
1782         CLK(NULL,       "gpu_fck",                      &gpu_fck,       CK_443X),
1783         CLK(NULL,       "hdq1w_fck",                    &hdq1w_fck,     CK_443X),
1784         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
1785         CLK(NULL,       "i2c1_fck",                     &i2c1_fck,      CK_443X),
1786         CLK(NULL,       "i2c2_fck",                     &i2c2_fck,      CK_443X),
1787         CLK(NULL,       "i2c3_fck",                     &i2c3_fck,      CK_443X),
1788         CLK(NULL,       "i2c4_fck",                     &i2c4_fck,      CK_443X),
1789         CLK(NULL,       "ipu_fck",                      &ipu_fck,       CK_443X),
1790         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
1791         CLK(NULL,       "iss_fck",                      &iss_fck,       CK_443X),
1792         CLK(NULL,       "iva_fck",                      &iva_fck,       CK_443X),
1793         CLK(NULL,       "kbd_fck",                      &kbd_fck,       CK_443X),
1794         CLK(NULL,       "l3_instr_ick",                 &l3_instr_ick,  CK_443X),
1795         CLK(NULL,       "l3_main_3_ick",                &l3_main_3_ick, CK_443X),
1796         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
1797         CLK(NULL,       "mcasp_fck",                    &mcasp_fck,     CK_443X),
1798         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
1799         CLK(NULL,       "mcbsp1_fck",                   &mcbsp1_fck,    CK_443X),
1800         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
1801         CLK(NULL,       "mcbsp2_fck",                   &mcbsp2_fck,    CK_443X),
1802         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
1803         CLK(NULL,       "mcbsp3_fck",                   &mcbsp3_fck,    CK_443X),
1804         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
1805         CLK(NULL,       "mcbsp4_fck",                   &mcbsp4_fck,    CK_443X),
1806         CLK(NULL,       "mcpdm_fck",                    &mcpdm_fck,     CK_443X),
1807         CLK(NULL,       "mcspi1_fck",                   &mcspi1_fck,    CK_443X),
1808         CLK(NULL,       "mcspi2_fck",                   &mcspi2_fck,    CK_443X),
1809         CLK(NULL,       "mcspi3_fck",                   &mcspi3_fck,    CK_443X),
1810         CLK(NULL,       "mcspi4_fck",                   &mcspi4_fck,    CK_443X),
1811         CLK(NULL,       "mmc1_fck",                     &mmc1_fck,      CK_443X),
1812         CLK(NULL,       "mmc2_fck",                     &mmc2_fck,      CK_443X),
1813         CLK(NULL,       "mmc3_fck",                     &mmc3_fck,      CK_443X),
1814         CLK(NULL,       "mmc4_fck",                     &mmc4_fck,      CK_443X),
1815         CLK(NULL,       "mmc5_fck",                     &mmc5_fck,      CK_443X),
1816         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
1817         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
1818         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
1819         CLK(NULL,       "rng_ick",                      &rng_ick,       CK_443X),
1820         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
1821         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
1822         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
1823         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
1824         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
1825         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
1826         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
1827         CLK(NULL,       "slimbus1_fck",                 &slimbus1_fck,  CK_443X),
1828         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
1829         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
1830         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
1831         CLK(NULL,       "slimbus2_fck",                 &slimbus2_fck,  CK_443X),
1832         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
1833         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
1834         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
1835         CLK(NULL,       "timer1_fck",                   &timer1_fck,    CK_443X),
1836         CLK(NULL,       "timer10_fck",                  &timer10_fck,   CK_443X),
1837         CLK(NULL,       "timer11_fck",                  &timer11_fck,   CK_443X),
1838         CLK(NULL,       "timer2_fck",                   &timer2_fck,    CK_443X),
1839         CLK(NULL,       "timer3_fck",                   &timer3_fck,    CK_443X),
1840         CLK(NULL,       "timer4_fck",                   &timer4_fck,    CK_443X),
1841         CLK(NULL,       "timer5_fck",                   &timer5_fck,    CK_443X),
1842         CLK(NULL,       "timer6_fck",                   &timer6_fck,    CK_443X),
1843         CLK(NULL,       "timer7_fck",                   &timer7_fck,    CK_443X),
1844         CLK(NULL,       "timer8_fck",                   &timer8_fck,    CK_443X),
1845         CLK(NULL,       "timer9_fck",                   &timer9_fck,    CK_443X),
1846         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
1847         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
1848         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
1849         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
1850         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
1851         CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
1852         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
1853         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
1854         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
1855         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
1856         CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
1857         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
1858         CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
1859         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
1860         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
1861         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
1862         CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
1863         CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
1864         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
1865         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
1866         CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
1867         CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick,        CK_443X),
1868         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
1869         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
1870         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
1871         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
1872         CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
1873         CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
1874         CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
1875         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
1876         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
1877         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
1878         CLK(NULL,       "wd_timer2_fck",                &wd_timer2_fck, CK_443X),
1879         CLK(NULL,       "wd_timer3_fck",                &wd_timer3_fck, CK_443X),
1880         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
1881         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
1882         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
1883         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
1884         CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
1885         CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
1886         CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
1887         CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
1888         CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
1889         CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
1890         CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
1891         CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
1892         CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
1893         CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
1894         CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
1895         CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
1896         CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
1897         CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
1898         CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
1899         CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
1900         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
1901         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
1902         CLK("omap-gpmc",        "fck",                  &dummy_ck,      CK_443X),
1903         CLK("omap_i2c.1",       "ick",                  &dummy_ck,      CK_443X),
1904         CLK("omap_i2c.2",       "ick",                  &dummy_ck,      CK_443X),
1905         CLK("omap_i2c.3",       "ick",                  &dummy_ck,      CK_443X),
1906         CLK("omap_i2c.4",       "ick",                  &dummy_ck,      CK_443X),
1907         CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
1908         CLK("omap_hsmmc.0",     "ick",                  &dummy_ck,      CK_443X),
1909         CLK("omap_hsmmc.1",     "ick",                  &dummy_ck,      CK_443X),
1910         CLK("omap_hsmmc.2",     "ick",                  &dummy_ck,      CK_443X),
1911         CLK("omap_hsmmc.3",     "ick",                  &dummy_ck,      CK_443X),
1912         CLK("omap_hsmmc.4",     "ick",                  &dummy_ck,      CK_443X),
1913         CLK("omap-mcbsp.1",     "ick",                  &dummy_ck,      CK_443X),
1914         CLK("omap-mcbsp.2",     "ick",                  &dummy_ck,      CK_443X),
1915         CLK("omap-mcbsp.3",     "ick",                  &dummy_ck,      CK_443X),
1916         CLK("omap-mcbsp.4",     "ick",                  &dummy_ck,      CK_443X),
1917         CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
1918         CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
1919         CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
1920         CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
1921         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
1922         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
1923         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
1924         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
1925         CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
1926         CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
1927         CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
1928         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
1929         CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
1930         /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
1931         CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1932         CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1933         CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1934         CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1935         CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1936         CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1937         CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1938         CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1939         CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1940         CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1941         CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1942         CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1943         CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1944         CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1945         CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1946         CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1947         CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1948         CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1949         CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1950         CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1951         CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1952         CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1953         CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
1954 };
1955
1956 static const char *enable_init_clks[] = {
1957         "emif1_fck",
1958         "emif2_fck",
1959         "gpmc_ick",
1960         "l3_instr_ick",
1961         "l3_main_3_ick",
1962         "ocp_wp_noc_ick",
1963 };
1964
1965 int __init omap4xxx_clk_init(void)
1966 {
1967         u32 cpu_clkflg;
1968         struct omap_clk *c;
1969
1970         if (cpu_is_omap443x()) {
1971                 cpu_mask = RATE_IN_4430;
1972                 cpu_clkflg = CK_443X;
1973         } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
1974                 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
1975                 cpu_clkflg = CK_446X | CK_443X;
1976
1977                 if (cpu_is_omap447x())
1978                         pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
1979         } else {
1980                 return 0;
1981         }
1982
1983         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
1984                                                                         c++) {
1985                 if (c->cpu & cpu_clkflg) {
1986                         clkdev_add(&c->lk);
1987                         if (!__clk_init(NULL, c->lk.clk))
1988                                 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1989                 }
1990         }
1991
1992         omap2_clk_disable_autoidle_all();
1993
1994         omap2_clk_enable_init_clocks(enable_init_clks,
1995                                      ARRAY_SIZE(enable_init_clks));
1996
1997         return 0;
1998 }