arch/arm/mach-omap1/pm.c

   1 /*
   2  * linux/arch/arm/mach-omap1/pm.c
   3  *
   4  * OMAP Power Management Routines
   5  *
   6  * Original code for the SA11x0:
   7  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   8  *
   9  * Modified for the PXA250 by Nicolas Pitre:
  10  * Copyright (c) 2002 Monta Vista Software, Inc.
  11  *
  12  * Modified for the OMAP1510 by David Singleton:
  13  * Copyright (c) 2002 Monta Vista Software, Inc.
  14  *
  15  * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
  16  *
  17  * This program is free software; you can redistribute it and/or modify it
  18  * under the terms of the GNU General Public License as published by the
  19  * Free Software Foundation; either version 2 of the License, or (at your
  20  * option) any later version.
  21  *
  22  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * You should have received a copy of the GNU General Public License along
  34  * with this program; if not, write to the Free Software Foundation, Inc.,
  35  * 675 Mass Ave, Cambridge, MA 02139, USA.
  36  */
  37
  38 #include <linux/suspend.h>
  39 #include <linux/sched.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/sysfs.h>
  43 #include <linux/module.h>
  44 #include <linux/io.h>
  45 #include <linux/atomic.h>
  46
  47 #include <asm/irq.h>
  48 #include <asm/mach/time.h>
  49 #include <asm/mach/irq.h>
  50
  51 #include <plat/cpu.h>
  52 #include <plat/clock.h>
  53 #include <plat/sram.h>
  54 #include <plat/tc.h>
  55 #include <plat/mux.h>
  56 #include <plat/dma.h>
  57 #include <plat/dmtimer.h>
  58
  59 #include <mach/irqs.h>
  60
  61 #include "iomap.h"
  62 #include "pm.h"
  63
  64 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
  65 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
  66 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
  67 static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE];
  68 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
  69 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
  70
  71 #ifdef CONFIG_OMAP_32K_TIMER
  72
  73 static unsigned short enable_dyn_sleep = 1;
  74
  75 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
  76                          char *buf)
  77 {
  78         return sprintf(buf, "%hu\n", enable_dyn_sleep);
  79 }
  80
  81 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
  82                           const char * buf, size_t n)
  83 {
  84         unsigned short value;
  85         if (sscanf(buf, "%hu", &value) != 1 ||
  86             (value != 0 && value != 1)) {
  87                 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
  88                 return -EINVAL;
  89         }
  90         enable_dyn_sleep = value;
  91         return n;
  92 }
  93
  94 static struct kobj_attribute sleep_while_idle_attr =
  95         __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
  96
  97 #endif
  98
  99 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
 100
 101 /*
 102  * Let's power down on idle, but only if we are really
 103  * idle, because once we start down the path of
 104  * going idle we continue to do idle even if we get
 105  * a clock tick interrupt . .
 106  */
 107 void omap1_pm_idle(void)
 108 {
 109         extern __u32 arm_idlect1_mask;
 110         __u32 use_idlect1 = arm_idlect1_mask;
 111         int do_sleep = 0;
 112
 113         local_fiq_disable();
 114
 115 #if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER)
 116 #warning Enable 32kHz OS timer in order to allow sleep states in idle
 117         use_idlect1 = use_idlect1 & ~(1 << 9);
 118 #else
 119
 120         while (enable_dyn_sleep) {
 121
 122 #ifdef CONFIG_CBUS_TAHVO_USB
 123                 extern int vbus_active;
 124                 /* Clock requirements? */
 125                 if (vbus_active)
 126                         break;
 127 #endif
 128                 do_sleep = 1;
 129                 break;
 130         }
 131
 132 #endif
 133
 134 #ifdef CONFIG_OMAP_DM_TIMER
 135         use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
 136 #endif
 137
 138         if (omap_dma_running())
 139                 use_idlect1 &= ~(1 << 6);
 140
 141         /* We should be able to remove the do_sleep variable and multiple
 142          * tests above as soon as drivers, timer and DMA code have been fixed.
 143          * Even the sleep block count should become obsolete. */
 144         if ((use_idlect1 != ~0) || !do_sleep) {
 145
 146                 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
 147                 if (cpu_is_omap15xx())
 148                         use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
 149                 else
 150                         use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
 151                 omap_writel(use_idlect1, ARM_IDLECT1);
 152                 __asm__ volatile ("mcr  p15, 0, r0, c7, c0, 4");
 153                 omap_writel(saved_idlect1, ARM_IDLECT1);
 154
 155                 local_fiq_enable();
 156                 return;
 157         }
 158         omap_sram_suspend(omap_readl(ARM_IDLECT1),
 159                           omap_readl(ARM_IDLECT2));
 160
 161         local_fiq_enable();
 162 }
 163
 164 /*
 165  * Configuration of the wakeup event is board specific. For the
 166  * moment we put it into this helper function. Later it may move
 167  * to board specific files.
 168  */
 169 static void omap_pm_wakeup_setup(void)
 170 {
 171         u32 level1_wake = 0;
 172         u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
 173
 174         /*
 175          * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
 176          * and the L2 wakeup interrupts: keypad and UART2. Note that the
 177          * drivers must still separately call omap_set_gpio_wakeup() to
 178          * wake up to a GPIO interrupt.
 179          */
 180         if (cpu_is_omap7xx())
 181                 level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) |
 182                         OMAP_IRQ_BIT(INT_7XX_IH2_IRQ);
 183         else if (cpu_is_omap15xx())
 184                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 185                         OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
 186         else if (cpu_is_omap16xx())
 187                 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
 188                         OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
 189
 190         omap_writel(~level1_wake, OMAP_IH1_MIR);
 191
 192         if (cpu_is_omap7xx()) {
 193                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 194                 omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) |
 195                                 OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)),
 196                                 OMAP_IH2_1_MIR);
 197         } else if (cpu_is_omap15xx()) {
 198                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 199                 omap_writel(~level2_wake,  OMAP_IH2_MIR);
 200         } else if (cpu_is_omap16xx()) {
 201                 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
 202                 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
 203
 204                 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
 205                 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
 206                             OMAP_IH2_1_MIR);
 207                 omap_writel(~0x0, OMAP_IH2_2_MIR);
 208                 omap_writel(~0x0, OMAP_IH2_3_MIR);
 209         }
 210
 211         /*  New IRQ agreement, recalculate in cascade order */
 212         omap_writel(1, OMAP_IH2_CONTROL);
 213         omap_writel(1, OMAP_IH1_CONTROL);
 214 }
 215
 216 #define EN_DSPCK        13      /* ARM_CKCTL */
 217 #define EN_APICK        6       /* ARM_IDLECT2 */
 218 #define DSP_EN          1       /* ARM_RSTCT1 */
 219
 220 void omap1_pm_suspend(void)
 221 {
 222         unsigned long arg0 = 0, arg1 = 0;
 223
 224         printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
 225                 omap_rev());
 226
 227         omap_serial_wake_trigger(1);
 228
 229         if (!cpu_is_omap15xx())
 230                 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
 231
 232         /*
 233          * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
 234          */
 235
 236         local_irq_disable();
 237         local_fiq_disable();
 238
 239         /*
 240          * Step 2: save registers
 241          *
 242          * The omap is a strange/beautiful device. The caches, memory
 243          * and register state are preserved across power saves.
 244          * We have to save and restore very little register state to
 245          * idle the omap.
 246          *
 247          * Save interrupt, MPUI, ARM and UPLD control registers.
 248          */
 249
 250         if (cpu_is_omap7xx()) {
 251                 MPUI7XX_SAVE(OMAP_IH1_MIR);
 252                 MPUI7XX_SAVE(OMAP_IH2_0_MIR);
 253                 MPUI7XX_SAVE(OMAP_IH2_1_MIR);
 254                 MPUI7XX_SAVE(MPUI_CTRL);
 255                 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
 256                 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
 257                 MPUI7XX_SAVE(EMIFS_CONFIG);
 258                 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
 259
 260         } else if (cpu_is_omap15xx()) {
 261                 MPUI1510_SAVE(OMAP_IH1_MIR);
 262                 MPUI1510_SAVE(OMAP_IH2_MIR);
 263                 MPUI1510_SAVE(MPUI_CTRL);
 264                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 265                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 266                 MPUI1510_SAVE(EMIFS_CONFIG);
 267                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 268         } else if (cpu_is_omap16xx()) {
 269                 MPUI1610_SAVE(OMAP_IH1_MIR);
 270                 MPUI1610_SAVE(OMAP_IH2_0_MIR);
 271                 MPUI1610_SAVE(OMAP_IH2_1_MIR);
 272                 MPUI1610_SAVE(OMAP_IH2_2_MIR);
 273                 MPUI1610_SAVE(OMAP_IH2_3_MIR);
 274                 MPUI1610_SAVE(MPUI_CTRL);
 275                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 276                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 277                 MPUI1610_SAVE(EMIFS_CONFIG);
 278                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 279         }
 280
 281         ARM_SAVE(ARM_CKCTL);
 282         ARM_SAVE(ARM_IDLECT1);
 283         ARM_SAVE(ARM_IDLECT2);
 284         if (!(cpu_is_omap15xx()))
 285                 ARM_SAVE(ARM_IDLECT3);
 286         ARM_SAVE(ARM_EWUPCT);
 287         ARM_SAVE(ARM_RSTCT1);
 288         ARM_SAVE(ARM_RSTCT2);
 289         ARM_SAVE(ARM_SYSST);
 290         ULPD_SAVE(ULPD_CLOCK_CTRL);
 291         ULPD_SAVE(ULPD_STATUS_REQ);
 292
 293         /* (Step 3 removed - we now allow deep sleep by default) */
 294
 295         /*
 296          * Step 4: OMAP DSP Shutdown
 297          */
 298
 299         /* stop DSP */
 300         omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
 301
 302                 /* shut down dsp_ck */
 303         if (!cpu_is_omap7xx())
 304                 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
 305
 306         /* temporarily enabling api_ck to access DSP registers */
 307         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 308
 309         /* save DSP registers */
 310         DSP_SAVE(DSP_IDLECT2);
 311
 312         /* Stop all DSP domain clocks */
 313         __raw_writew(0, DSP_IDLECT2);
 314
 315         /*
 316          * Step 5: Wakeup Event Setup
 317          */
 318
 319         omap_pm_wakeup_setup();
 320
 321         /*
 322          * Step 6: ARM and Traffic controller shutdown
 323          */
 324
 325         /* disable ARM watchdog */
 326         omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
 327         omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
 328
 329         /*
 330          * Step 6b: ARM and Traffic controller shutdown
 331          *
 332          * Step 6 continues here. Prepare jump to power management
 333          * assembly code in internal SRAM.
 334          *
 335          * Since the omap_cpu_suspend routine has been copied to
 336          * SRAM, we'll do an indirect procedure call to it and pass the
 337          * contents of arm_idlect1 and arm_idlect2 so it can restore
 338          * them when it wakes up and it will return.
 339          */
 340
 341         arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
 342         arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
 343
 344         /*
 345          * Step 6c: ARM and Traffic controller shutdown
 346          *
 347          * Jump to assembly code. The processor will stay there
 348          * until wake up.
 349          */
 350         omap_sram_suspend(arg0, arg1);
 351
 352         /*
 353          * If we are here, processor is woken up!
 354          */
 355
 356         /*
 357          * Restore DSP clocks
 358          */
 359
 360         /* again temporarily enabling api_ck to access DSP registers */
 361         omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
 362
 363         /* Restore DSP domain clocks */
 364         DSP_RESTORE(DSP_IDLECT2);
 365
 366         /*
 367          * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
 368          */
 369
 370         if (!(cpu_is_omap15xx()))
 371                 ARM_RESTORE(ARM_IDLECT3);
 372         ARM_RESTORE(ARM_CKCTL);
 373         ARM_RESTORE(ARM_EWUPCT);
 374         ARM_RESTORE(ARM_RSTCT1);
 375         ARM_RESTORE(ARM_RSTCT2);
 376         ARM_RESTORE(ARM_SYSST);
 377         ULPD_RESTORE(ULPD_CLOCK_CTRL);
 378         ULPD_RESTORE(ULPD_STATUS_REQ);
 379
 380         if (cpu_is_omap7xx()) {
 381                 MPUI7XX_RESTORE(EMIFS_CONFIG);
 382                 MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG);
 383                 MPUI7XX_RESTORE(OMAP_IH1_MIR);
 384                 MPUI7XX_RESTORE(OMAP_IH2_0_MIR);
 385                 MPUI7XX_RESTORE(OMAP_IH2_1_MIR);
 386         } else if (cpu_is_omap15xx()) {
 387                 MPUI1510_RESTORE(MPUI_CTRL);
 388                 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
 389                 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
 390                 MPUI1510_RESTORE(EMIFS_CONFIG);
 391                 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
 392                 MPUI1510_RESTORE(OMAP_IH1_MIR);
 393                 MPUI1510_RESTORE(OMAP_IH2_MIR);
 394         } else if (cpu_is_omap16xx()) {
 395                 MPUI1610_RESTORE(MPUI_CTRL);
 396                 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
 397                 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
 398                 MPUI1610_RESTORE(EMIFS_CONFIG);
 399                 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
 400
 401                 MPUI1610_RESTORE(OMAP_IH1_MIR);
 402                 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
 403                 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
 404                 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
 405                 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
 406         }
 407
 408         if (!cpu_is_omap15xx())
 409                 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
 410
 411         /*
 412          * Re-enable interrupts
 413          */
 414
 415         local_irq_enable();
 416         local_fiq_enable();
 417
 418         omap_serial_wake_trigger(0);
 419
 420         printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
 421                 omap_rev());
 422 }
 423
 424 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 425 static int g_read_completed;
 426
 427 /*
 428  * Read system PM registers for debugging
 429  */
 430 static int omap_pm_read_proc(
 431         char *page_buffer,
 432         char **my_first_byte,
 433         off_t virtual_start,
 434         int length,
 435         int *eof,
 436         void *data)
 437 {
 438         int my_buffer_offset = 0;
 439         char * const my_base = page_buffer;
 440
 441         ARM_SAVE(ARM_CKCTL);
 442         ARM_SAVE(ARM_IDLECT1);
 443         ARM_SAVE(ARM_IDLECT2);
 444         if (!(cpu_is_omap15xx()))
 445                 ARM_SAVE(ARM_IDLECT3);
 446         ARM_SAVE(ARM_EWUPCT);
 447         ARM_SAVE(ARM_RSTCT1);
 448         ARM_SAVE(ARM_RSTCT2);
 449         ARM_SAVE(ARM_SYSST);
 450
 451         ULPD_SAVE(ULPD_IT_STATUS);
 452         ULPD_SAVE(ULPD_CLOCK_CTRL);
 453         ULPD_SAVE(ULPD_SOFT_REQ);
 454         ULPD_SAVE(ULPD_STATUS_REQ);
 455         ULPD_SAVE(ULPD_DPLL_CTRL);
 456         ULPD_SAVE(ULPD_POWER_CTRL);
 457
 458         if (cpu_is_omap7xx()) {
 459                 MPUI7XX_SAVE(MPUI_CTRL);
 460                 MPUI7XX_SAVE(MPUI_DSP_STATUS);
 461                 MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG);
 462                 MPUI7XX_SAVE(MPUI_DSP_API_CONFIG);
 463                 MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG);
 464                 MPUI7XX_SAVE(EMIFS_CONFIG);
 465         } else if (cpu_is_omap15xx()) {
 466                 MPUI1510_SAVE(MPUI_CTRL);
 467                 MPUI1510_SAVE(MPUI_DSP_STATUS);
 468                 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
 469                 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
 470                 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
 471                 MPUI1510_SAVE(EMIFS_CONFIG);
 472         } else if (cpu_is_omap16xx()) {
 473                 MPUI1610_SAVE(MPUI_CTRL);
 474                 MPUI1610_SAVE(MPUI_DSP_STATUS);
 475                 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
 476                 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
 477                 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
 478                 MPUI1610_SAVE(EMIFS_CONFIG);
 479         }
 480
 481         if (virtual_start == 0) {
 482                 g_read_completed = 0;
 483
 484                 my_buffer_offset += sprintf(my_base + my_buffer_offset,
 485                    "ARM_CKCTL_REG:            0x%-8x     \n"
 486                    "ARM_IDLECT1_REG:          0x%-8x     \n"
 487                    "ARM_IDLECT2_REG:          0x%-8x     \n"
 488                    "ARM_IDLECT3_REG:          0x%-8x     \n"
 489                    "ARM_EWUPCT_REG:           0x%-8x     \n"
 490                    "ARM_RSTCT1_REG:           0x%-8x     \n"
 491                    "ARM_RSTCT2_REG:           0x%-8x     \n"
 492                    "ARM_SYSST_REG:            0x%-8x     \n"
 493                    "ULPD_IT_STATUS_REG:       0x%-4x     \n"
 494                    "ULPD_CLOCK_CTRL_REG:      0x%-4x     \n"
 495                    "ULPD_SOFT_REQ_REG:        0x%-4x     \n"
 496                    "ULPD_DPLL_CTRL_REG:       0x%-4x     \n"
 497                    "ULPD_STATUS_REQ_REG:      0x%-4x     \n"
 498                    "ULPD_POWER_CTRL_REG:      0x%-4x     \n",
 499                    ARM_SHOW(ARM_CKCTL),
 500                    ARM_SHOW(ARM_IDLECT1),
 501                    ARM_SHOW(ARM_IDLECT2),
 502                    ARM_SHOW(ARM_IDLECT3),
 503                    ARM_SHOW(ARM_EWUPCT),
 504                    ARM_SHOW(ARM_RSTCT1),
 505                    ARM_SHOW(ARM_RSTCT2),
 506                    ARM_SHOW(ARM_SYSST),
 507                    ULPD_SHOW(ULPD_IT_STATUS),
 508                    ULPD_SHOW(ULPD_CLOCK_CTRL),
 509                    ULPD_SHOW(ULPD_SOFT_REQ),
 510                    ULPD_SHOW(ULPD_DPLL_CTRL),
 511                    ULPD_SHOW(ULPD_STATUS_REQ),
 512                    ULPD_SHOW(ULPD_POWER_CTRL));
 513
 514                 if (cpu_is_omap7xx()) {
 515                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 516                            "MPUI7XX_CTRL_REG         0x%-8x \n"
 517                            "MPUI7XX_DSP_STATUS_REG:      0x%-8x \n"
 518                            "MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 519                            "MPUI7XX_DSP_API_CONFIG_REG:  0x%-8x \n"
 520                            "MPUI7XX_SDRAM_CONFIG_REG:    0x%-8x \n"
 521                            "MPUI7XX_EMIFS_CONFIG_REG:    0x%-8x \n",
 522                            MPUI7XX_SHOW(MPUI_CTRL),
 523                            MPUI7XX_SHOW(MPUI_DSP_STATUS),
 524                            MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG),
 525                            MPUI7XX_SHOW(MPUI_DSP_API_CONFIG),
 526                            MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG),
 527                            MPUI7XX_SHOW(EMIFS_CONFIG));
 528                 } else if (cpu_is_omap15xx()) {
 529                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 530                            "MPUI1510_CTRL_REG             0x%-8x \n"
 531                            "MPUI1510_DSP_STATUS_REG:      0x%-8x \n"
 532                            "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 533                            "MPUI1510_DSP_API_CONFIG_REG:  0x%-8x \n"
 534                            "MPUI1510_SDRAM_CONFIG_REG:    0x%-8x \n"
 535                            "MPUI1510_EMIFS_CONFIG_REG:    0x%-8x \n",
 536                            MPUI1510_SHOW(MPUI_CTRL),
 537                            MPUI1510_SHOW(MPUI_DSP_STATUS),
 538                            MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
 539                            MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
 540                            MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
 541                            MPUI1510_SHOW(EMIFS_CONFIG));
 542                 } else if (cpu_is_omap16xx()) {
 543                         my_buffer_offset += sprintf(my_base + my_buffer_offset,
 544                            "MPUI1610_CTRL_REG             0x%-8x \n"
 545                            "MPUI1610_DSP_STATUS_REG:      0x%-8x \n"
 546                            "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
 547                            "MPUI1610_DSP_API_CONFIG_REG:  0x%-8x \n"
 548                            "MPUI1610_SDRAM_CONFIG_REG:    0x%-8x \n"
 549                            "MPUI1610_EMIFS_CONFIG_REG:    0x%-8x \n",
 550                            MPUI1610_SHOW(MPUI_CTRL),
 551                            MPUI1610_SHOW(MPUI_DSP_STATUS),
 552                            MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
 553                            MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
 554                            MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
 555                            MPUI1610_SHOW(EMIFS_CONFIG));
 556                 }
 557
 558                 g_read_completed++;
 559         } else if (g_read_completed >= 1) {
 560                  *eof = 1;
 561                  return 0;
 562         }
 563         g_read_completed++;
 564
 565         *my_first_byte = page_buffer;
 566         return  my_buffer_offset;
 567 }
 568
 569 static void omap_pm_init_proc(void)
 570 {
 571         struct proc_dir_entry *entry;
 572
 573         entry = create_proc_read_entry("driver/omap_pm",
 574                                        S_IWUSR | S_IRUGO, NULL,
 575                                        omap_pm_read_proc, NULL);
 576 }
 577
 578 #endif /* DEBUG && CONFIG_PROC_FS */
 579
 580 /*
 581  *      omap_pm_prepare - Do preliminary suspend work.
 582  *
 583  */
 584 static int omap_pm_prepare(void)
 585 {
 586         /* We cannot sleep in idle until we have resumed */
 587         disable_hlt();
 588
 589         return 0;
 590 }
 591
 592
 593 /*
 594  *      omap_pm_enter - Actually enter a sleep state.
 595  *      @state:         State we're entering.
 596  *
 597  */
 598
 599 static int omap_pm_enter(suspend_state_t state)
 600 {
 601         switch (state)
 602         {
 603         case PM_SUSPEND_STANDBY:
 604         case PM_SUSPEND_MEM:
 605                 omap1_pm_suspend();
 606                 break;
 607         default:
 608                 return -EINVAL;
 609         }
 610
 611         return 0;
 612 }
 613
 614
 615 /**
 616  *      omap_pm_finish - Finish up suspend sequence.
 617  *
 618  *      This is called after we wake back up (or if entering the sleep state
 619  *      failed).
 620  */
 621
 622 static void omap_pm_finish(void)
 623 {
 624         enable_hlt();
 625 }
 626
 627
 628 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
 629 {
 630         return IRQ_HANDLED;
 631 }
 632
 633 static struct irqaction omap_wakeup_irq = {
 634         .name           = "peripheral wakeup",
 635         .flags          = IRQF_DISABLED,
 636         .handler        = omap_wakeup_interrupt
 637 };
 638
 639
 640
 641 static const struct platform_suspend_ops omap_pm_ops = {
 642         .prepare        = omap_pm_prepare,
 643         .enter          = omap_pm_enter,
 644         .finish         = omap_pm_finish,
 645         .valid          = suspend_valid_only_mem,
 646 };
 647
 648 static int __init omap_pm_init(void)
 649 {
 650
 651 #ifdef CONFIG_OMAP_32K_TIMER
 652         int error;
 653 #endif
 654
 655         if (!cpu_class_is_omap1())
 656                 return -ENODEV;
 657
 658         printk("Power Management for TI OMAP.\n");
 659
 660         /*
 661          * We copy the assembler sleep/wakeup routines to SRAM.
 662          * These routines need to be in SRAM as that's the only
 663          * memory the MPU can see when it wakes up.
 664          */
 665         if (cpu_is_omap7xx()) {
 666                 omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend,
 667                                                    omap7xx_cpu_suspend_sz);
 668         } else if (cpu_is_omap15xx()) {
 669                 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
 670                                                    omap1510_cpu_suspend_sz);
 671         } else if (cpu_is_omap16xx()) {
 672                 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
 673                                                    omap1610_cpu_suspend_sz);
 674         }
 675
 676         if (omap_sram_suspend == NULL) {
 677                 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
 678                 return -ENODEV;
 679         }
 680
 681         arm_pm_idle = omap1_pm_idle;
 682
 683         if (cpu_is_omap7xx())
 684                 setup_irq(INT_7XX_WAKE_UP_REQ, &omap_wakeup_irq);
 685         else if (cpu_is_omap16xx())
 686                 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
 687
 688         /* Program new power ramp-up time
 689          * (0 for most boards since we don't lower voltage when in deep sleep)
 690          */
 691         omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
 692
 693         /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
 694         omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
 695
 696         /* Configure IDLECT3 */
 697         if (cpu_is_omap7xx())
 698                 omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3);
 699         else if (cpu_is_omap16xx())
 700                 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
 701
 702         suspend_set_ops(&omap_pm_ops);
 703
 704 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
 705         omap_pm_init_proc();
 706 #endif
 707
 708 #ifdef CONFIG_OMAP_32K_TIMER
 709         error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
 710         if (error)
 711                 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
 712 #endif
 713
 714         if (cpu_is_omap16xx()) {
 715                 /* configure LOW_PWR pin */
 716                 omap_cfg_reg(T20_1610_LOW_PWR);
 717         }
 718
 719         return 0;
 720 }
 721 __initcall(omap_pm_init);