arch/arm/mach-mxs/clock-mx23.c

   1 /*
   2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/mm.h>
  20 #include <linux/delay.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23 #include <linux/jiffies.h>
  24 #include <linux/clkdev.h>
  25
  26 #include <asm/clkdev.h>
  27 #include <asm/div64.h>
  28
  29 #include <mach/mx23.h>
  30 #include <mach/common.h>
  31 #include <mach/clock.h>
  32
  33 #include "regs-clkctrl-mx23.h"
  34
  35 #define CLKCTRL_BASE_ADDR       MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
  36 #define DIGCTRL_BASE_ADDR       MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
  37
  38 #define PARENT_RATE_SHIFT       8
  39
  40 static int _raw_clk_enable(struct clk *clk)
  41 {
  42         u32 reg;
  43
  44         if (clk->enable_reg) {
  45                 reg = __raw_readl(clk->enable_reg);
  46                 reg &= ~(1 << clk->enable_shift);
  47                 __raw_writel(reg, clk->enable_reg);
  48         }
  49
  50         return 0;
  51 }
  52
  53 static void _raw_clk_disable(struct clk *clk)
  54 {
  55         u32 reg;
  56
  57         if (clk->enable_reg) {
  58                 reg = __raw_readl(clk->enable_reg);
  59                 reg |= 1 << clk->enable_shift;
  60                 __raw_writel(reg, clk->enable_reg);
  61         }
  62 }
  63
  64 /*
  65  * ref_xtal_clk
  66  */
  67 static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
  68 {
  69         return 24000000;
  70 }
  71
  72 static struct clk ref_xtal_clk = {
  73         .get_rate = ref_xtal_clk_get_rate,
  74 };
  75
  76 /*
  77  * pll_clk
  78  */
  79 static unsigned long pll_clk_get_rate(struct clk *clk)
  80 {
  81         return 480000000;
  82 }
  83
  84 static int pll_clk_enable(struct clk *clk)
  85 {
  86         __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
  87                         BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
  88                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
  89
  90         /* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
  91          * and is incorrect (excessive). Per definition of the PLLCTRL0
  92          * POWER field, waiting at least 10us.
  93          */
  94         udelay(10);
  95
  96         return 0;
  97 }
  98
  99 static void pll_clk_disable(struct clk *clk)
 100 {
 101         __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
 102                         BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
 103                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
 104 }
 105
 106 static struct clk pll_clk = {
 107          .get_rate = pll_clk_get_rate,
 108          .enable = pll_clk_enable,
 109          .disable = pll_clk_disable,
 110          .parent = &ref_xtal_clk,
 111 };
 112
 113 /*
 114  * ref_clk
 115  */
 116 #define _CLK_GET_RATE_REF(name, sr, ss)                                 \
 117 static unsigned long name##_get_rate(struct clk *clk)                   \
 118 {                                                                       \
 119         unsigned long parent_rate;                                      \
 120         u32 reg, div;                                                   \
 121                                                                         \
 122         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr);         \
 123         div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f;             \
 124         parent_rate = clk_get_rate(clk->parent);                        \
 125                                                                         \
 126         return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18,          \
 127                         div, PARENT_RATE_SHIFT);                        \
 128 }
 129
 130 _CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
 131 _CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
 132 _CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
 133 _CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
 134
 135 #define _DEFINE_CLOCK_REF(name, er, es)                                 \
 136         static struct clk name = {                                      \
 137                 .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
 138                 .enable_shift   = BP_CLKCTRL_##er##_CLKGATE##es,        \
 139                 .get_rate       = name##_get_rate,                      \
 140                 .enable         = _raw_clk_enable,                      \
 141                 .disable        = _raw_clk_disable,                     \
 142                 .parent         = &pll_clk,                             \
 143         }
 144
 145 _DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
 146 _DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
 147 _DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
 148 _DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
 149
 150 /*
 151  * General clocks
 152  *
 153  * clk_get_rate
 154  */
 155 static unsigned long rtc_clk_get_rate(struct clk *clk)
 156 {
 157         /* ref_xtal_clk is implemented as the only parent */
 158         return clk_get_rate(clk->parent) / 768;
 159 }
 160
 161 static unsigned long clk32k_clk_get_rate(struct clk *clk)
 162 {
 163         return clk->parent->get_rate(clk->parent) / 750;
 164 }
 165
 166 #define _CLK_GET_RATE(name, rs)                                         \
 167 static unsigned long name##_get_rate(struct clk *clk)                   \
 168 {                                                                       \
 169         u32 reg, div;                                                   \
 170                                                                         \
 171         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
 172                                                                         \
 173         if (clk->parent == &ref_xtal_clk)                               \
 174                 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >>             \
 175                         BP_CLKCTRL_##rs##_DIV_XTAL;                     \
 176         else                                                            \
 177                 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >>             \
 178                         BP_CLKCTRL_##rs##_DIV_##rs;                     \
 179                                                                         \
 180         if (!div)                                                       \
 181                 return -EINVAL;                                         \
 182                                                                         \
 183         return clk_get_rate(clk->parent) / div;                         \
 184 }
 185
 186 _CLK_GET_RATE(cpu_clk, CPU)
 187 _CLK_GET_RATE(emi_clk, EMI)
 188
 189 #define _CLK_GET_RATE1(name, rs)                                        \
 190 static unsigned long name##_get_rate(struct clk *clk)                   \
 191 {                                                                       \
 192         u32 reg, div;                                                   \
 193                                                                         \
 194         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs);         \
 195         div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV;   \
 196                                                                         \
 197         if (!div)                                                       \
 198                 return -EINVAL;                                         \
 199                                                                         \
 200         return clk_get_rate(clk->parent) / div;                         \
 201 }
 202
 203 _CLK_GET_RATE1(hbus_clk, HBUS)
 204 _CLK_GET_RATE1(xbus_clk, XBUS)
 205 _CLK_GET_RATE1(ssp_clk, SSP)
 206 _CLK_GET_RATE1(gpmi_clk, GPMI)
 207 _CLK_GET_RATE1(lcdif_clk, PIX)
 208
 209 #define _CLK_GET_RATE_STUB(name)                                        \
 210 static unsigned long name##_get_rate(struct clk *clk)                   \
 211 {                                                                       \
 212         return clk_get_rate(clk->parent);                               \
 213 }
 214
 215 _CLK_GET_RATE_STUB(uart_clk)
 216 _CLK_GET_RATE_STUB(audio_clk)
 217 _CLK_GET_RATE_STUB(pwm_clk)
 218
 219 /*
 220  * clk_set_rate
 221  */
 222 static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
 223 {
 224         u32 reg, bm_busy, div_max, d, f, div, frac;
 225         unsigned long diff, parent_rate, calc_rate;
 226
 227         parent_rate = clk_get_rate(clk->parent);
 228
 229         if (clk->parent == &ref_xtal_clk) {
 230                 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
 231                 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
 232                 div = DIV_ROUND_UP(parent_rate, rate);
 233                 if (div == 0 || div > div_max)
 234                         return -EINVAL;
 235         } else {
 236                 div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
 237                 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
 238                 rate >>= PARENT_RATE_SHIFT;
 239                 parent_rate >>= PARENT_RATE_SHIFT;
 240                 diff = parent_rate;
 241                 div = frac = 1;
 242                 for (d = 1; d <= div_max; d++) {
 243                         f = parent_rate * 18 / d / rate;
 244                         if ((parent_rate * 18 / d) % rate)
 245                                 f++;
 246                         if (f < 18 || f > 35)
 247                                 continue;
 248
 249                         calc_rate = parent_rate * 18 / f / d;
 250                         if (calc_rate > rate)
 251                                 continue;
 252
 253                         if (rate - calc_rate < diff) {
 254                                 frac = f;
 255                                 div = d;
 256                                 diff = rate - calc_rate;
 257                         }
 258
 259                         if (diff == 0)
 260                                 break;
 261                 }
 262
 263                 if (diff == parent_rate)
 264                         return -EINVAL;
 265
 266                 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
 267                 reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
 268                 reg |= frac;
 269                 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
 270         }
 271
 272         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
 273         reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
 274         reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
 275         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
 276
 277         mxs_clkctrl_timeout(HW_CLKCTRL_CPU, bm_busy);
 278
 279         return 0;
 280 }
 281
 282 #define _CLK_SET_RATE(name, dr)                                         \
 283 static int name##_set_rate(struct clk *clk, unsigned long rate)         \
 284 {                                                                       \
 285         u32 reg, div_max, div;                                          \
 286         unsigned long parent_rate;                                      \
 287                                                                         \
 288         parent_rate = clk_get_rate(clk->parent);                        \
 289         div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
 290                                                                         \
 291         div = DIV_ROUND_UP(parent_rate, rate);                          \
 292         if (div == 0 || div > div_max)                                  \
 293                 return -EINVAL;                                         \
 294                                                                         \
 295         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
 296         reg &= ~BM_CLKCTRL_##dr##_DIV;                                  \
 297         reg |= div << BP_CLKCTRL_##dr##_DIV;                            \
 298         if (reg & (1 << clk->enable_shift)) {                           \
 299                 pr_err("%s: clock is gated\n", __func__);               \
 300                 return -EINVAL;                                         \
 301         }                                                               \
 302         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr);         \
 303                                                                         \
 304         mxs_clkctrl_timeout(HW_CLKCTRL_##dr, BM_CLKCTRL_##dr##_BUSY);   \
 305         return 0;                                                       \
 306 }
 307
 308 _CLK_SET_RATE(xbus_clk, XBUS)
 309 _CLK_SET_RATE(ssp_clk, SSP)
 310 _CLK_SET_RATE(gpmi_clk, GPMI)
 311 _CLK_SET_RATE(lcdif_clk, PIX)
 312
 313 #define _CLK_SET_RATE_STUB(name)                                        \
 314 static int name##_set_rate(struct clk *clk, unsigned long rate)         \
 315 {                                                                       \
 316         return -EINVAL;                                                 \
 317 }
 318
 319 _CLK_SET_RATE_STUB(emi_clk)
 320 _CLK_SET_RATE_STUB(uart_clk)
 321 _CLK_SET_RATE_STUB(audio_clk)
 322 _CLK_SET_RATE_STUB(pwm_clk)
 323 _CLK_SET_RATE_STUB(clk32k_clk)
 324
 325 /*
 326  * clk_set_parent
 327  */
 328 #define _CLK_SET_PARENT(name, bit)                                      \
 329 static int name##_set_parent(struct clk *clk, struct clk *parent)       \
 330 {                                                                       \
 331         if (parent != clk->parent) {                                    \
 332                 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit,            \
 333                          CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG);    \
 334                 clk->parent = parent;                                   \
 335         }                                                               \
 336                                                                         \
 337         return 0;                                                       \
 338 }
 339
 340 _CLK_SET_PARENT(cpu_clk, CPU)
 341 _CLK_SET_PARENT(emi_clk, EMI)
 342 _CLK_SET_PARENT(ssp_clk, SSP)
 343 _CLK_SET_PARENT(gpmi_clk, GPMI)
 344 _CLK_SET_PARENT(lcdif_clk, PIX)
 345
 346 #define _CLK_SET_PARENT_STUB(name)                                      \
 347 static int name##_set_parent(struct clk *clk, struct clk *parent)       \
 348 {                                                                       \
 349         if (parent != clk->parent)                                      \
 350                 return -EINVAL;                                         \
 351         else                                                            \
 352                 return 0;                                               \
 353 }
 354
 355 _CLK_SET_PARENT_STUB(uart_clk)
 356 _CLK_SET_PARENT_STUB(audio_clk)
 357 _CLK_SET_PARENT_STUB(pwm_clk)
 358 _CLK_SET_PARENT_STUB(clk32k_clk)
 359
 360 /*
 361  * clk definition
 362  */
 363 static struct clk cpu_clk = {
 364         .get_rate = cpu_clk_get_rate,
 365         .set_rate = cpu_clk_set_rate,
 366         .set_parent = cpu_clk_set_parent,
 367         .parent = &ref_cpu_clk,
 368 };
 369
 370 static struct clk hbus_clk = {
 371         .get_rate = hbus_clk_get_rate,
 372         .parent = &cpu_clk,
 373 };
 374
 375 static struct clk xbus_clk = {
 376         .get_rate = xbus_clk_get_rate,
 377         .set_rate = xbus_clk_set_rate,
 378         .parent = &ref_xtal_clk,
 379 };
 380
 381 static struct clk rtc_clk = {
 382         .get_rate = rtc_clk_get_rate,
 383         .parent = &ref_xtal_clk,
 384 };
 385
 386 /* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
 387 static struct clk usb_clk = {
 388         .enable_reg = DIGCTRL_BASE_ADDR,
 389         .enable_shift = 2,
 390         .enable = _raw_clk_enable,
 391         .disable = _raw_clk_disable,
 392         .parent = &pll_clk,
 393 };
 394
 395 #define _DEFINE_CLOCK(name, er, es, p)                                  \
 396         static struct clk name = {                                      \
 397                 .enable_reg     = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er,  \
 398                 .enable_shift   = BP_CLKCTRL_##er##_##es,               \
 399                 .get_rate       = name##_get_rate,                      \
 400                 .set_rate       = name##_set_rate,                      \
 401                 .set_parent     = name##_set_parent,                    \
 402                 .enable         = _raw_clk_enable,                      \
 403                 .disable        = _raw_clk_disable,                     \
 404                 .parent         = p,                                    \
 405         }
 406
 407 _DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
 408 _DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
 409 _DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
 410 _DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
 411 _DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
 412 _DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
 413 _DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
 414 _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
 415
 416 #define _REGISTER_CLOCK(d, n, c) \
 417         { \
 418                 .dev_id = d, \
 419                 .con_id = n, \
 420                 .clk = &c, \
 421         },
 422
 423 static struct clk_lookup lookups[] = {
 424         /* for amba bus driver */
 425         _REGISTER_CLOCK("duart", "apb_pclk", xbus_clk)
 426         /* for amba-pl011 driver */
 427         _REGISTER_CLOCK("duart", NULL, uart_clk)
 428         _REGISTER_CLOCK("mxs-auart.0", NULL, uart_clk)
 429         _REGISTER_CLOCK("rtc", NULL, rtc_clk)
 430         _REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
 431         _REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
 432         _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk)
 433         _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk)
 434         _REGISTER_CLOCK(NULL, "usb", usb_clk)
 435         _REGISTER_CLOCK(NULL, "audio", audio_clk)
 436         _REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
 437         _REGISTER_CLOCK("mxs-pwm.1", NULL, pwm_clk)
 438         _REGISTER_CLOCK("mxs-pwm.2", NULL, pwm_clk)
 439         _REGISTER_CLOCK("mxs-pwm.3", NULL, pwm_clk)
 440         _REGISTER_CLOCK("mxs-pwm.4", NULL, pwm_clk)
 441         _REGISTER_CLOCK("imx23-fb", NULL, lcdif_clk)
 442         _REGISTER_CLOCK("imx23-gpmi-nand", NULL, gpmi_clk)
 443 };
 444
 445 static int clk_misc_init(void)
 446 {
 447         u32 reg;
 448         int ret;
 449
 450         /* Fix up parent per register setting */
 451         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
 452         cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
 453                         &ref_xtal_clk : &ref_cpu_clk;
 454         emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
 455                         &ref_xtal_clk : &ref_emi_clk;
 456         ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
 457                         &ref_xtal_clk : &ref_io_clk;
 458         gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
 459                         &ref_xtal_clk : &ref_io_clk;
 460         lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
 461                         &ref_xtal_clk : &ref_pix_clk;
 462
 463         /* Use int div over frac when both are available */
 464         __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
 465                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
 466         __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
 467                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
 468         __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
 469                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
 470
 471         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
 472         reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
 473         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
 474
 475         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
 476         reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
 477         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
 478
 479         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
 480         reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
 481         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
 482
 483         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
 484         reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
 485         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
 486
 487         /*
 488          * Set safe hbus clock divider. A divider of 3 ensure that
 489          * the Vddd voltage required for the cpu clock is sufficiently
 490          * high for the hbus clock.
 491          */
 492         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
 493         reg &= BM_CLKCTRL_HBUS_DIV;
 494         reg |= 3 << BP_CLKCTRL_HBUS_DIV;
 495         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
 496
 497         ret = mxs_clkctrl_timeout(HW_CLKCTRL_HBUS, BM_CLKCTRL_HBUS_BUSY);
 498
 499         /* Gate off cpu clock in WFI for power saving */
 500         __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
 501                         CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
 502
 503         /*
 504          * 480 MHz seems too high to be ssp clock source directly,
 505          * so set frac to get a 288 MHz ref_io.
 506          */
 507         reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
 508         reg &= ~BM_CLKCTRL_FRAC_IOFRAC;
 509         reg |= 30 << BP_CLKCTRL_FRAC_IOFRAC;
 510         __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
 511
 512         return ret;
 513 }
 514
 515 int __init mx23_clocks_init(void)
 516 {
 517         clk_misc_init();
 518
 519         /*
 520          * source ssp clock from ref_io than ref_xtal,
 521          * as ref_xtal only provides 24 MHz as maximum.
 522          */
 523         clk_set_parent(&ssp_clk, &ref_io_clk);
 524
 525         clk_prepare_enable(&cpu_clk);
 526         clk_prepare_enable(&hbus_clk);
 527         clk_prepare_enable(&xbus_clk);
 528         clk_prepare_enable(&emi_clk);
 529         clk_prepare_enable(&uart_clk);
 530
 531         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 532
 533         mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
 534
 535         return 0;
 536 }