2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/gpio.h>
35 #include <mach/irqs.h>
36 #include <mach/hardware.h>
37 #include <mach/common.h>
43 * SPI master controller
45 * - i.MX1: 2 channel (slighly different register setting)
49 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq) \
50 static struct resource mxc_spi_resources ## n[] = { \
53 .end = baseaddr + SZ_4K - 1, \
54 .flags = IORESOURCE_MEM, \
58 .flags = IORESOURCE_IRQ, \
62 struct platform_device mxc_spi_device ## n = { \
65 .num_resources = ARRAY_SIZE(mxc_spi_resources ## n), \
66 .resource = mxc_spi_resources ## n, \
69 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
70 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
72 #ifdef CONFIG_MACH_MX27
73 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
77 * General Purpose Timer
81 #define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
82 static struct resource timer ## n ##_resources[] = { \
85 .end = baseaddr + SZ_4K - 1, \
86 .flags = IORESOURCE_MEM, \
90 .flags = IORESOURCE_IRQ, \
94 struct platform_device mxc_gpt ## n = { \
97 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
98 .resource = timer ## n ## _resources, \
101 /* We use gpt1 as system timer, so do not add a device for this one */
102 DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
103 DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
105 #ifdef CONFIG_MACH_MX27
106 DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
107 DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
108 DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
117 static struct resource mxc_wdt_resources[] = {
119 .start = MX2x_WDOG_BASE_ADDR,
120 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
121 .flags = IORESOURCE_MEM,
125 struct platform_device mxc_wdt = {
128 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
129 .resource = mxc_wdt_resources,
132 static struct resource mxc_w1_master_resources[] = {
134 .start = MX2x_OWIRE_BASE_ADDR,
135 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
136 .flags = IORESOURCE_MEM,
140 struct platform_device mxc_w1_master_device = {
143 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
144 .resource = mxc_w1_master_resources,
147 static struct resource mxc_nand_resources[] = {
149 .start = NFC_BASE_ADDR,
150 .end = NFC_BASE_ADDR + SZ_4K - 1,
151 .flags = IORESOURCE_MEM,
153 .start = MX2x_INT_NANDFC,
154 .end = MX2x_INT_NANDFC,
155 .flags = IORESOURCE_IRQ,
159 struct platform_device mxc_nand_device = {
162 .num_resources = ARRAY_SIZE(mxc_nand_resources),
163 .resource = mxc_nand_resources,
168 * - i.MX1: the basic controller
169 * - i.MX21: to be checked
170 * - i.MX27: like i.MX1, with slightly variations
172 static struct resource mxc_fb[] = {
174 .start = MX2x_LCDC_BASE_ADDR,
175 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
176 .flags = IORESOURCE_MEM,
178 .start = MX2x_INT_LCDC,
179 .end = MX2x_INT_LCDC,
180 .flags = IORESOURCE_IRQ,
185 struct platform_device mxc_fb_device = {
188 .num_resources = ARRAY_SIZE(mxc_fb),
191 .coherent_dma_mask = 0xFFFFFFFF,
195 #ifdef CONFIG_MACH_MX27
196 static struct resource mxc_fec_resources[] = {
198 .start = MX27_FEC_BASE_ADDR,
199 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
200 .flags = IORESOURCE_MEM,
202 .start = MX27_INT_FEC,
204 .flags = IORESOURCE_IRQ,
208 struct platform_device mxc_fec_device = {
211 .num_resources = ARRAY_SIZE(mxc_fec_resources),
212 .resource = mxc_fec_resources,
216 #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq) \
217 static struct resource mxc_i2c_resources ## n[] = { \
220 .end = baseaddr + SZ_4K - 1, \
221 .flags = IORESOURCE_MEM, \
225 .flags = IORESOURCE_IRQ, \
229 struct platform_device mxc_i2c_device ## n = { \
232 .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n), \
233 .resource = mxc_i2c_resources ## n, \
236 DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
238 #ifdef CONFIG_MACH_MX27
239 DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
242 static struct resource mxc_pwm_resources[] = {
244 .start = MX2x_PWM_BASE_ADDR,
245 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
246 .flags = IORESOURCE_MEM,
248 .start = MX2x_INT_PWM,
250 .flags = IORESOURCE_IRQ,
254 struct platform_device mxc_pwm_device = {
257 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
258 .resource = mxc_pwm_resources,
262 * Resource definition for the MXC SDHC
264 #define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
265 static struct resource mxc_sdhc_resources ## n[] = { \
268 .end = baseaddr + SZ_4K - 1, \
269 .flags = IORESOURCE_MEM, \
273 .flags = IORESOURCE_IRQ, \
277 .flags = IORESOURCE_DMA, \
281 static u64 mxc_sdhc ## n ## _dmamask = 0xffffffffUL; \
283 struct platform_device mxc_sdhc_device ## n = { \
287 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
288 .coherent_dma_mask = 0xffffffff, \
290 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
291 .resource = mxc_sdhc_resources ## n, \
294 DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
295 DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
297 #ifdef CONFIG_MACH_MX27
298 static struct resource otg_resources[] = {
300 .start = MX27_USBOTG_BASE_ADDR,
301 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
302 .flags = IORESOURCE_MEM,
304 .start = MX27_INT_USB3,
305 .end = MX27_INT_USB3,
306 .flags = IORESOURCE_IRQ,
310 static u64 otg_dmamask = 0xffffffffUL;
312 /* OTG gadget device */
313 struct platform_device mxc_otg_udc_device = {
314 .name = "fsl-usb2-udc",
317 .dma_mask = &otg_dmamask,
318 .coherent_dma_mask = 0xffffffffUL,
320 .resource = otg_resources,
321 .num_resources = ARRAY_SIZE(otg_resources),
325 struct platform_device mxc_otg_host = {
329 .coherent_dma_mask = 0xffffffff,
330 .dma_mask = &otg_dmamask,
332 .resource = otg_resources,
333 .num_resources = ARRAY_SIZE(otg_resources),
338 static u64 usbh1_dmamask = 0xffffffffUL;
340 static struct resource mxc_usbh1_resources[] = {
342 .start = MX27_USBOTG_BASE_ADDR + 0x200,
343 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
344 .flags = IORESOURCE_MEM,
346 .start = MX27_INT_USB1,
347 .end = MX27_INT_USB1,
348 .flags = IORESOURCE_IRQ,
352 struct platform_device mxc_usbh1 = {
356 .coherent_dma_mask = 0xffffffff,
357 .dma_mask = &usbh1_dmamask,
359 .resource = mxc_usbh1_resources,
360 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
364 static u64 usbh2_dmamask = 0xffffffffUL;
366 static struct resource mxc_usbh2_resources[] = {
368 .start = MX27_USBOTG_BASE_ADDR + 0x400,
369 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
370 .flags = IORESOURCE_MEM,
372 .start = MX27_INT_USB2,
373 .end = MX27_INT_USB2,
374 .flags = IORESOURCE_IRQ,
378 struct platform_device mxc_usbh2 = {
382 .coherent_dma_mask = 0xffffffff,
383 .dma_mask = &usbh2_dmamask,
385 .resource = mxc_usbh2_resources,
386 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
390 #define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
393 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
394 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
395 .flags = IORESOURCE_DMA, \
398 #define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
399 static struct resource imx_ssi_resources ## n[] = { \
401 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
402 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
403 .flags = IORESOURCE_MEM, \
405 .start = MX2x_INT_SSI1, \
406 .end = MX2x_INT_SSI1, \
407 .flags = IORESOURCE_IRQ, \
409 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
410 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
411 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
412 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
415 struct platform_device imx_ssi_device ## n = { \
418 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
419 .resource = imx_ssi_resources ## n, \
422 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
423 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
425 /* GPIO port description */
426 static struct mxc_gpio_port imx_gpio_ports[] = {
428 .chip.label = "gpio-0",
429 .irq = MX2x_INT_GPIO,
430 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR),
431 .virtual_irq_start = MXC_GPIO_IRQ_START,
433 .chip.label = "gpio-1",
434 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x100),
435 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
437 .chip.label = "gpio-2",
438 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x200),
439 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
441 .chip.label = "gpio-3",
442 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x300),
443 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
445 .chip.label = "gpio-4",
446 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x400),
447 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
449 .chip.label = "gpio-5",
450 .base = IO_ADDRESS(MX2x_GPIO_BASE_ADDR + 0x500),
451 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
455 int __init mxc_register_gpios(void)
457 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));