2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/gpio.h>
35 #include <mach/irqs.h>
36 #include <mach/hardware.h>
37 #include <mach/common.h>
43 * SPI master controller
45 * - i.MX1: 2 channel (slighly different register setting)
49 static struct resource mxc_spi_resources0[] = {
51 .start = CSPI1_BASE_ADDR,
52 .end = CSPI1_BASE_ADDR + SZ_4K - 1,
53 .flags = IORESOURCE_MEM,
55 .start = MXC_INT_CSPI1,
57 .flags = IORESOURCE_IRQ,
61 static struct resource mxc_spi_resources1[] = {
63 .start = CSPI2_BASE_ADDR,
64 .end = CSPI2_BASE_ADDR + SZ_4K - 1,
65 .flags = IORESOURCE_MEM,
67 .start = MXC_INT_CSPI2,
69 .flags = IORESOURCE_IRQ,
73 #ifdef CONFIG_MACH_MX27
74 static struct resource mxc_spi_resources2[] = {
76 .start = CSPI3_BASE_ADDR,
77 .end = CSPI3_BASE_ADDR + SZ_4K - 1,
78 .flags = IORESOURCE_MEM,
80 .start = MXC_INT_CSPI3,
82 .flags = IORESOURCE_IRQ,
87 struct platform_device mxc_spi_device0 = {
90 .num_resources = ARRAY_SIZE(mxc_spi_resources0),
91 .resource = mxc_spi_resources0,
94 struct platform_device mxc_spi_device1 = {
97 .num_resources = ARRAY_SIZE(mxc_spi_resources1),
98 .resource = mxc_spi_resources1,
101 #ifdef CONFIG_MACH_MX27
102 struct platform_device mxc_spi_device2 = {
105 .num_resources = ARRAY_SIZE(mxc_spi_resources2),
106 .resource = mxc_spi_resources2,
111 * General Purpose Timer
116 /* We use gpt0 as system timer, so do not add a device for this one */
118 static struct resource timer1_resources[] = {
120 .start = GPT2_BASE_ADDR,
121 .end = GPT2_BASE_ADDR + 0x17,
122 .flags = IORESOURCE_MEM,
124 .start = MXC_INT_GPT2,
126 .flags = IORESOURCE_IRQ,
130 struct platform_device mxc_gpt1 = {
133 .num_resources = ARRAY_SIZE(timer1_resources),
134 .resource = timer1_resources,
137 static struct resource timer2_resources[] = {
139 .start = GPT3_BASE_ADDR,
140 .end = GPT3_BASE_ADDR + 0x17,
141 .flags = IORESOURCE_MEM,
143 .start = MXC_INT_GPT3,
145 .flags = IORESOURCE_IRQ,
149 struct platform_device mxc_gpt2 = {
152 .num_resources = ARRAY_SIZE(timer2_resources),
153 .resource = timer2_resources,
156 #ifdef CONFIG_MACH_MX27
157 static struct resource timer3_resources[] = {
159 .start = GPT4_BASE_ADDR,
160 .end = GPT4_BASE_ADDR + 0x17,
161 .flags = IORESOURCE_MEM,
163 .start = MXC_INT_GPT4,
165 .flags = IORESOURCE_IRQ,
169 struct platform_device mxc_gpt3 = {
172 .num_resources = ARRAY_SIZE(timer3_resources),
173 .resource = timer3_resources,
176 static struct resource timer4_resources[] = {
178 .start = GPT5_BASE_ADDR,
179 .end = GPT5_BASE_ADDR + 0x17,
180 .flags = IORESOURCE_MEM,
182 .start = MXC_INT_GPT5,
184 .flags = IORESOURCE_IRQ,
188 struct platform_device mxc_gpt4 = {
191 .num_resources = ARRAY_SIZE(timer4_resources),
192 .resource = timer4_resources,
195 static struct resource timer5_resources[] = {
197 .start = GPT6_BASE_ADDR,
198 .end = GPT6_BASE_ADDR + 0x17,
199 .flags = IORESOURCE_MEM,
201 .start = MXC_INT_GPT6,
203 .flags = IORESOURCE_IRQ,
207 struct platform_device mxc_gpt5 = {
210 .num_resources = ARRAY_SIZE(timer5_resources),
211 .resource = timer5_resources,
221 static struct resource mxc_wdt_resources[] = {
223 .start = WDOG_BASE_ADDR,
224 .end = WDOG_BASE_ADDR + 0x30,
225 .flags = IORESOURCE_MEM,
229 struct platform_device mxc_wdt = {
232 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
233 .resource = mxc_wdt_resources,
236 static struct resource mxc_w1_master_resources[] = {
238 .start = OWIRE_BASE_ADDR,
239 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
240 .flags = IORESOURCE_MEM,
244 struct platform_device mxc_w1_master_device = {
247 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
248 .resource = mxc_w1_master_resources,
251 static struct resource mxc_nand_resources[] = {
253 .start = NFC_BASE_ADDR,
254 .end = NFC_BASE_ADDR + 0xfff,
255 .flags = IORESOURCE_MEM,
257 .start = MXC_INT_NANDFC,
258 .end = MXC_INT_NANDFC,
259 .flags = IORESOURCE_IRQ,
263 struct platform_device mxc_nand_device = {
266 .num_resources = ARRAY_SIZE(mxc_nand_resources),
267 .resource = mxc_nand_resources,
272 * - i.MX1: the basic controller
273 * - i.MX21: to be checked
274 * - i.MX27: like i.MX1, with slightly variations
276 static struct resource mxc_fb[] = {
278 .start = LCDC_BASE_ADDR,
279 .end = LCDC_BASE_ADDR + 0xFFF,
280 .flags = IORESOURCE_MEM,
282 .start = MXC_INT_LCDC,
284 .flags = IORESOURCE_IRQ,
289 struct platform_device mxc_fb_device = {
292 .num_resources = ARRAY_SIZE(mxc_fb),
295 .coherent_dma_mask = 0xFFFFFFFF,
299 #ifdef CONFIG_MACH_MX27
300 static struct resource mxc_fec_resources[] = {
302 .start = FEC_BASE_ADDR,
303 .end = FEC_BASE_ADDR + 0xfff,
304 .flags = IORESOURCE_MEM,
306 .start = MXC_INT_FEC,
308 .flags = IORESOURCE_IRQ,
312 struct platform_device mxc_fec_device = {
315 .num_resources = ARRAY_SIZE(mxc_fec_resources),
316 .resource = mxc_fec_resources,
320 static struct resource mxc_i2c_1_resources[] = {
322 .start = I2C_BASE_ADDR,
323 .end = I2C_BASE_ADDR + 0x0fff,
324 .flags = IORESOURCE_MEM,
326 .start = MXC_INT_I2C,
328 .flags = IORESOURCE_IRQ,
332 struct platform_device mxc_i2c_device0 = {
335 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
336 .resource = mxc_i2c_1_resources,
339 #ifdef CONFIG_MACH_MX27
340 static struct resource mxc_i2c_2_resources[] = {
342 .start = I2C2_BASE_ADDR,
343 .end = I2C2_BASE_ADDR + 0x0fff,
344 .flags = IORESOURCE_MEM,
346 .start = MXC_INT_I2C2,
348 .flags = IORESOURCE_IRQ,
352 struct platform_device mxc_i2c_device1 = {
355 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
356 .resource = mxc_i2c_2_resources,
360 static struct resource mxc_pwm_resources[] = {
362 .start = PWM_BASE_ADDR,
363 .end = PWM_BASE_ADDR + 0x0fff,
364 .flags = IORESOURCE_MEM,
366 .start = MXC_INT_PWM,
368 .flags = IORESOURCE_IRQ,
372 struct platform_device mxc_pwm_device = {
375 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
376 .resource = mxc_pwm_resources,
380 * Resource definition for the MXC SDHC
382 static struct resource mxc_sdhc1_resources[] = {
384 .start = SDHC1_BASE_ADDR,
385 .end = SDHC1_BASE_ADDR + SZ_4K - 1,
386 .flags = IORESOURCE_MEM,
388 .start = MXC_INT_SDHC1,
389 .end = MXC_INT_SDHC1,
390 .flags = IORESOURCE_IRQ,
392 .start = DMA_REQ_SDHC1,
393 .end = DMA_REQ_SDHC1,
394 .flags = IORESOURCE_DMA,
398 static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
400 struct platform_device mxc_sdhc_device0 = {
404 .dma_mask = &mxc_sdhc1_dmamask,
405 .coherent_dma_mask = 0xffffffff,
407 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
408 .resource = mxc_sdhc1_resources,
411 static struct resource mxc_sdhc2_resources[] = {
413 .start = SDHC2_BASE_ADDR,
414 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
415 .flags = IORESOURCE_MEM,
417 .start = MXC_INT_SDHC2,
418 .end = MXC_INT_SDHC2,
419 .flags = IORESOURCE_IRQ,
421 .start = DMA_REQ_SDHC2,
422 .end = DMA_REQ_SDHC2,
423 .flags = IORESOURCE_DMA,
427 static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
429 struct platform_device mxc_sdhc_device1 = {
433 .dma_mask = &mxc_sdhc2_dmamask,
434 .coherent_dma_mask = 0xffffffff,
436 .num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
437 .resource = mxc_sdhc2_resources,
440 #ifdef CONFIG_MACH_MX27
441 static struct resource otg_resources[] = {
443 .start = OTG_BASE_ADDR,
444 .end = OTG_BASE_ADDR + 0x1ff,
445 .flags = IORESOURCE_MEM,
447 .start = MXC_INT_USB3,
449 .flags = IORESOURCE_IRQ,
453 static u64 otg_dmamask = 0xffffffffUL;
455 /* OTG gadget device */
456 struct platform_device mxc_otg_udc_device = {
457 .name = "fsl-usb2-udc",
460 .dma_mask = &otg_dmamask,
461 .coherent_dma_mask = 0xffffffffUL,
463 .resource = otg_resources,
464 .num_resources = ARRAY_SIZE(otg_resources),
468 struct platform_device mxc_otg_host = {
472 .coherent_dma_mask = 0xffffffff,
473 .dma_mask = &otg_dmamask,
475 .resource = otg_resources,
476 .num_resources = ARRAY_SIZE(otg_resources),
481 static u64 usbh1_dmamask = 0xffffffffUL;
483 static struct resource mxc_usbh1_resources[] = {
485 .start = OTG_BASE_ADDR + 0x200,
486 .end = OTG_BASE_ADDR + 0x3ff,
487 .flags = IORESOURCE_MEM,
489 .start = MXC_INT_USB1,
491 .flags = IORESOURCE_IRQ,
495 struct platform_device mxc_usbh1 = {
499 .coherent_dma_mask = 0xffffffff,
500 .dma_mask = &usbh1_dmamask,
502 .resource = mxc_usbh1_resources,
503 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
507 static u64 usbh2_dmamask = 0xffffffffUL;
509 static struct resource mxc_usbh2_resources[] = {
511 .start = OTG_BASE_ADDR + 0x400,
512 .end = OTG_BASE_ADDR + 0x5ff,
513 .flags = IORESOURCE_MEM,
515 .start = MXC_INT_USB2,
517 .flags = IORESOURCE_IRQ,
521 struct platform_device mxc_usbh2 = {
525 .coherent_dma_mask = 0xffffffff,
526 .dma_mask = &usbh2_dmamask,
528 .resource = mxc_usbh2_resources,
529 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
533 static struct resource imx_ssi_resources0[] = {
535 .start = SSI1_BASE_ADDR,
536 .end = SSI1_BASE_ADDR + 0x6F,
537 .flags = IORESOURCE_MEM,
539 .start = MXC_INT_SSI1,
541 .flags = IORESOURCE_IRQ,
544 .start = DMA_REQ_SSI1_TX0,
545 .end = DMA_REQ_SSI1_TX0,
546 .flags = IORESOURCE_DMA,
549 .start = DMA_REQ_SSI1_RX0,
550 .end = DMA_REQ_SSI1_RX0,
551 .flags = IORESOURCE_DMA,
554 .start = DMA_REQ_SSI1_TX1,
555 .end = DMA_REQ_SSI1_TX1,
556 .flags = IORESOURCE_DMA,
559 .start = DMA_REQ_SSI1_RX1,
560 .end = DMA_REQ_SSI1_RX1,
561 .flags = IORESOURCE_DMA,
565 static struct resource imx_ssi_resources1[] = {
567 .start = SSI2_BASE_ADDR,
568 .end = SSI2_BASE_ADDR + 0x6F,
569 .flags = IORESOURCE_MEM,
571 .start = MXC_INT_SSI2,
573 .flags = IORESOURCE_IRQ,
576 .start = DMA_REQ_SSI2_TX0,
577 .end = DMA_REQ_SSI2_TX0,
578 .flags = IORESOURCE_DMA,
581 .start = DMA_REQ_SSI2_RX0,
582 .end = DMA_REQ_SSI2_RX0,
583 .flags = IORESOURCE_DMA,
586 .start = DMA_REQ_SSI2_TX1,
587 .end = DMA_REQ_SSI2_TX1,
588 .flags = IORESOURCE_DMA,
591 .start = DMA_REQ_SSI2_RX1,
592 .end = DMA_REQ_SSI2_RX1,
593 .flags = IORESOURCE_DMA,
597 struct platform_device imx_ssi_device0 = {
600 .num_resources = ARRAY_SIZE(imx_ssi_resources0),
601 .resource = imx_ssi_resources0,
604 struct platform_device imx_ssi_device1 = {
607 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
608 .resource = imx_ssi_resources1,
611 /* GPIO port description */
612 static struct mxc_gpio_port imx_gpio_ports[] = {
614 .chip.label = "gpio-0",
616 .base = IO_ADDRESS(GPIO_BASE_ADDR),
617 .virtual_irq_start = MXC_GPIO_IRQ_START,
619 .chip.label = "gpio-1",
620 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
621 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
623 .chip.label = "gpio-2",
624 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
625 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
627 .chip.label = "gpio-3",
628 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
629 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
631 .chip.label = "gpio-4",
632 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
633 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
635 .chip.label = "gpio-5",
636 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
637 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
641 int __init mxc_register_gpios(void)
643 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));