2 * ID and revision information for mvebu SoCs
4 * Copyright (C) 2014 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
12 * All the mvebu SoCs have information related to their variant and
13 * revision that can be read from the PCI control register. This is
14 * done before the PCI initialization to avoid any conflict. Once the
15 * ID and revision are retrieved, the mapping is freed.
18 #define pr_fmt(fmt) "mvebu-soc-id: " fmt
20 #include <linux/clk.h>
21 #include <linux/init.h>
23 #include <linux/kernel.h>
25 #include <linux/of_address.h>
26 #include "mvebu-soc-id.h"
28 #define PCIE_DEV_ID_OFF 0x0
29 #define PCIE_DEV_REV_OFF 0x8
31 #define SOC_ID_MASK 0xFFFF0000
32 #define SOC_REV_MASK 0xFF
34 static u32 soc_dev_id;
36 static bool is_id_valid;
38 static const struct of_device_id mvebu_pcie_of_match_table[] = {
39 { .compatible = "marvell,armada-xp-pcie", },
40 { .compatible = "marvell,armada-370-pcie", },
41 { .compatible = "marvell,kirkwood-pcie" },
45 int mvebu_get_soc_id(u32 *dev, u32 *rev)
55 static int __init mvebu_soc_id_init(void)
57 struct device_node *np;
59 void __iomem *pci_base;
61 struct device_node *child;
63 np = of_find_matching_node(NULL, mvebu_pcie_of_match_table);
68 * ID and revision are available from any port, so we
69 * just pick the first one
71 child = of_get_next_child(np, NULL);
73 pr_err("cannot get pci node\n");
78 clk = of_clk_get_by_name(child, NULL);
80 pr_err("cannot get clock\n");
85 ret = clk_prepare_enable(clk);
87 pr_err("cannot enable clock\n");
91 pci_base = of_iomap(child, 0);
92 if (pci_base == NULL) {
93 pr_err("cannot map registers\n");
99 soc_dev_id = readl(pci_base + PCIE_DEV_ID_OFF) >> 16;
102 soc_rev = readl(pci_base + PCIE_DEV_REV_OFF) & SOC_REV_MASK;
106 pr_info("MVEBU SoC ID=0x%X, Rev=0x%X\n", soc_dev_id, soc_rev);
112 * If the PCIe unit is actually enabled and we have PCI
113 * support in the kernel, we intentionally do not release the
114 * reference to the clock. We want to keep it running since
115 * the bootloader does some PCIe link configuration that the
116 * kernel is for now unable to do, and gating the clock would
117 * make us loose this precious configuration.
119 if (!of_device_is_available(child) || !IS_ENABLED(CONFIG_PCI_MVEBU)) {
120 clk_disable_unprepare(clk);
130 core_initcall(mvebu_soc_id_init);