2 * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
4 * Copyright (C) 2012 Marvell
6 * Yehuda Yitschak <yehuday@marvell.com>
7 * Gregory Clement <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * The Armada 370 and Armada XP SOCs have a coherency fabric which is
15 * responsible for ensuring hardware coherency between all CPUs and between
16 * CPUs and I/O masters. This file initializes the coherency fabric and
17 * supplies basic routines for configuring and controlling hardware coherency
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/of_address.h>
24 #include <linux/smp.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <asm/smp_plat.h>
28 #include <asm/cacheflush.h>
29 #include "armada-370-xp.h"
30 #include "coherency.h"
32 unsigned long coherency_phys_base;
33 static void __iomem *coherency_base;
34 static void __iomem *coherency_cpu_base;
36 /* Coherency fabric registers */
37 #define COHERENCY_FABRIC_CFG_OFFSET 0x4
39 #define IO_SYNC_BARRIER_CTL_OFFSET 0x0
42 COHERENCY_FABRIC_TYPE_NONE,
43 COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
46 static struct of_device_id of_coherency_table[] = {
47 {.compatible = "marvell,coherency-fabric",
48 .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
49 { /* end of list */ },
52 /* Function defined in coherency_ll.S */
53 int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
55 int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id)
57 if (!coherency_base) {
58 pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id);
59 pr_warn("Coherency fabric is not initialized\n");
63 return ll_set_cpu_coherent(coherency_base, hw_cpu_id);
66 static inline void mvebu_hwcc_sync_io_barrier(void)
68 writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
69 while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
72 static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page,
73 unsigned long offset, size_t size,
74 enum dma_data_direction dir,
75 struct dma_attrs *attrs)
77 if (dir != DMA_TO_DEVICE)
78 mvebu_hwcc_sync_io_barrier();
79 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
83 static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
84 size_t size, enum dma_data_direction dir,
85 struct dma_attrs *attrs)
87 if (dir != DMA_TO_DEVICE)
88 mvebu_hwcc_sync_io_barrier();
91 static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
92 size_t size, enum dma_data_direction dir)
94 if (dir != DMA_TO_DEVICE)
95 mvebu_hwcc_sync_io_barrier();
98 static struct dma_map_ops mvebu_hwcc_dma_ops = {
99 .alloc = arm_dma_alloc,
100 .free = arm_dma_free,
101 .mmap = arm_dma_mmap,
102 .map_page = mvebu_hwcc_dma_map_page,
103 .unmap_page = mvebu_hwcc_dma_unmap_page,
104 .get_sgtable = arm_dma_get_sgtable,
105 .map_sg = arm_dma_map_sg,
106 .unmap_sg = arm_dma_unmap_sg,
107 .sync_single_for_cpu = mvebu_hwcc_dma_sync,
108 .sync_single_for_device = mvebu_hwcc_dma_sync,
109 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
110 .sync_sg_for_device = arm_dma_sync_sg_for_device,
111 .set_dma_mask = arm_dma_set_mask,
114 static int mvebu_hwcc_platform_notifier(struct notifier_block *nb,
115 unsigned long event, void *__dev)
117 struct device *dev = __dev;
119 if (event != BUS_NOTIFY_ADD_DEVICE)
121 set_dma_ops(dev, &mvebu_hwcc_dma_ops);
126 static struct notifier_block mvebu_hwcc_platform_nb = {
127 .notifier_call = mvebu_hwcc_platform_notifier,
130 static void __init armada_370_coherency_init(struct device_node *np)
134 of_address_to_resource(np, 0, &res);
135 coherency_phys_base = res.start;
137 * Ensure secondary CPUs will see the updated value,
138 * which they read before they join the coherency
139 * fabric, and therefore before they are coherent with
140 * the boot CPU cache.
142 sync_cache_w(&coherency_phys_base);
143 coherency_base = of_iomap(np, 0);
144 coherency_cpu_base = of_iomap(np, 1);
145 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
148 static int coherency_type(void)
150 struct device_node *np;
151 const struct of_device_id *match;
153 np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
155 int type = (int) match->data;
157 /* Armada 370/XP coherency works in both UP and SMP */
158 if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
164 return COHERENCY_FABRIC_TYPE_NONE;
167 int coherency_available(void)
169 return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
172 int __init coherency_init(void)
174 int type = coherency_type();
175 struct device_node *np;
177 np = of_find_matching_node(NULL, of_coherency_table);
179 if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
180 armada_370_coherency_init(np);
185 static int __init coherency_late_init(void)
187 if (coherency_available())
188 bus_register_notifier(&platform_bus_type,
189 &mvebu_hwcc_platform_nb);
193 postcore_initcall(coherency_late_init);