2 * Coherency fabric (Aurora) support for Armada 370 and XP platforms.
4 * Copyright (C) 2012 Marvell
6 * Yehuda Yitschak <yehuday@marvell.com>
7 * Gregory Clement <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * The Armada 370 and Armada XP SOCs have a coherency fabric which is
15 * responsible for ensuring hardware coherency between all CPUs and between
16 * CPUs and I/O masters. This file initializes the coherency fabric and
17 * supplies basic routines for configuring and controlling hardware coherency
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/of_address.h>
24 #include <linux/smp.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <asm/smp_plat.h>
28 #include "armada-370-xp.h"
31 * Some functions in this file are called very early during SMP
32 * initialization. At that time the device tree framework is not yet
33 * ready, and it is not possible to get the register address to
34 * ioremap it. That's why the pointer below is given with an initial
35 * value matching its virtual mapping
37 static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
38 static void __iomem *coherency_cpu_base;
40 /* Coherency fabric registers */
41 #define COHERENCY_FABRIC_CFG_OFFSET 0x4
43 #define IO_SYNC_BARRIER_CTL_OFFSET 0x0
45 static struct of_device_id of_coherency_table[] = {
46 {.compatible = "marvell,coherency-fabric"},
47 { /* end of list */ },
51 int coherency_get_cpu_count(void)
55 reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
56 cnt = (reg & 0xF) + 1;
62 /* Function defined in coherency_ll.S */
63 int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
65 int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id)
67 if (!coherency_base) {
68 pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id);
69 pr_warn("Coherency fabric is not initialized\n");
73 return ll_set_cpu_coherent(coherency_base, hw_cpu_id);
76 static inline void mvebu_hwcc_sync_io_barrier(void)
78 writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
79 while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
82 static dma_addr_t mvebu_hwcc_dma_map_page(struct device *dev, struct page *page,
83 unsigned long offset, size_t size,
84 enum dma_data_direction dir,
85 struct dma_attrs *attrs)
87 if (dir != DMA_TO_DEVICE)
88 mvebu_hwcc_sync_io_barrier();
89 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
93 static void mvebu_hwcc_dma_unmap_page(struct device *dev, dma_addr_t dma_handle,
94 size_t size, enum dma_data_direction dir,
95 struct dma_attrs *attrs)
97 if (dir != DMA_TO_DEVICE)
98 mvebu_hwcc_sync_io_barrier();
101 static void mvebu_hwcc_dma_sync(struct device *dev, dma_addr_t dma_handle,
102 size_t size, enum dma_data_direction dir)
104 if (dir != DMA_TO_DEVICE)
105 mvebu_hwcc_sync_io_barrier();
108 static struct dma_map_ops mvebu_hwcc_dma_ops = {
109 .alloc = arm_dma_alloc,
110 .free = arm_dma_free,
111 .mmap = arm_dma_mmap,
112 .map_page = mvebu_hwcc_dma_map_page,
113 .unmap_page = mvebu_hwcc_dma_unmap_page,
114 .get_sgtable = arm_dma_get_sgtable,
115 .map_sg = arm_dma_map_sg,
116 .unmap_sg = arm_dma_unmap_sg,
117 .sync_single_for_cpu = mvebu_hwcc_dma_sync,
118 .sync_single_for_device = mvebu_hwcc_dma_sync,
119 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
120 .sync_sg_for_device = arm_dma_sync_sg_for_device,
121 .set_dma_mask = arm_dma_set_mask,
124 static int mvebu_hwcc_platform_notifier(struct notifier_block *nb,
125 unsigned long event, void *__dev)
127 struct device *dev = __dev;
129 if (event != BUS_NOTIFY_ADD_DEVICE)
131 set_dma_ops(dev, &mvebu_hwcc_dma_ops);
136 static struct notifier_block mvebu_hwcc_platform_nb = {
137 .notifier_call = mvebu_hwcc_platform_notifier,
140 int __init coherency_init(void)
142 struct device_node *np;
145 * The coherency fabric is needed:
146 * - For coherency between processors on Armada XP, so only
147 * when SMP is enabled.
148 * - For coherency between the processor and I/O devices, but
149 * this coherency requires many pre-requisites (write
150 * allocate cache policy, shareable pages, SMP bit set) that
151 * are only meant in SMP situations.
153 * Note that this means that on Armada 370, there is currently
154 * no way to use hardware I/O coherency, because even when
155 * CONFIG_SMP is enabled, is_smp() returns false due to the
156 * Armada 370 being a single-core processor. To lift this
157 * limitation, we would have to find a way to make the cache
158 * policy set to write-allocate (on all Armada SoCs), and to
159 * set the shareable attribute in page tables (on all Armada
160 * SoCs except the Armada 370). Unfortunately, such decisions
161 * are taken very early in the kernel boot process, at a point
162 * where we don't know yet on which SoC we are running.
167 np = of_find_matching_node(NULL, of_coherency_table);
169 pr_info("Initializing Coherency fabric\n");
170 coherency_base = of_iomap(np, 0);
171 coherency_cpu_base = of_iomap(np, 1);
172 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
173 bus_register_notifier(&platform_bus_type,
174 &mvebu_hwcc_platform_nb);