2 * arch/arm/mach-mv78xx0/common.c
4 * Core functions for Marvell MV78xx0 SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/ata_platform.h>
16 #include <linux/clk-provider.h>
17 #include <linux/ethtool.h>
18 #include <asm/mach/map.h>
19 #include <asm/mach/time.h>
20 #include <mach/mv78xx0.h>
21 #include <mach/bridge-regs.h>
22 #include <plat/cache-feroceon-l2.h>
23 #include <plat/ehci-orion.h>
24 #include <plat/orion_nand.h>
25 #include <plat/time.h>
26 #include <plat/common.h>
27 #include <plat/addr-map.h>
30 static int get_tclk(void);
32 /*****************************************************************************
34 ****************************************************************************/
35 int mv78xx0_core_index(void)
40 * Read Extra Features register.
42 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
44 return !!(extra & 0x00004000);
47 static int get_hclk(void)
52 * HCLK tick rate is configured by DEV_D[7:5] pins.
54 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
71 panic("unknown HCLK PLL setting: %.8x\n",
72 readl(SAMPLE_AT_RESET_LOW));
78 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
83 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
84 * PCLK/L2CLK by bits [19:14].
86 if (core_index == 0) {
87 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
89 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
93 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
94 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
96 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
99 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
102 *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
105 static int get_tclk(void)
110 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
112 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
114 tclk_freq = 166666667;
117 tclk_freq = 200000000;
120 panic("unknown TCLK PLL setting: %.8x\n",
121 readl(SAMPLE_AT_RESET_HIGH));
128 /*****************************************************************************
129 * I/O Address Mapping
130 ****************************************************************************/
131 static struct map_desc mv78xx0_io_desc[] __initdata = {
133 .virtual = MV78XX0_CORE_REGS_VIRT_BASE,
135 .length = MV78XX0_CORE_REGS_SIZE,
138 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
139 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
140 .length = MV78XX0_PCIE_IO_SIZE * 8,
143 .virtual = MV78XX0_REGS_VIRT_BASE,
144 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
145 .length = MV78XX0_REGS_SIZE,
150 void __init mv78xx0_map_io(void)
155 * Map the right set of per-core registers depending on
156 * which core we are running on.
158 if (mv78xx0_core_index() == 0) {
159 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
161 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
163 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
165 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
169 /*****************************************************************************
171 ****************************************************************************/
172 static struct clk *tclk;
174 static void __init clk_init(void)
176 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
179 orion_clkdev_init(tclk);
182 /*****************************************************************************
184 ****************************************************************************/
185 void __init mv78xx0_ehci0_init(void)
187 orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA);
191 /*****************************************************************************
193 ****************************************************************************/
194 void __init mv78xx0_ehci1_init(void)
196 orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
200 /*****************************************************************************
202 ****************************************************************************/
203 void __init mv78xx0_ehci2_init(void)
205 orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
209 /*****************************************************************************
211 ****************************************************************************/
212 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
214 orion_ge00_init(eth_data,
215 GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
217 MV643XX_TX_CSUM_DEFAULT_LIMIT);
221 /*****************************************************************************
223 ****************************************************************************/
224 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
226 orion_ge01_init(eth_data,
227 GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
229 MV643XX_TX_CSUM_DEFAULT_LIMIT);
233 /*****************************************************************************
235 ****************************************************************************/
236 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
241 * On the Z0, ge10 and ge11 are internally connected back
242 * to back, and not brought out.
244 mv78xx0_pcie_id(&dev, &rev);
245 if (dev == MV78X00_Z0_DEV_ID) {
246 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
247 eth_data->speed = SPEED_1000;
248 eth_data->duplex = DUPLEX_FULL;
251 orion_ge10_init(eth_data,
252 GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
257 /*****************************************************************************
259 ****************************************************************************/
260 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
265 * On the Z0, ge10 and ge11 are internally connected back
266 * to back, and not brought out.
268 mv78xx0_pcie_id(&dev, &rev);
269 if (dev == MV78X00_Z0_DEV_ID) {
270 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
271 eth_data->speed = SPEED_1000;
272 eth_data->duplex = DUPLEX_FULL;
275 orion_ge11_init(eth_data,
276 GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
280 /*****************************************************************************
282 ****************************************************************************/
283 void __init mv78xx0_i2c_init(void)
285 orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
286 orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
289 /*****************************************************************************
291 ****************************************************************************/
292 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
294 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
298 /*****************************************************************************
300 ****************************************************************************/
301 void __init mv78xx0_uart0_init(void)
303 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
304 IRQ_MV78XX0_UART_0, tclk);
308 /*****************************************************************************
310 ****************************************************************************/
311 void __init mv78xx0_uart1_init(void)
313 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
314 IRQ_MV78XX0_UART_1, tclk);
318 /*****************************************************************************
320 ****************************************************************************/
321 void __init mv78xx0_uart2_init(void)
323 orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
324 IRQ_MV78XX0_UART_2, tclk);
327 /*****************************************************************************
329 ****************************************************************************/
330 void __init mv78xx0_uart3_init(void)
332 orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
333 IRQ_MV78XX0_UART_3, tclk);
336 /*****************************************************************************
338 ****************************************************************************/
339 void __init mv78xx0_init_early(void)
341 orion_time_set_base(TIMER_VIRT_BASE);
344 static void mv78xx0_timer_init(void)
346 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
347 IRQ_MV78XX0_TIMER_1, get_tclk());
350 struct sys_timer mv78xx0_timer = {
351 .init = mv78xx0_timer_init,
355 /*****************************************************************************
357 ****************************************************************************/
358 static char * __init mv78xx0_id(void)
362 mv78xx0_pcie_id(&dev, &rev);
364 if (dev == MV78X00_Z0_DEV_ID) {
365 if (rev == MV78X00_REV_Z0)
368 return "MV78X00-Rev-Unsupported";
369 } else if (dev == MV78100_DEV_ID) {
370 if (rev == MV78100_REV_A0)
372 else if (rev == MV78100_REV_A1)
375 return "MV78100-Rev-Unsupported";
376 } else if (dev == MV78200_DEV_ID) {
377 if (rev == MV78100_REV_A0)
380 return "MV78200-Rev-Unsupported";
382 return "Device-Unknown";
386 static int __init is_l2_writethrough(void)
388 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
391 void __init mv78xx0_init(void)
398 core_index = mv78xx0_core_index();
400 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
402 printk(KERN_INFO "%s ", mv78xx0_id());
403 printk("core #%d, ", core_index);
404 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
405 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
406 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
407 printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
409 mv78xx0_setup_cpu_mbus();
411 #ifdef CONFIG_CACHE_FEROCEON_L2
412 feroceon_l2_init(is_l2_writethrough());
415 /* Setup root of clk tree */
419 void mv78xx0_restart(char mode, const char *cmd)
422 * Enable soft reset to assert RSTOUTn.
424 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
429 writel(SOFT_RESET, SYSTEM_SOFT_RESET);