3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/clocksource.h>
18 #include <linux/clockchips.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <asm/mach/time.h>
28 #include <asm/localtimer.h>
29 #include <asm/sched_clock.h>
33 #define TIMER_MATCH_VAL 0x0000
34 #define TIMER_COUNT_VAL 0x0004
35 #define TIMER_ENABLE 0x0008
36 #define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
37 #define TIMER_ENABLE_EN BIT(0)
38 #define TIMER_CLEAR 0x000C
39 #define DGT_CLK_CTL_DIV_4 0x3
43 #define MSM_DGT_SHIFT 5
45 static void __iomem *event_base;
47 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
49 struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
50 /* Stop the timer tick */
51 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
52 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
53 ctrl &= ~TIMER_ENABLE_EN;
54 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
56 evt->event_handler(evt);
60 static int msm_timer_set_next_event(unsigned long cycles,
61 struct clock_event_device *evt)
63 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
65 writel_relaxed(0, event_base + TIMER_CLEAR);
66 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
67 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
71 static void msm_timer_set_mode(enum clock_event_mode mode,
72 struct clock_event_device *evt)
76 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
77 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
80 case CLOCK_EVT_MODE_RESUME:
81 case CLOCK_EVT_MODE_PERIODIC:
83 case CLOCK_EVT_MODE_ONESHOT:
84 /* Timer is enabled in set_next_event */
86 case CLOCK_EVT_MODE_UNUSED:
87 case CLOCK_EVT_MODE_SHUTDOWN:
90 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
93 static struct clock_event_device msm_clockevent = {
95 .features = CLOCK_EVT_FEAT_ONESHOT,
97 .set_next_event = msm_timer_set_next_event,
98 .set_mode = msm_timer_set_mode,
102 struct clock_event_device *evt;
103 struct clock_event_device * __percpu *percpu_evt;
106 static void __iomem *source_base;
108 static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
110 return readl_relaxed(source_base + TIMER_COUNT_VAL);
113 static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
116 * Shift timer count down by a constant due to unreliable lower bits
119 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
122 static struct clocksource msm_clocksource = {
125 .read = msm_read_timer_count,
126 .mask = CLOCKSOURCE_MASK(32),
127 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
130 #ifdef CONFIG_LOCAL_TIMERS
131 static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
133 /* Use existing clock_event for cpu 0 */
134 if (!smp_processor_id())
137 writel_relaxed(0, event_base + TIMER_ENABLE);
138 writel_relaxed(0, event_base + TIMER_CLEAR);
139 writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
140 evt->irq = msm_clockevent.irq;
141 evt->name = "local_timer";
142 evt->features = msm_clockevent.features;
143 evt->rating = msm_clockevent.rating;
144 evt->set_mode = msm_timer_set_mode;
145 evt->set_next_event = msm_timer_set_next_event;
147 *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
148 clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
149 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
153 static void msm_local_timer_stop(struct clock_event_device *evt)
155 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
156 disable_percpu_irq(evt->irq);
159 static struct local_timer_ops msm_local_timer_ops __cpuinitdata = {
160 .setup = msm_local_timer_setup,
161 .stop = msm_local_timer_stop,
163 #endif /* CONFIG_LOCAL_TIMERS */
165 static notrace u32 msm_sched_clock_read(void)
167 return msm_clocksource.read(&msm_clocksource);
170 static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
173 struct clock_event_device *ce = &msm_clockevent;
174 struct clocksource *cs = &msm_clocksource;
177 writel_relaxed(0, event_base + TIMER_ENABLE);
178 writel_relaxed(0, event_base + TIMER_CLEAR);
179 writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
180 ce->cpumask = cpumask_of(0);
183 clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
185 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
186 if (!msm_evt.percpu_evt) {
187 pr_err("memory allocation failed for %s\n", ce->name);
190 *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
191 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
192 ce->name, msm_evt.percpu_evt);
194 enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
195 #ifdef CONFIG_LOCAL_TIMERS
196 local_timer_register(&msm_local_timer_ops);
201 res = request_irq(ce->irq, msm_timer_interrupt,
202 IRQF_TIMER | IRQF_NOBALANCING |
203 IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
207 pr_err("request_irq failed for %s\n", ce->name);
209 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
210 res = clocksource_register_hz(cs, dgt_hz);
212 pr_err("clocksource_register failed\n");
213 setup_sched_clock(msm_sched_clock_read, sched_bits, dgt_hz);
217 static const struct of_device_id msm_dgt_match[] __initconst = {
218 { .compatible = "qcom,msm-dgt" },
222 static const struct of_device_id msm_gpt_match[] __initconst = {
223 { .compatible = "qcom,msm-gpt" },
227 void __init msm_dt_timer_init(void)
229 struct device_node *np;
234 void __iomem *dgt_clk_ctl;
236 np = of_find_matching_node(NULL, msm_gpt_match);
238 pr_err("Can't find GPT DT node\n");
242 event_base = of_iomap(np, 0);
244 pr_err("Failed to map event base\n");
248 irq = irq_of_parse_and_map(np, 0);
250 pr_err("Can't get irq\n");
255 np = of_find_matching_node(NULL, msm_dgt_match);
257 pr_err("Can't find DGT DT node\n");
261 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
264 if (of_address_to_resource(np, 0, &res)) {
265 pr_err("Failed to parse DGT resource\n");
269 source_base = ioremap(res.start + percpu_offset, resource_size(&res));
271 pr_err("Failed to map source base\n");
275 if (!of_address_to_resource(np, 1, &res)) {
276 dgt_clk_ctl = ioremap(res.start + percpu_offset,
277 resource_size(&res));
279 pr_err("Failed to map DGT control base\n");
282 writel_relaxed(DGT_CLK_CTL_DIV_4, dgt_clk_ctl);
283 iounmap(dgt_clk_ctl);
286 if (of_property_read_u32(np, "clock-frequency", &freq)) {
287 pr_err("Unknown frequency\n");
292 msm_timer_init(freq, 32, irq, !!percpu_offset);
296 static int __init msm_timer_map(phys_addr_t event, phys_addr_t source)
298 event_base = ioremap(event, SZ_64);
300 pr_err("Failed to map event base\n");
303 source_base = ioremap(source, SZ_64);
305 pr_err("Failed to map source base\n");
311 void __init msm7x01_timer_init(void)
313 struct clocksource *cs = &msm_clocksource;
315 if (msm_timer_map(0xc0100000, 0xc0100010))
317 cs->read = msm_read_timer_count_shift;
318 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
320 msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
324 void __init msm7x30_timer_init(void)
326 if (msm_timer_map(0xc0100004, 0xc0100024))
328 msm_timer_init(24576000 / 4, 32, 1, false);
331 void __init qsd8x50_timer_init(void)
333 if (msm_timer_map(0xAC100000, 0xAC100010))
335 msm_timer_init(19200000 / 4, 32, 7, false);