1 /* linux/arch/arm/mach-msm/timer.c
3 * Copyright (C) 2007 Google, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #include <linux/init.h>
17 #include <linux/time.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/clk.h>
21 #include <linux/clockchips.h>
22 #include <linux/delay.h>
25 #include <asm/mach/time.h>
26 #include <asm/hardware/gic.h>
28 #include <mach/msm_iomap.h>
31 #define TIMER_MATCH_VAL 0x0000
32 #define TIMER_COUNT_VAL 0x0004
33 #define TIMER_ENABLE 0x0008
34 #define TIMER_ENABLE_CLR_ON_MATCH_EN 2
35 #define TIMER_ENABLE_EN 1
36 #define TIMER_CLEAR 0x000C
37 #define DGT_CLK_CTL 0x0034
39 DGT_CLK_CTL_DIV_1 = 0,
40 DGT_CLK_CTL_DIV_2 = 1,
41 DGT_CLK_CTL_DIV_3 = 2,
42 DGT_CLK_CTL_DIV_4 = 3,
44 #define CSR_PROTECTION 0x0020
45 #define CSR_PROTECTION_EN 1
54 #define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
56 /* TODO: Remove these ifdefs */
57 #if defined(CONFIG_ARCH_QSD8X50)
58 #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
59 #define MSM_DGT_SHIFT (0)
60 #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \
61 defined(CONFIG_ARCH_MSM8960)
62 #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
63 #define MSM_DGT_SHIFT (0)
65 #define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
66 #define MSM_DGT_SHIFT (5)
70 struct clock_event_device clockevent;
71 struct clocksource clocksource;
73 void __iomem *regbase;
76 void __iomem *global_counter;
77 void __iomem *local_counter;
87 static struct msm_clock msm_clocks[];
88 static struct clock_event_device *local_clock_event;
90 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
92 struct clock_event_device *evt = dev_id;
93 if (smp_processor_id() != 0)
94 evt = local_clock_event;
95 if (evt->event_handler == NULL)
97 evt->event_handler(evt);
101 static cycle_t msm_read_timer_count(struct clocksource *cs)
103 struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
106 * Shift timer count down by a constant due to unreliable lower bits
109 return readl(clk->global_counter) >> clk->shift;
112 static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
116 for (i = 0; i < NR_TIMERS; i++)
117 if (evt == &(msm_clocks[i].clockevent))
118 return &msm_clocks[i];
119 return &msm_clocks[MSM_GLOBAL_TIMER];
121 return container_of(evt, struct msm_clock, clockevent);
125 static int msm_timer_set_next_event(unsigned long cycles,
126 struct clock_event_device *evt)
128 struct msm_clock *clock = clockevent_to_clock(evt);
129 uint32_t now = readl(clock->local_counter);
130 uint32_t alarm = now + (cycles << clock->shift);
132 writel(alarm, clock->regbase + TIMER_MATCH_VAL);
136 static void msm_timer_set_mode(enum clock_event_mode mode,
137 struct clock_event_device *evt)
139 struct msm_clock *clock = clockevent_to_clock(evt);
142 case CLOCK_EVT_MODE_RESUME:
143 case CLOCK_EVT_MODE_PERIODIC:
145 case CLOCK_EVT_MODE_ONESHOT:
146 writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
148 case CLOCK_EVT_MODE_UNUSED:
149 case CLOCK_EVT_MODE_SHUTDOWN:
150 writel(0, clock->regbase + TIMER_ENABLE);
155 static struct msm_clock msm_clocks[] = {
159 .features = CLOCK_EVT_FEAT_ONESHOT,
162 .set_next_event = msm_timer_set_next_event,
163 .set_mode = msm_timer_set_mode,
168 .read = msm_read_timer_count,
169 .mask = CLOCKSOURCE_MASK(32),
170 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
174 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
175 .handler = msm_timer_interrupt,
176 .dev_id = &msm_clocks[0].clockevent,
177 .irq = INT_GP_TIMER_EXP
184 .features = CLOCK_EVT_FEAT_ONESHOT,
185 .shift = 32 + MSM_DGT_SHIFT,
187 .set_next_event = msm_timer_set_next_event,
188 .set_mode = msm_timer_set_mode,
193 .read = msm_read_timer_count,
194 .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
195 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
199 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
200 .handler = msm_timer_interrupt,
201 .dev_id = &msm_clocks[1].clockevent,
202 .irq = INT_DEBUG_TIMER_EXP
204 .freq = DGT_HZ >> MSM_DGT_SHIFT,
205 .shift = MSM_DGT_SHIFT,
209 static void __init msm_timer_init(void)
213 int global_offset = 0;
215 if (cpu_is_msm7x01()) {
216 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
217 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
218 } else if (cpu_is_msm7x30()) {
219 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
220 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
221 } else if (cpu_is_qsd8x50()) {
222 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
223 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
224 } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
225 msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
226 msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
228 /* Use CPU0's timer as the global timer. */
229 global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
233 #ifdef CONFIG_ARCH_MSM_SCORPIONMP
234 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
237 for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
238 struct msm_clock *clock = &msm_clocks[i];
239 struct clock_event_device *ce = &clock->clockevent;
240 struct clocksource *cs = &clock->clocksource;
242 clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
243 clock->global_counter = clock->local_counter + global_offset;
245 writel(0, clock->regbase + TIMER_ENABLE);
246 writel(0, clock->regbase + TIMER_CLEAR);
247 writel(~0, clock->regbase + TIMER_MATCH_VAL);
249 ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
250 /* allow at least 10 seconds to notice that the timer wrapped */
252 clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
253 /* 4 gets rounded down to 3 */
254 ce->min_delta_ns = clockevent_delta2ns(4, ce);
255 ce->cpumask = cpumask_of(0);
257 res = clocksource_register_hz(cs, clock->freq);
259 printk(KERN_ERR "msm_timer_init: clocksource_register "
260 "failed for %s\n", cs->name);
262 res = setup_irq(clock->irq.irq, &clock->irq);
264 printk(KERN_ERR "msm_timer_init: setup_irq "
265 "failed for %s\n", cs->name);
267 clockevents_register_device(ce);
272 int __cpuinit local_timer_setup(struct clock_event_device *evt)
274 struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
276 /* Use existing clock_event for cpu 0 */
277 if (!smp_processor_id())
280 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
282 if (!local_clock_event) {
283 writel(0, clock->regbase + TIMER_ENABLE);
284 writel(0, clock->regbase + TIMER_CLEAR);
285 writel(~0, clock->regbase + TIMER_MATCH_VAL);
287 evt->irq = clock->irq.irq;
288 evt->name = "local_timer";
289 evt->features = CLOCK_EVT_FEAT_ONESHOT;
290 evt->rating = clock->clockevent.rating;
291 evt->set_mode = msm_timer_set_mode;
292 evt->set_next_event = msm_timer_set_next_event;
293 evt->shift = clock->clockevent.shift;
294 evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
296 clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
297 evt->min_delta_ns = clockevent_delta2ns(4, evt);
299 local_clock_event = evt;
301 gic_enable_ppi(clock->irq.irq);
303 clockevents_register_device(evt);
307 inline int local_timer_ack(void)
314 struct sys_timer msm_timer = {
315 .init = msm_timer_init