1 /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 #include <linux/kernel.h>
19 #include <linux/platform_device.h>
20 #include <linux/bootmem.h>
22 #include <mach/msm_iomap-8x60.h>
23 #include <mach/irqs-8x60.h>
24 #include <mach/iommu.h>
26 static struct resource msm_iommu_jpegd_resources[] = {
28 .start = MSM_IOMMU_JPEGD_PHYS,
29 .end = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1,
31 .flags = IORESOURCE_MEM,
34 .name = "nonsecure_irq",
35 .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
36 .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
37 .flags = IORESOURCE_IRQ,
41 .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
42 .end = SMMU_JPEGD_CB_SC_SECURE_IRQ,
43 .flags = IORESOURCE_IRQ,
47 static struct resource msm_iommu_vpe_resources[] = {
49 .start = MSM_IOMMU_VPE_PHYS,
50 .end = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1,
52 .flags = IORESOURCE_MEM,
55 .name = "nonsecure_irq",
56 .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
57 .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
58 .flags = IORESOURCE_IRQ,
62 .start = SMMU_VPE_CB_SC_SECURE_IRQ,
63 .end = SMMU_VPE_CB_SC_SECURE_IRQ,
64 .flags = IORESOURCE_IRQ,
68 static struct resource msm_iommu_mdp0_resources[] = {
70 .start = MSM_IOMMU_MDP0_PHYS,
71 .end = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1,
73 .flags = IORESOURCE_MEM,
76 .name = "nonsecure_irq",
77 .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
78 .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
79 .flags = IORESOURCE_IRQ,
83 .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
84 .end = SMMU_MDP0_CB_SC_SECURE_IRQ,
85 .flags = IORESOURCE_IRQ,
89 static struct resource msm_iommu_mdp1_resources[] = {
91 .start = MSM_IOMMU_MDP1_PHYS,
92 .end = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1,
94 .flags = IORESOURCE_MEM,
97 .name = "nonsecure_irq",
98 .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
99 .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
100 .flags = IORESOURCE_IRQ,
103 .name = "secure_irq",
104 .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
105 .end = SMMU_MDP1_CB_SC_SECURE_IRQ,
106 .flags = IORESOURCE_IRQ,
110 static struct resource msm_iommu_rot_resources[] = {
112 .start = MSM_IOMMU_ROT_PHYS,
113 .end = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1,
115 .flags = IORESOURCE_MEM,
118 .name = "nonsecure_irq",
119 .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
120 .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
121 .flags = IORESOURCE_IRQ,
124 .name = "secure_irq",
125 .start = SMMU_ROT_CB_SC_SECURE_IRQ,
126 .end = SMMU_ROT_CB_SC_SECURE_IRQ,
127 .flags = IORESOURCE_IRQ,
131 static struct resource msm_iommu_ijpeg_resources[] = {
133 .start = MSM_IOMMU_IJPEG_PHYS,
134 .end = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1,
136 .flags = IORESOURCE_MEM,
139 .name = "nonsecure_irq",
140 .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
141 .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
142 .flags = IORESOURCE_IRQ,
145 .name = "secure_irq",
146 .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
147 .end = SMMU_IJPEG_CB_SC_SECURE_IRQ,
148 .flags = IORESOURCE_IRQ,
152 static struct resource msm_iommu_vfe_resources[] = {
154 .start = MSM_IOMMU_VFE_PHYS,
155 .end = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1,
157 .flags = IORESOURCE_MEM,
160 .name = "nonsecure_irq",
161 .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
162 .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
163 .flags = IORESOURCE_IRQ,
166 .name = "secure_irq",
167 .start = SMMU_VFE_CB_SC_SECURE_IRQ,
168 .end = SMMU_VFE_CB_SC_SECURE_IRQ,
169 .flags = IORESOURCE_IRQ,
173 static struct resource msm_iommu_vcodec_a_resources[] = {
175 .start = MSM_IOMMU_VCODEC_A_PHYS,
176 .end = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1,
178 .flags = IORESOURCE_MEM,
181 .name = "nonsecure_irq",
182 .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
183 .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
184 .flags = IORESOURCE_IRQ,
187 .name = "secure_irq",
188 .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
189 .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
190 .flags = IORESOURCE_IRQ,
194 static struct resource msm_iommu_vcodec_b_resources[] = {
196 .start = MSM_IOMMU_VCODEC_B_PHYS,
197 .end = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1,
199 .flags = IORESOURCE_MEM,
202 .name = "nonsecure_irq",
203 .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
204 .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
205 .flags = IORESOURCE_IRQ,
208 .name = "secure_irq",
209 .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
210 .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
211 .flags = IORESOURCE_IRQ,
215 static struct resource msm_iommu_gfx3d_resources[] = {
217 .start = MSM_IOMMU_GFX3D_PHYS,
218 .end = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1,
220 .flags = IORESOURCE_MEM,
223 .name = "nonsecure_irq",
224 .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
225 .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
226 .flags = IORESOURCE_IRQ,
229 .name = "secure_irq",
230 .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
231 .end = SMMU_GFX3D_CB_SC_SECURE_IRQ,
232 .flags = IORESOURCE_IRQ,
236 static struct resource msm_iommu_gfx2d0_resources[] = {
238 .start = MSM_IOMMU_GFX2D0_PHYS,
239 .end = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1,
241 .flags = IORESOURCE_MEM,
244 .name = "nonsecure_irq",
245 .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
246 .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
247 .flags = IORESOURCE_IRQ,
250 .name = "secure_irq",
251 .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
252 .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
253 .flags = IORESOURCE_IRQ,
257 static struct resource msm_iommu_gfx2d1_resources[] = {
259 .start = MSM_IOMMU_GFX2D1_PHYS,
260 .end = MSM_IOMMU_GFX2D1_PHYS + MSM_IOMMU_GFX2D1_SIZE - 1,
262 .flags = IORESOURCE_MEM,
265 .name = "nonsecure_irq",
266 .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
267 .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
268 .flags = IORESOURCE_IRQ,
271 .name = "secure_irq",
272 .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
273 .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
274 .flags = IORESOURCE_IRQ,
278 static struct platform_device msm_root_iommu_dev = {
283 static struct msm_iommu_dev jpegd_iommu = {
288 static struct msm_iommu_dev vpe_iommu = {
292 static struct msm_iommu_dev mdp0_iommu = {
296 static struct msm_iommu_dev mdp1_iommu = {
300 static struct msm_iommu_dev rot_iommu = {
304 static struct msm_iommu_dev ijpeg_iommu = {
308 static struct msm_iommu_dev vfe_iommu = {
313 static struct msm_iommu_dev vcodec_a_iommu = {
317 static struct msm_iommu_dev vcodec_b_iommu = {
321 static struct msm_iommu_dev gfx3d_iommu = {
326 static struct msm_iommu_dev gfx2d0_iommu = {
331 static struct msm_iommu_dev gfx2d1_iommu = {
336 static struct platform_device msm_device_iommu_jpegd = {
340 .parent = &msm_root_iommu_dev.dev,
342 .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
343 .resource = msm_iommu_jpegd_resources,
346 static struct platform_device msm_device_iommu_vpe = {
350 .parent = &msm_root_iommu_dev.dev,
352 .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
353 .resource = msm_iommu_vpe_resources,
356 static struct platform_device msm_device_iommu_mdp0 = {
360 .parent = &msm_root_iommu_dev.dev,
362 .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
363 .resource = msm_iommu_mdp0_resources,
366 static struct platform_device msm_device_iommu_mdp1 = {
370 .parent = &msm_root_iommu_dev.dev,
372 .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
373 .resource = msm_iommu_mdp1_resources,
376 static struct platform_device msm_device_iommu_rot = {
380 .parent = &msm_root_iommu_dev.dev,
382 .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
383 .resource = msm_iommu_rot_resources,
386 static struct platform_device msm_device_iommu_ijpeg = {
390 .parent = &msm_root_iommu_dev.dev,
392 .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
393 .resource = msm_iommu_ijpeg_resources,
396 static struct platform_device msm_device_iommu_vfe = {
400 .parent = &msm_root_iommu_dev.dev,
402 .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
403 .resource = msm_iommu_vfe_resources,
406 static struct platform_device msm_device_iommu_vcodec_a = {
410 .parent = &msm_root_iommu_dev.dev,
412 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
413 .resource = msm_iommu_vcodec_a_resources,
416 static struct platform_device msm_device_iommu_vcodec_b = {
420 .parent = &msm_root_iommu_dev.dev,
422 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
423 .resource = msm_iommu_vcodec_b_resources,
426 static struct platform_device msm_device_iommu_gfx3d = {
430 .parent = &msm_root_iommu_dev.dev,
432 .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
433 .resource = msm_iommu_gfx3d_resources,
436 static struct platform_device msm_device_iommu_gfx2d0 = {
440 .parent = &msm_root_iommu_dev.dev,
442 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
443 .resource = msm_iommu_gfx2d0_resources,
446 struct platform_device msm_device_iommu_gfx2d1 = {
450 .parent = &msm_root_iommu_dev.dev,
452 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
453 .resource = msm_iommu_gfx2d1_resources,
456 static struct msm_iommu_ctx_dev jpegd_src_ctx = {
462 static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
468 static struct msm_iommu_ctx_dev vpe_src_ctx = {
474 static struct msm_iommu_ctx_dev vpe_dst_ctx = {
480 static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
486 static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
489 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
492 static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
498 static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
501 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
504 static struct msm_iommu_ctx_dev rot_src_ctx = {
510 static struct msm_iommu_ctx_dev rot_dst_ctx = {
516 static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
522 static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
528 static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
531 .mids = {2, 3, 4, 5, 6, 7, 8, -1}
534 static struct msm_iommu_ctx_dev vfe_misc_ctx = {
537 .mids = {0, 1, 9, -1}
540 static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
541 .name = "vcodec_a_stream",
546 static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
547 .name = "vcodec_a_mm1",
549 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
552 static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
553 .name = "vcodec_b_mm2",
555 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
558 static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
559 .name = "gfx3d_user",
561 .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
564 static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
565 .name = "gfx3d_priv",
567 .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
571 static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
572 .name = "gfx2d0_2d0",
574 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
577 static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
578 .name = "gfx2d1_2d1",
580 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
583 static struct platform_device msm_device_jpegd_src_ctx = {
584 .name = "msm_iommu_ctx",
587 .parent = &msm_device_iommu_jpegd.dev,
591 static struct platform_device msm_device_jpegd_dst_ctx = {
592 .name = "msm_iommu_ctx",
595 .parent = &msm_device_iommu_jpegd.dev,
599 static struct platform_device msm_device_vpe_src_ctx = {
600 .name = "msm_iommu_ctx",
603 .parent = &msm_device_iommu_vpe.dev,
607 static struct platform_device msm_device_vpe_dst_ctx = {
608 .name = "msm_iommu_ctx",
611 .parent = &msm_device_iommu_vpe.dev,
615 static struct platform_device msm_device_mdp_vg1_ctx = {
616 .name = "msm_iommu_ctx",
619 .parent = &msm_device_iommu_mdp0.dev,
623 static struct platform_device msm_device_mdp_rgb1_ctx = {
624 .name = "msm_iommu_ctx",
627 .parent = &msm_device_iommu_mdp0.dev,
631 static struct platform_device msm_device_mdp_vg2_ctx = {
632 .name = "msm_iommu_ctx",
635 .parent = &msm_device_iommu_mdp1.dev,
639 static struct platform_device msm_device_mdp_rgb2_ctx = {
640 .name = "msm_iommu_ctx",
643 .parent = &msm_device_iommu_mdp1.dev,
647 static struct platform_device msm_device_rot_src_ctx = {
648 .name = "msm_iommu_ctx",
651 .parent = &msm_device_iommu_rot.dev,
655 static struct platform_device msm_device_rot_dst_ctx = {
656 .name = "msm_iommu_ctx",
659 .parent = &msm_device_iommu_rot.dev,
663 static struct platform_device msm_device_ijpeg_src_ctx = {
664 .name = "msm_iommu_ctx",
667 .parent = &msm_device_iommu_ijpeg.dev,
671 static struct platform_device msm_device_ijpeg_dst_ctx = {
672 .name = "msm_iommu_ctx",
675 .parent = &msm_device_iommu_ijpeg.dev,
679 static struct platform_device msm_device_vfe_imgwr_ctx = {
680 .name = "msm_iommu_ctx",
683 .parent = &msm_device_iommu_vfe.dev,
687 static struct platform_device msm_device_vfe_misc_ctx = {
688 .name = "msm_iommu_ctx",
691 .parent = &msm_device_iommu_vfe.dev,
695 static struct platform_device msm_device_vcodec_a_stream_ctx = {
696 .name = "msm_iommu_ctx",
699 .parent = &msm_device_iommu_vcodec_a.dev,
703 static struct platform_device msm_device_vcodec_a_mm1_ctx = {
704 .name = "msm_iommu_ctx",
707 .parent = &msm_device_iommu_vcodec_a.dev,
711 static struct platform_device msm_device_vcodec_b_mm2_ctx = {
712 .name = "msm_iommu_ctx",
715 .parent = &msm_device_iommu_vcodec_b.dev,
719 static struct platform_device msm_device_gfx3d_user_ctx = {
720 .name = "msm_iommu_ctx",
723 .parent = &msm_device_iommu_gfx3d.dev,
727 static struct platform_device msm_device_gfx3d_priv_ctx = {
728 .name = "msm_iommu_ctx",
731 .parent = &msm_device_iommu_gfx3d.dev,
735 static struct platform_device msm_device_gfx2d0_2d0_ctx = {
736 .name = "msm_iommu_ctx",
739 .parent = &msm_device_iommu_gfx2d0.dev,
743 static struct platform_device msm_device_gfx2d1_2d1_ctx = {
744 .name = "msm_iommu_ctx",
747 .parent = &msm_device_iommu_gfx2d1.dev,
751 static struct platform_device *msm_iommu_devs[] = {
752 &msm_device_iommu_jpegd,
753 &msm_device_iommu_vpe,
754 &msm_device_iommu_mdp0,
755 &msm_device_iommu_mdp1,
756 &msm_device_iommu_rot,
757 &msm_device_iommu_ijpeg,
758 &msm_device_iommu_vfe,
759 &msm_device_iommu_vcodec_a,
760 &msm_device_iommu_vcodec_b,
761 &msm_device_iommu_gfx3d,
762 &msm_device_iommu_gfx2d0,
763 &msm_device_iommu_gfx2d1,
766 static struct msm_iommu_dev *msm_iommu_data[] = {
781 static struct platform_device *msm_iommu_ctx_devs[] = {
782 &msm_device_jpegd_src_ctx,
783 &msm_device_jpegd_dst_ctx,
784 &msm_device_vpe_src_ctx,
785 &msm_device_vpe_dst_ctx,
786 &msm_device_mdp_vg1_ctx,
787 &msm_device_mdp_rgb1_ctx,
788 &msm_device_mdp_vg2_ctx,
789 &msm_device_mdp_rgb2_ctx,
790 &msm_device_rot_src_ctx,
791 &msm_device_rot_dst_ctx,
792 &msm_device_ijpeg_src_ctx,
793 &msm_device_ijpeg_dst_ctx,
794 &msm_device_vfe_imgwr_ctx,
795 &msm_device_vfe_misc_ctx,
796 &msm_device_vcodec_a_stream_ctx,
797 &msm_device_vcodec_a_mm1_ctx,
798 &msm_device_vcodec_b_mm2_ctx,
799 &msm_device_gfx3d_user_ctx,
800 &msm_device_gfx3d_priv_ctx,
801 &msm_device_gfx2d0_2d0_ctx,
802 &msm_device_gfx2d1_2d1_ctx,
805 static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
820 &vcodec_a_stream_ctx,
829 static int __init msm8x60_iommu_init(void)
833 ret = platform_device_register(&msm_root_iommu_dev);
835 pr_err("Failed to register root IOMMU device!\n");
839 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
840 ret = platform_device_add_data(msm_iommu_devs[i],
842 sizeof(struct msm_iommu_dev));
844 pr_err("platform_device_add_data failed, "
849 ret = platform_device_register(msm_iommu_devs[i]);
852 pr_err("platform_device_register iommu failed, "
858 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
859 ret = platform_device_add_data(msm_iommu_ctx_devs[i],
860 msm_iommu_ctx_data[i],
861 sizeof(*msm_iommu_ctx_devs[i]));
863 pr_err("platform_device_add_data iommu failed, "
865 goto failure_unwind2;
868 ret = platform_device_register(msm_iommu_ctx_devs[i]);
870 pr_err("platform_device_register ctx failed, "
872 goto failure_unwind2;
879 platform_device_unregister(msm_iommu_ctx_devs[i]);
882 platform_device_unregister(msm_iommu_devs[i]);
884 platform_device_unregister(&msm_root_iommu_dev);
889 static void __exit msm8x60_iommu_exit(void)
893 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
894 platform_device_unregister(msm_iommu_ctx_devs[i]);
896 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
897 platform_device_unregister(msm_iommu_devs[i]);
899 platform_device_unregister(&msm_root_iommu_dev);
902 subsys_initcall(msm8x60_iommu_init);
903 module_exit(msm8x60_iommu_exit);
905 MODULE_LICENSE("GPL v2");
906 MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");