2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
23 #include <asm/pgtable.h>
24 #include <asm/hardware/cache-l2x0.h>
25 #include <asm/mach/map.h>
27 #include <mach/common.h>
28 #include <mach/devices-common.h>
29 #include <mach/hardware.h>
30 #include <mach/iomux-v3.h>
31 #include <mach/irqs.h>
33 static void imx3_idle(void)
35 unsigned long reg = 0;
37 /* disable I and D cache */
38 "mrc p15, 0, %0, c1, c0, 0\n"
39 "bic %0, %0, #0x00001000\n"
40 "bic %0, %0, #0x00000004\n"
41 "mcr p15, 0, %0, c1, c0, 0\n"
42 /* invalidate I cache */
44 "mcr p15, 0, %0, c7, c5, 0\n"
45 /* clear and invalidate D cache */
47 "mcr p15, 0, %0, c7, c14, 0\n"
50 "mcr p15, 0, %0, c7, c0, 4\n"
51 "nop\n" "nop\n" "nop\n" "nop\n"
52 "nop\n" "nop\n" "nop\n"
53 /* enable I and D cache */
54 "mrc p15, 0, %0, c1, c0, 0\n"
55 "orr %0, %0, #0x00001000\n"
56 "orr %0, %0, #0x00000004\n"
57 "mcr p15, 0, %0, c1, c0, 0\n"
61 static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
64 if (mtype == MT_DEVICE) {
66 * Access all peripherals below 0x80000000 as nonshared device
67 * on mx3, but leave l2cc alone. Otherwise cache corruptions
70 if (phys_addr < 0x80000000 &&
71 !addr_in_module(phys_addr, MX3x_L2CC))
72 mtype = MT_DEVICE_NONSHARED;
75 return __arm_ioremap(phys_addr, size, mtype);
78 void imx3_init_l2x0(void)
80 void __iomem *l2x0_base;
81 void __iomem *clkctl_base;
84 * First of all, we must repair broken chip settings. There are some
85 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
86 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
87 * Workaraound is to setup the correct register setting prior enabling the
88 * L2 cache. This should not hurt already working CPUs, as they are using the
91 #define L2_MEM_VAL 0x10
93 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
94 if (clkctl_base != NULL) {
95 writel(0x00000515, clkctl_base + L2_MEM_VAL);
98 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
101 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
102 if (IS_ERR(l2x0_base)) {
103 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
108 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
111 #ifdef CONFIG_SOC_IMX31
112 static struct map_desc mx31_io_desc[] __initdata = {
113 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
114 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
115 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
116 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
117 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
121 * This function initializes the memory map. It is called during the
122 * system startup to create static physical to virtual memory mappings
123 * for the IO modules.
125 void __init mx31_map_io(void)
127 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
130 void __init imx31_init_early(void)
132 mxc_set_cpu_type(MXC_CPU_MX31);
133 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
134 imx_idle = imx3_idle;
135 imx_ioremap = imx3_ioremap;
138 void __init mx31_init_irq(void)
140 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
143 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
144 .per_2_per_addr = 1677,
147 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
150 .bp_2_ap_addr = 1029,
153 static struct sdma_platform_data imx31_sdma_pdata __initdata = {
154 .fw_name = "sdma-imx31-to2.bin",
155 .script_addrs = &imx31_to2_sdma_script,
158 void __init imx31_soc_init(void)
160 int to_version = mx31_revision() >> 4;
164 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
165 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
166 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
168 if (to_version == 1) {
169 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
170 strlen(imx31_sdma_pdata.fw_name));
171 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
174 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
176 #endif /* ifdef CONFIG_SOC_IMX31 */
178 #ifdef CONFIG_SOC_IMX35
179 static struct map_desc mx35_io_desc[] __initdata = {
180 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
181 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
182 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
183 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
184 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
187 void __init mx35_map_io(void)
189 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
192 void __init imx35_init_early(void)
194 mxc_set_cpu_type(MXC_CPU_MX35);
195 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
196 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
197 imx_idle = imx3_idle;
198 imx_ioremap = imx3_ioremap;
201 void __init mx35_init_irq(void)
203 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
206 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
208 .uart_2_mcu_addr = 817,
209 .mcu_2_app_addr = 747,
210 .uartsh_2_mcu_addr = 1183,
211 .per_2_shp_addr = 1033,
212 .mcu_2_shp_addr = 961,
213 .ata_2_mcu_addr = 1333,
214 .mcu_2_ata_addr = 1252,
215 .app_2_mcu_addr = 683,
216 .shp_2_per_addr = 1111,
217 .shp_2_mcu_addr = 892,
220 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
222 .uart_2_mcu_addr = 904,
223 .per_2_app_addr = 1597,
224 .mcu_2_app_addr = 834,
225 .uartsh_2_mcu_addr = 1270,
226 .per_2_shp_addr = 1120,
227 .mcu_2_shp_addr = 1048,
228 .ata_2_mcu_addr = 1429,
229 .mcu_2_ata_addr = 1339,
230 .app_2_per_addr = 1531,
231 .app_2_mcu_addr = 770,
232 .shp_2_per_addr = 1198,
233 .shp_2_mcu_addr = 979,
236 static struct sdma_platform_data imx35_sdma_pdata __initdata = {
237 .fw_name = "sdma-imx35-to2.bin",
238 .script_addrs = &imx35_to2_sdma_script,
241 void __init imx35_soc_init(void)
243 int to_version = mx35_revision() >> 4;
247 /* i.mx35 has the i.mx31 type gpio */
248 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
249 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
250 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
252 if (to_version == 1) {
253 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
254 strlen(imx35_sdma_pdata.fw_name));
255 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
258 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
260 #endif /* ifdef CONFIG_SOC_IMX35 */