2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
16 #include <linux/slab.h>
17 #include <linux/jiffies.h>
18 #include <linux/err.h>
21 #define PLL_NUM_OFFSET 0x10
22 #define PLL_DENOM_OFFSET 0x20
24 #define BM_PLL_POWER (0x1 << 12)
25 #define BM_PLL_ENABLE (0x1 << 13)
26 #define BM_PLL_BYPASS (0x1 << 16)
27 #define BM_PLL_LOCK (0x1 << 31)
30 * struct clk_pllv3 - IMX PLL clock version 3
31 * @clk_hw: clock source
32 * @base: base address of PLL registers
33 * @powerup_set: set POWER bit to power up the PLL
34 * @gate_mask: mask of gate bits
35 * @div_mask: mask of divider bits
37 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
38 * is actually a multiplier, and always sits at bit 0.
48 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
50 static int clk_pllv3_prepare(struct clk_hw *hw)
52 struct clk_pllv3 *pll = to_clk_pllv3(hw);
53 unsigned long timeout = jiffies + msecs_to_jiffies(10);
56 val = readl_relaxed(pll->base);
57 val &= ~BM_PLL_BYPASS;
62 writel_relaxed(val, pll->base);
64 /* Wait for PLL to lock */
65 while (!(readl_relaxed(pll->base) & BM_PLL_LOCK))
66 if (time_after(jiffies, timeout))
72 static void clk_pllv3_unprepare(struct clk_hw *hw)
74 struct clk_pllv3 *pll = to_clk_pllv3(hw);
77 val = readl_relaxed(pll->base);
83 writel_relaxed(val, pll->base);
86 static int clk_pllv3_enable(struct clk_hw *hw)
88 struct clk_pllv3 *pll = to_clk_pllv3(hw);
91 val = readl_relaxed(pll->base);
92 val |= pll->gate_mask;
93 writel_relaxed(val, pll->base);
98 static void clk_pllv3_disable(struct clk_hw *hw)
100 struct clk_pllv3 *pll = to_clk_pllv3(hw);
103 val = readl_relaxed(pll->base);
104 val &= ~pll->gate_mask;
105 writel_relaxed(val, pll->base);
108 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
109 unsigned long parent_rate)
111 struct clk_pllv3 *pll = to_clk_pllv3(hw);
112 u32 div = readl_relaxed(pll->base) & pll->div_mask;
114 return (div == 1) ? parent_rate * 22 : parent_rate * 20;
117 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
118 unsigned long *prate)
120 unsigned long parent_rate = *prate;
122 return (rate >= parent_rate * 22) ? parent_rate * 22 :
126 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
127 unsigned long parent_rate)
129 struct clk_pllv3 *pll = to_clk_pllv3(hw);
132 if (rate == parent_rate * 22)
134 else if (rate == parent_rate * 20)
139 val = readl_relaxed(pll->base);
140 val &= ~pll->div_mask;
142 writel_relaxed(val, pll->base);
147 static const struct clk_ops clk_pllv3_ops = {
148 .prepare = clk_pllv3_prepare,
149 .unprepare = clk_pllv3_unprepare,
150 .enable = clk_pllv3_enable,
151 .disable = clk_pllv3_disable,
152 .recalc_rate = clk_pllv3_recalc_rate,
153 .round_rate = clk_pllv3_round_rate,
154 .set_rate = clk_pllv3_set_rate,
157 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
158 unsigned long parent_rate)
160 struct clk_pllv3 *pll = to_clk_pllv3(hw);
161 u32 div = readl_relaxed(pll->base) & pll->div_mask;
163 return parent_rate * div / 2;
166 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
167 unsigned long *prate)
169 unsigned long parent_rate = *prate;
170 unsigned long min_rate = parent_rate * 54 / 2;
171 unsigned long max_rate = parent_rate * 108 / 2;
176 else if (rate < min_rate)
178 div = rate * 2 / parent_rate;
180 return parent_rate * div / 2;
183 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
184 unsigned long parent_rate)
186 struct clk_pllv3 *pll = to_clk_pllv3(hw);
187 unsigned long min_rate = parent_rate * 54 / 2;
188 unsigned long max_rate = parent_rate * 108 / 2;
191 if (rate < min_rate || rate > max_rate)
194 div = rate * 2 / parent_rate;
195 val = readl_relaxed(pll->base);
196 val &= ~pll->div_mask;
198 writel_relaxed(val, pll->base);
203 static const struct clk_ops clk_pllv3_sys_ops = {
204 .prepare = clk_pllv3_prepare,
205 .unprepare = clk_pllv3_unprepare,
206 .enable = clk_pllv3_enable,
207 .disable = clk_pllv3_disable,
208 .recalc_rate = clk_pllv3_sys_recalc_rate,
209 .round_rate = clk_pllv3_sys_round_rate,
210 .set_rate = clk_pllv3_sys_set_rate,
213 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
214 unsigned long parent_rate)
216 struct clk_pllv3 *pll = to_clk_pllv3(hw);
217 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
218 u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
219 u32 div = readl_relaxed(pll->base) & pll->div_mask;
221 return (parent_rate * div) + ((parent_rate / mfd) * mfn);
224 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
225 unsigned long *prate)
227 unsigned long parent_rate = *prate;
228 unsigned long min_rate = parent_rate * 27;
229 unsigned long max_rate = parent_rate * 54;
231 u32 mfn, mfd = 1000000;
236 else if (rate < min_rate)
239 div = rate / parent_rate;
240 temp64 = (u64) (rate - div * parent_rate);
242 do_div(temp64, parent_rate);
245 return parent_rate * div + parent_rate / mfd * mfn;
248 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
249 unsigned long parent_rate)
251 struct clk_pllv3 *pll = to_clk_pllv3(hw);
252 unsigned long min_rate = parent_rate * 27;
253 unsigned long max_rate = parent_rate * 54;
255 u32 mfn, mfd = 1000000;
258 if (rate < min_rate || rate > max_rate)
261 div = rate / parent_rate;
262 temp64 = (u64) (rate - div * parent_rate);
264 do_div(temp64, parent_rate);
267 val = readl_relaxed(pll->base);
268 val &= ~pll->div_mask;
270 writel_relaxed(val, pll->base);
271 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
272 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
277 static const struct clk_ops clk_pllv3_av_ops = {
278 .prepare = clk_pllv3_prepare,
279 .unprepare = clk_pllv3_unprepare,
280 .enable = clk_pllv3_enable,
281 .disable = clk_pllv3_disable,
282 .recalc_rate = clk_pllv3_av_recalc_rate,
283 .round_rate = clk_pllv3_av_round_rate,
284 .set_rate = clk_pllv3_av_set_rate,
287 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
288 unsigned long parent_rate)
290 struct clk_pllv3 *pll = to_clk_pllv3(hw);
291 u32 div = readl_relaxed(pll->base) & pll->div_mask;
307 static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
308 unsigned long *prate)
310 if (rate >= 125000000)
312 else if (rate >= 100000000)
314 else if (rate >= 50000000)
321 static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
322 unsigned long parent_rate)
324 struct clk_pllv3 *pll = to_clk_pllv3(hw);
344 val = readl_relaxed(pll->base);
345 val &= ~pll->div_mask;
347 writel_relaxed(val, pll->base);
352 static const struct clk_ops clk_pllv3_enet_ops = {
353 .prepare = clk_pllv3_prepare,
354 .unprepare = clk_pllv3_unprepare,
355 .enable = clk_pllv3_enable,
356 .disable = clk_pllv3_disable,
357 .recalc_rate = clk_pllv3_enet_recalc_rate,
358 .round_rate = clk_pllv3_enet_round_rate,
359 .set_rate = clk_pllv3_enet_set_rate,
362 static const struct clk_ops clk_pllv3_mlb_ops = {
363 .prepare = clk_pllv3_prepare,
364 .unprepare = clk_pllv3_unprepare,
365 .enable = clk_pllv3_enable,
366 .disable = clk_pllv3_disable,
369 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
370 const char *parent_name, void __iomem *base,
371 u32 gate_mask, u32 div_mask)
373 struct clk_pllv3 *pll;
374 const struct clk_ops *ops;
376 struct clk_init_data init;
378 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
380 return ERR_PTR(-ENOMEM);
384 ops = &clk_pllv3_sys_ops;
387 ops = &clk_pllv3_ops;
388 pll->powerup_set = true;
391 ops = &clk_pllv3_av_ops;
394 ops = &clk_pllv3_enet_ops;
397 ops = &clk_pllv3_mlb_ops;
400 ops = &clk_pllv3_ops;
403 pll->gate_mask = gate_mask;
404 pll->div_mask = div_mask;
409 init.parent_names = &parent_name;
410 init.num_parents = 1;
412 pll->hw.init = &init;
414 clk = clk_register(NULL, &pll->hw);