2 #include <linux/clk-provider.h>
3 #include <linux/clkdev.h>
6 #include <linux/of_address.h>
12 static void __iomem *ccm __initdata;
14 /* Register offsets */
15 #define CCM_CSCR (ccm + 0x00)
16 #define CCM_MPCTL0 (ccm + 0x04)
17 #define CCM_MPCTL1 (ccm + 0x08)
18 #define CCM_SPCTL0 (ccm + 0x0c)
19 #define CCM_SPCTL1 (ccm + 0x10)
20 #define CCM_OSC26MCTL (ccm + 0x14)
21 #define CCM_PCDR0 (ccm + 0x18)
22 #define CCM_PCDR1 (ccm + 0x1c)
23 #define CCM_PCCR0 (ccm + 0x20)
24 #define CCM_PCCR1 (ccm + 0x24)
25 #define CCM_CCSR (ccm + 0x28)
26 #define CCM_PMCTL (ccm + 0x2c)
27 #define CCM_PMCOUNT (ccm + 0x30)
28 #define CCM_WKGDCTL (ccm + 0x34)
30 #define CCM_CSCR_UPDATE_DIS (1 << 31)
31 #define CCM_CSCR_SSI2 (1 << 23)
32 #define CCM_CSCR_SSI1 (1 << 22)
33 #define CCM_CSCR_VPU (1 << 21)
34 #define CCM_CSCR_MSHC (1 << 20)
35 #define CCM_CSCR_SPLLRES (1 << 19)
36 #define CCM_CSCR_MPLLRES (1 << 18)
37 #define CCM_CSCR_SP (1 << 17)
38 #define CCM_CSCR_MCU (1 << 16)
39 #define CCM_CSCR_OSC26MDIV (1 << 4)
40 #define CCM_CSCR_OSC26M (1 << 3)
41 #define CCM_CSCR_FPM (1 << 2)
42 #define CCM_CSCR_SPEN (1 << 1)
43 #define CCM_CSCR_MPEN (1 << 0)
46 #define CCM_CSCR_ARM_SRC (1 << 15)
48 #define CCM_SPCTL1_LF (1 << 15)
49 #define CCM_SPCTL1_BRMO (1 << 6)
51 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
52 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
53 static const char *mpll_sel_clks[] = { "fpm", "mpll_osc_sel", };
54 static const char *mpll_osc_sel_clks[] = { "ckih", "ckih_div1p5", };
55 static const char *clko_sel_clks[] = {
56 "ckil", "fpm", "ckih", "ckih",
57 "ckih", "mpll", "spll", "cpu_div",
58 "ahb", "ipg", "per1_div", "per2_div",
59 "per3_div", "per4_div", "ssi1_div", "ssi2_div",
60 "nfc_div", "mshc_div", "vpu_div", "60m",
61 "32k", "usb_div", "dptc",
64 static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
67 dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
68 per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
69 clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
70 clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
71 sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
72 rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
73 kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
74 gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
75 gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
76 emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
77 cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
78 vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
79 usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
80 vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
81 csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
82 uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
83 uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
84 mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
85 rtic_ahb_gate, mshc_baud_gate, clk_max
88 static struct clk *clk[clk_max];
89 static struct clk_onecell_data clk_data;
91 static void __init _mx27_clocks_init(unsigned long fref)
95 clk[dummy] = imx_clk_fixed("dummy", 0);
96 clk[ckih] = imx_clk_fixed("ckih", fref);
97 clk[ckil] = imx_clk_fixed("ckil", 32768);
98 clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1);
99 clk[ckih_div1p5] = imx_clk_fixed_factor("ckih_div1p5", "ckih", 2, 3);
101 clk[mpll_osc_sel] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1,
103 ARRAY_SIZE(mpll_osc_sel_clks));
104 clk[mpll_sel] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks,
105 ARRAY_SIZE(mpll_sel_clks));
106 clk[mpll] = imx_clk_pllv1("mpll", "mpll_sel", CCM_MPCTL0);
107 clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
108 clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
109 clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
111 if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
112 clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
113 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
115 clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
116 clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
119 clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
120 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
121 clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
122 clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
123 clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
124 clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
125 clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
126 clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6);
127 clk[usb_div] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3);
128 clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
129 clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
130 if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
131 clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
133 clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
134 clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
135 clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
136 clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
137 clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
138 clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6);
139 clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
140 clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
141 clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
142 clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
143 clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
144 clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
145 clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
146 clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
147 clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
148 clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
149 clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
150 clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
151 clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
152 clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
153 clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
154 clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
155 clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
156 clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
157 clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
158 clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
159 clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
160 clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
161 clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
162 clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
163 clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
164 clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
165 clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
166 clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
167 clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
168 clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
169 clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
170 clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
171 clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
172 clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
173 clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
174 clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
175 clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6);
176 clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7);
177 clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8);
178 clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9);
179 clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
180 clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
181 clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
182 clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
183 clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
184 clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
185 clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
186 clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
187 clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
188 clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
189 clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
190 clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
191 clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
192 clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
193 clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
194 clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
195 clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
196 clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
197 clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
198 clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
199 clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
200 clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
202 imx_check_clocks(clk, ARRAY_SIZE(clk));
204 clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
206 clk_prepare_enable(clk[emi_ahb_gate]);
208 imx_print_silicon_rev("i.MX27", mx27_revision());
211 int __init mx27_clocks_init(unsigned long fref)
213 ccm = ioremap(MX27_CCM_BASE_ADDR, SZ_4K);
215 _mx27_clocks_init(fref);
217 clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
218 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
219 clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
220 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
221 clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
222 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
223 clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
224 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
225 clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
226 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
227 clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
228 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
229 clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
230 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
231 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
232 clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
233 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
234 clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.1");
235 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.2");
236 clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "imx21-mmc.2");
237 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.0");
238 clk_register_clkdev(clk[cspi1_ipg_gate], "ipg", "imx27-cspi.0");
239 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.1");
240 clk_register_clkdev(clk[cspi2_ipg_gate], "ipg", "imx27-cspi.1");
241 clk_register_clkdev(clk[per2_gate], "per", "imx27-cspi.2");
242 clk_register_clkdev(clk[cspi3_ipg_gate], "ipg", "imx27-cspi.2");
243 clk_register_clkdev(clk[per3_gate], "per", "imx21-fb.0");
244 clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx21-fb.0");
245 clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx21-fb.0");
246 clk_register_clkdev(clk[csi_ahb_gate], "ahb", "imx27-camera.0");
247 clk_register_clkdev(clk[per4_gate], "per", "imx27-camera.0");
248 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
249 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "imx-udc-mx27");
250 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "imx-udc-mx27");
251 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
252 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
253 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
254 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
255 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
256 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
257 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
258 clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
259 clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
260 clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
261 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
262 clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
263 clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
264 clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
265 clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
266 clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
267 clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
268 clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
269 clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
270 clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
271 clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
272 clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
273 clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
274 clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "imx27-camera.0");
275 clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
276 clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
277 clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
279 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
284 static void __init mx27_clocks_init_dt(struct device_node *np)
286 struct device_node *refnp;
287 u32 fref = 26000000; /* default */
289 for_each_compatible_node(refnp, NULL, "fixed-clock") {
290 if (!of_device_is_compatible(refnp, "fsl,imx-osc26m"))
293 if (!of_property_read_u32(refnp, "clock-frequency", &fref))
297 ccm = of_iomap(np, 0);
299 _mx27_clocks_init(fref);
302 clk_data.clk_num = ARRAY_SIZE(clk);
303 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
305 mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx1-gpt"));
307 CLK_OF_DECLARE(imx27_ccm, "fsl,imx27-ccm", mx27_clocks_init_dt);