2 * linux/arch/arm/kernel/dec21285.c: PCI functions for DC21285
4 * Copyright (C) 1998-2001 Russell King
5 * Copyright (C) 1998-2000 Phil Blundell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/interrupt.h>
15 #include <linux/slab.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
20 #include <linux/spinlock.h>
21 #include <video/vga.h>
24 #include <asm/system.h>
25 #include <asm/mach/pci.h>
26 #include <asm/hardware/dec21285.h>
30 #define PCICMD_ABORT ((PCI_STATUS_REC_MASTER_ABORT| \
31 PCI_STATUS_REC_TARGET_ABORT)<<16)
33 #define PCICMD_ERROR_BITS ((PCI_STATUS_DETECTED_PARITY | \
34 PCI_STATUS_REC_MASTER_ABORT | \
35 PCI_STATUS_REC_TARGET_ABORT | \
36 PCI_STATUS_PARITY) << 16)
38 extern int setup_arm_irq(int, struct irqaction *);
39 extern void pcibios_report_status(u_int status_mask, int warn);
42 dc21285_base_address(struct pci_bus *bus, unsigned int devfn)
44 unsigned long addr = 0;
46 if (bus->number == 0) {
47 if (PCI_SLOT(devfn) == 0)
49 * For devfn 0, point at the 21285
55 if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
56 addr = PCICFG0_BASE | 0xc00000 | (devfn << 8);
59 addr = PCICFG1_BASE | (bus->number << 16) | (devfn << 8);
65 dc21285_read_config(struct pci_bus *bus, unsigned int devfn, int where,
68 unsigned long addr = dc21285_base_address(bus, devfn);
74 asm("ldrb %0, [%1, %2]"
75 : "=r" (v) : "r" (addr), "r" (where) : "cc");
78 asm("ldrh %0, [%1, %2]"
79 : "=r" (v) : "r" (addr), "r" (where) : "cc");
82 asm("ldr %0, [%1, %2]"
83 : "=r" (v) : "r" (addr), "r" (where) : "cc");
90 if (v & PCICMD_ABORT) {
91 *CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
95 return PCIBIOS_SUCCESSFUL;
99 dc21285_write_config(struct pci_bus *bus, unsigned int devfn, int where,
102 unsigned long addr = dc21285_base_address(bus, devfn);
108 asm("strb %0, [%1, %2]"
109 : : "r" (value), "r" (addr), "r" (where)
113 asm("strh %0, [%1, %2]"
114 : : "r" (value), "r" (addr), "r" (where)
118 asm("str %0, [%1, %2]"
119 : : "r" (value), "r" (addr), "r" (where)
125 if (v & PCICMD_ABORT) {
126 *CSR_PCICMD = v & (0xffff|PCICMD_ABORT);
130 return PCIBIOS_SUCCESSFUL;
133 static struct pci_ops dc21285_ops = {
134 .read = dc21285_read_config,
135 .write = dc21285_write_config,
138 static struct timer_list serr_timer;
139 static struct timer_list perr_timer;
141 static void dc21285_enable_error(unsigned long __data)
145 del_timer(&serr_timer);
149 del_timer(&perr_timer);
157 * Warn on PCI errors.
159 static irqreturn_t dc21285_abort_irq(int irq, void *dev_id)
168 if (status & PCI_STATUS_REC_MASTER_ABORT) {
169 printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n",
170 instruction_pointer(get_irq_regs()));
171 cmd |= PCI_STATUS_REC_MASTER_ABORT << 16;
174 if (status & PCI_STATUS_REC_TARGET_ABORT) {
175 printk(KERN_DEBUG "PCI: target abort: ");
176 pcibios_report_status(PCI_STATUS_REC_MASTER_ABORT |
177 PCI_STATUS_SIG_TARGET_ABORT |
178 PCI_STATUS_REC_TARGET_ABORT, 1);
181 cmd |= PCI_STATUS_REC_TARGET_ABORT << 16;
189 static irqreturn_t dc21285_serr_irq(int irq, void *dev_id)
191 struct timer_list *timer = dev_id;
194 printk(KERN_DEBUG "PCI: system error received: ");
195 pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
198 cntl = *CSR_SA110_CNTL & 0xffffdf07;
199 *CSR_SA110_CNTL = cntl | SA110_CNTL_RXSERR;
202 * back off this interrupt
205 timer->expires = jiffies + HZ;
211 static irqreturn_t dc21285_discard_irq(int irq, void *dev_id)
213 printk(KERN_DEBUG "PCI: discard timer expired\n");
214 *CSR_SA110_CNTL &= 0xffffde07;
219 static irqreturn_t dc21285_dparity_irq(int irq, void *dev_id)
223 printk(KERN_DEBUG "PCI: data parity error detected: ");
224 pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
227 cmd = *CSR_PCICMD & 0xffff;
228 *CSR_PCICMD = cmd | 1 << 24;
233 static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
235 struct timer_list *timer = dev_id;
238 printk(KERN_DEBUG "PCI: parity error detected: ");
239 pcibios_report_status(PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY, 1);
242 cmd = *CSR_PCICMD & 0xffff;
243 *CSR_PCICMD = cmd | 1 << 31;
246 * back off this interrupt
249 timer->expires = jiffies + HZ;
255 int __init dc21285_setup(int nr, struct pci_sys_data *sys)
257 struct resource *res;
259 if (nr || !footbridge_cfn_mode())
262 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
264 printk("out of memory for root bus resources");
268 res[0].flags = IORESOURCE_MEM;
269 res[0].name = "Footbridge non-prefetch";
270 res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
271 res[1].name = "Footbridge prefetch";
273 allocate_resource(&iomem_resource, &res[1], 0x20000000,
274 0xa0000000, 0xffffffff, 0x20000000, NULL, NULL);
275 allocate_resource(&iomem_resource, &res[0], 0x40000000,
276 0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
278 pci_add_resource(&sys->resources, &ioport_resource);
279 pci_add_resource(&sys->resources, &res[0]);
280 pci_add_resource(&sys->resources, &res[1]);
281 sys->mem_offset = DC21285_PCI_MEM;
286 struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys)
288 return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources);
291 #define dc21285_request_irq(_a, _b, _c, _d, _e) \
292 WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0)
294 void __init dc21285_preinit(void)
296 unsigned int mem_size, mem_mask;
299 pcibios_min_mem = 0x81000000;
300 vga_base = PCIMEM_BASE;
302 mem_size = (unsigned int)high_memory - PAGE_OFFSET;
303 for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
304 if (mem_mask >= mem_size)
308 * These registers need to be set up whether we're the
309 * central function or not.
311 *CSR_SDRAMBASEMASK = (mem_mask - 1) & 0x0ffc0000;
312 *CSR_SDRAMBASEOFFSET = 0;
313 *CSR_ROMBASEMASK = 0x80000000;
314 *CSR_CSRBASEMASK = 0;
315 *CSR_CSRBASEOFFSET = 0;
316 *CSR_PCIADDR_EXTN = 0;
318 cfn_mode = __footbridge_cfn_mode();
320 printk(KERN_INFO "PCI: DC21285 footbridge, revision %02lX, in "
321 "%s mode\n", *CSR_CLASSREV & 0xff, cfn_mode ?
322 "central function" : "addin");
324 if (footbridge_cfn_mode()) {
326 * Clear any existing errors - we aren't
327 * interested in historical data...
329 *CSR_SA110_CNTL = (*CSR_SA110_CNTL & 0xffffde07) |
331 *CSR_PCICMD = (*CSR_PCICMD & 0xffff) | PCICMD_ERROR_BITS;
334 init_timer(&serr_timer);
335 init_timer(&perr_timer);
337 serr_timer.data = IRQ_PCI_SERR;
338 serr_timer.function = dc21285_enable_error;
339 perr_timer.data = IRQ_PCI_PERR;
340 perr_timer.function = dc21285_enable_error;
343 * We don't care if these fail.
345 dc21285_request_irq(IRQ_PCI_SERR, dc21285_serr_irq, IRQF_DISABLED,
346 "PCI system error", &serr_timer);
347 dc21285_request_irq(IRQ_PCI_PERR, dc21285_parity_irq, IRQF_DISABLED,
348 "PCI parity error", &perr_timer);
349 dc21285_request_irq(IRQ_PCI_ABORT, dc21285_abort_irq, IRQF_DISABLED,
351 dc21285_request_irq(IRQ_DISCARD_TIMER, dc21285_discard_irq, IRQF_DISABLED,
352 "Discard timer", NULL);
353 dc21285_request_irq(IRQ_PCI_DPERR, dc21285_dparity_irq, IRQF_DISABLED,
354 "PCI data parity", NULL);
357 static struct resource csrio;
359 csrio.flags = IORESOURCE_IO;
360 csrio.name = "Footbridge";
362 allocate_resource(&ioport_resource, &csrio, 128,
363 0xff00, 0xffff, 128, NULL, NULL);
366 * Map our SDRAM at a known address in PCI space, just in case
367 * the firmware had other ideas. Using a nonzero base is
368 * necessary, since some VGA cards forcefully use PCI addresses
369 * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
371 *CSR_PCICSRBASE = 0xf4000000;
372 *CSR_PCICSRIOBASE = csrio.start;
373 *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
375 *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
376 PCI_COMMAND_INVALIDATE | PCICMD_ERROR_BITS;
377 } else if (footbridge_cfn_mode() != 0) {
379 * If we are not compiled to accept "add-in" mode, then
380 * we are using a constant virt_to_bus translation which
381 * can not hope to cater for the way the host BIOS has
382 * set up the machine.
384 panic("PCI: this kernel is compiled for central "
385 "function mode only");
389 void __init dc21285_postinit(void)
391 register_isa_ports(DC21285_PCI_MEM, DC21285_PCI_IO, 0);