1 /* linux/arch/arm/mach-exynos4/clock.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
25 #include <mach/regs-clock.h>
26 #include <mach/sysmmu.h>
28 static struct clk clk_sclk_hdmi27m = {
29 .name = "sclk_hdmi27m",
33 static struct clk clk_sclk_hdmiphy = {
34 .name = "sclk_hdmiphy",
37 static struct clk clk_sclk_usbphy0 = {
38 .name = "sclk_usbphy0",
42 static struct clk clk_sclk_usbphy1 = {
43 .name = "sclk_usbphy1",
46 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
48 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
51 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
53 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
56 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
58 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
61 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
63 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
66 static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
68 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
71 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
73 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
76 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
78 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
81 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
83 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
86 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
88 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
91 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
93 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
96 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
98 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
101 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
103 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
106 static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
108 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
111 static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
113 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
116 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
118 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
121 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
123 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
126 /* Core list of CMU_CPU side */
128 static struct clksrc_clk clk_mout_apll = {
132 .sources = &clk_src_apll,
133 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
136 static struct clksrc_clk clk_sclk_apll = {
139 .parent = &clk_mout_apll.clk,
141 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
144 static struct clksrc_clk clk_mout_epll = {
148 .sources = &clk_src_epll,
149 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
152 static struct clksrc_clk clk_mout_mpll = {
156 .sources = &clk_src_mpll,
157 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
160 static struct clk *clkset_moutcore_list[] = {
161 [0] = &clk_mout_apll.clk,
162 [1] = &clk_mout_mpll.clk,
165 static struct clksrc_sources clkset_moutcore = {
166 .sources = clkset_moutcore_list,
167 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
170 static struct clksrc_clk clk_moutcore = {
174 .sources = &clkset_moutcore,
175 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
178 static struct clksrc_clk clk_coreclk = {
181 .parent = &clk_moutcore.clk,
183 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
186 static struct clksrc_clk clk_armclk = {
189 .parent = &clk_coreclk.clk,
193 static struct clksrc_clk clk_aclk_corem0 = {
195 .name = "aclk_corem0",
196 .parent = &clk_coreclk.clk,
198 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
201 static struct clksrc_clk clk_aclk_cores = {
203 .name = "aclk_cores",
204 .parent = &clk_coreclk.clk,
206 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
209 static struct clksrc_clk clk_aclk_corem1 = {
211 .name = "aclk_corem1",
212 .parent = &clk_coreclk.clk,
214 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
217 static struct clksrc_clk clk_periphclk = {
220 .parent = &clk_coreclk.clk,
222 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
225 /* Core list of CMU_CORE side */
227 static struct clk *clkset_corebus_list[] = {
228 [0] = &clk_mout_mpll.clk,
229 [1] = &clk_sclk_apll.clk,
232 static struct clksrc_sources clkset_mout_corebus = {
233 .sources = clkset_corebus_list,
234 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
237 static struct clksrc_clk clk_mout_corebus = {
239 .name = "mout_corebus",
241 .sources = &clkset_mout_corebus,
242 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
245 static struct clksrc_clk clk_sclk_dmc = {
248 .parent = &clk_mout_corebus.clk,
250 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
253 static struct clksrc_clk clk_aclk_cored = {
255 .name = "aclk_cored",
256 .parent = &clk_sclk_dmc.clk,
258 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
261 static struct clksrc_clk clk_aclk_corep = {
263 .name = "aclk_corep",
264 .parent = &clk_aclk_cored.clk,
266 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
269 static struct clksrc_clk clk_aclk_acp = {
272 .parent = &clk_mout_corebus.clk,
274 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
277 static struct clksrc_clk clk_pclk_acp = {
280 .parent = &clk_aclk_acp.clk,
282 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
285 /* Core list of CMU_TOP side */
287 static struct clk *clkset_aclk_top_list[] = {
288 [0] = &clk_mout_mpll.clk,
289 [1] = &clk_sclk_apll.clk,
292 static struct clksrc_sources clkset_aclk = {
293 .sources = clkset_aclk_top_list,
294 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
297 static struct clksrc_clk clk_aclk_200 = {
301 .sources = &clkset_aclk,
302 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
303 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
306 static struct clksrc_clk clk_aclk_100 = {
310 .sources = &clkset_aclk,
311 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
312 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
315 static struct clksrc_clk clk_aclk_160 = {
319 .sources = &clkset_aclk,
320 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
321 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
324 static struct clksrc_clk clk_aclk_133 = {
328 .sources = &clkset_aclk,
329 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
330 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
333 static struct clk *clkset_vpllsrc_list[] = {
335 [1] = &clk_sclk_hdmi27m,
338 static struct clksrc_sources clkset_vpllsrc = {
339 .sources = clkset_vpllsrc_list,
340 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
343 static struct clksrc_clk clk_vpllsrc = {
346 .enable = exynos4_clksrc_mask_top_ctrl,
349 .sources = &clkset_vpllsrc,
350 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
353 static struct clk *clkset_sclk_vpll_list[] = {
354 [0] = &clk_vpllsrc.clk,
355 [1] = &clk_fout_vpll,
358 static struct clksrc_sources clkset_sclk_vpll = {
359 .sources = clkset_sclk_vpll_list,
360 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
363 static struct clksrc_clk clk_sclk_vpll = {
367 .sources = &clkset_sclk_vpll,
368 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
371 static struct clk init_clocks_off[] = {
374 .parent = &clk_aclk_100.clk,
375 .enable = exynos4_clk_ip_peril_ctrl,
379 .devname = "s5p-mipi-csis.0",
380 .enable = exynos4_clk_ip_cam_ctrl,
384 .devname = "s5p-mipi-csis.1",
385 .enable = exynos4_clk_ip_cam_ctrl,
389 .devname = "exynos4-fimc.0",
390 .enable = exynos4_clk_ip_cam_ctrl,
394 .devname = "exynos4-fimc.1",
395 .enable = exynos4_clk_ip_cam_ctrl,
399 .devname = "exynos4-fimc.2",
400 .enable = exynos4_clk_ip_cam_ctrl,
404 .devname = "exynos4-fimc.3",
405 .enable = exynos4_clk_ip_cam_ctrl,
409 .devname = "exynos4-fb.0",
410 .enable = exynos4_clk_ip_lcd0_ctrl,
414 .devname = "exynos4-fb.1",
415 .enable = exynos4_clk_ip_lcd1_ctrl,
419 .parent = &clk_aclk_133.clk,
420 .enable = exynos4_clk_ip_fsys_ctrl,
424 .devname = "s3c-sdhci.0",
425 .parent = &clk_aclk_133.clk,
426 .enable = exynos4_clk_ip_fsys_ctrl,
430 .devname = "s3c-sdhci.1",
431 .parent = &clk_aclk_133.clk,
432 .enable = exynos4_clk_ip_fsys_ctrl,
436 .devname = "s3c-sdhci.2",
437 .parent = &clk_aclk_133.clk,
438 .enable = exynos4_clk_ip_fsys_ctrl,
442 .devname = "s3c-sdhci.3",
443 .parent = &clk_aclk_133.clk,
444 .enable = exynos4_clk_ip_fsys_ctrl,
448 .parent = &clk_aclk_133.clk,
449 .enable = exynos4_clk_ip_fsys_ctrl,
453 .parent = &clk_aclk_133.clk,
454 .enable = exynos4_clk_ip_fsys_ctrl,
455 .ctrlbit = (1 << 10),
458 .devname = "s3c-pl330.0",
459 .enable = exynos4_clk_ip_fsys_ctrl,
463 .devname = "s3c-pl330.1",
464 .enable = exynos4_clk_ip_fsys_ctrl,
468 .enable = exynos4_clk_ip_peril_ctrl,
469 .ctrlbit = (1 << 15),
472 .enable = exynos4_clk_ip_perir_ctrl,
473 .ctrlbit = (1 << 16),
476 .enable = exynos4_clk_ip_perir_ctrl,
477 .ctrlbit = (1 << 15),
480 .parent = &clk_aclk_100.clk,
481 .enable = exynos4_clk_ip_perir_ctrl,
482 .ctrlbit = (1 << 14),
485 .enable = exynos4_clk_ip_fsys_ctrl ,
486 .ctrlbit = (1 << 12),
489 .enable = exynos4_clk_ip_fsys_ctrl,
490 .ctrlbit = (1 << 13),
493 .devname = "s3c64xx-spi.0",
494 .enable = exynos4_clk_ip_peril_ctrl,
495 .ctrlbit = (1 << 16),
498 .devname = "s3c64xx-spi.1",
499 .enable = exynos4_clk_ip_peril_ctrl,
500 .ctrlbit = (1 << 17),
503 .devname = "s3c64xx-spi.2",
504 .enable = exynos4_clk_ip_peril_ctrl,
505 .ctrlbit = (1 << 18),
508 .devname = "samsung-i2s.0",
509 .enable = exynos4_clk_ip_peril_ctrl,
510 .ctrlbit = (1 << 19),
513 .devname = "samsung-i2s.1",
514 .enable = exynos4_clk_ip_peril_ctrl,
515 .ctrlbit = (1 << 20),
518 .devname = "samsung-i2s.2",
519 .enable = exynos4_clk_ip_peril_ctrl,
520 .ctrlbit = (1 << 21),
523 .devname = "samsung-ac97",
524 .enable = exynos4_clk_ip_peril_ctrl,
525 .ctrlbit = (1 << 27),
528 .enable = exynos4_clk_ip_image_ctrl,
532 .devname = "s5p-mfc",
533 .enable = exynos4_clk_ip_mfc_ctrl,
537 .devname = "s3c2440-i2c.0",
538 .parent = &clk_aclk_100.clk,
539 .enable = exynos4_clk_ip_peril_ctrl,
543 .devname = "s3c2440-i2c.1",
544 .parent = &clk_aclk_100.clk,
545 .enable = exynos4_clk_ip_peril_ctrl,
549 .devname = "s3c2440-i2c.2",
550 .parent = &clk_aclk_100.clk,
551 .enable = exynos4_clk_ip_peril_ctrl,
555 .devname = "s3c2440-i2c.3",
556 .parent = &clk_aclk_100.clk,
557 .enable = exynos4_clk_ip_peril_ctrl,
561 .devname = "s3c2440-i2c.4",
562 .parent = &clk_aclk_100.clk,
563 .enable = exynos4_clk_ip_peril_ctrl,
564 .ctrlbit = (1 << 10),
567 .devname = "s3c2440-i2c.5",
568 .parent = &clk_aclk_100.clk,
569 .enable = exynos4_clk_ip_peril_ctrl,
570 .ctrlbit = (1 << 11),
573 .devname = "s3c2440-i2c.6",
574 .parent = &clk_aclk_100.clk,
575 .enable = exynos4_clk_ip_peril_ctrl,
576 .ctrlbit = (1 << 12),
579 .devname = "s3c2440-i2c.7",
580 .parent = &clk_aclk_100.clk,
581 .enable = exynos4_clk_ip_peril_ctrl,
582 .ctrlbit = (1 << 13),
584 .name = "SYSMMU_MDMA",
585 .enable = exynos4_clk_ip_image_ctrl,
588 .name = "SYSMMU_FIMC0",
589 .enable = exynos4_clk_ip_cam_ctrl,
592 .name = "SYSMMU_FIMC1",
593 .enable = exynos4_clk_ip_cam_ctrl,
596 .name = "SYSMMU_FIMC2",
597 .enable = exynos4_clk_ip_cam_ctrl,
600 .name = "SYSMMU_FIMC3",
601 .enable = exynos4_clk_ip_cam_ctrl,
602 .ctrlbit = (1 << 10),
604 .name = "SYSMMU_JPEG",
605 .enable = exynos4_clk_ip_cam_ctrl,
606 .ctrlbit = (1 << 11),
608 .name = "SYSMMU_FIMD0",
609 .enable = exynos4_clk_ip_lcd0_ctrl,
612 .name = "SYSMMU_FIMD1",
613 .enable = exynos4_clk_ip_lcd1_ctrl,
616 .name = "SYSMMU_PCIe",
617 .enable = exynos4_clk_ip_fsys_ctrl,
618 .ctrlbit = (1 << 18),
620 .name = "SYSMMU_G2D",
621 .enable = exynos4_clk_ip_image_ctrl,
624 .name = "SYSMMU_ROTATOR",
625 .enable = exynos4_clk_ip_image_ctrl,
629 .enable = exynos4_clk_ip_tv_ctrl,
632 .name = "SYSMMU_MFC_L",
633 .enable = exynos4_clk_ip_mfc_ctrl,
636 .name = "SYSMMU_MFC_R",
637 .enable = exynos4_clk_ip_mfc_ctrl,
642 static struct clk init_clocks[] = {
645 .devname = "s5pv210-uart.0",
646 .enable = exynos4_clk_ip_peril_ctrl,
650 .devname = "s5pv210-uart.1",
651 .enable = exynos4_clk_ip_peril_ctrl,
655 .devname = "s5pv210-uart.2",
656 .enable = exynos4_clk_ip_peril_ctrl,
660 .devname = "s5pv210-uart.3",
661 .enable = exynos4_clk_ip_peril_ctrl,
665 .devname = "s5pv210-uart.4",
666 .enable = exynos4_clk_ip_peril_ctrl,
670 .devname = "s5pv210-uart.5",
671 .enable = exynos4_clk_ip_peril_ctrl,
676 static struct clk *clkset_group_list[] = {
677 [0] = &clk_ext_xtal_mux,
679 [2] = &clk_sclk_hdmi27m,
680 [3] = &clk_sclk_usbphy0,
681 [4] = &clk_sclk_usbphy1,
682 [5] = &clk_sclk_hdmiphy,
683 [6] = &clk_mout_mpll.clk,
684 [7] = &clk_mout_epll.clk,
685 [8] = &clk_sclk_vpll.clk,
688 static struct clksrc_sources clkset_group = {
689 .sources = clkset_group_list,
690 .nr_sources = ARRAY_SIZE(clkset_group_list),
693 static struct clk *clkset_mout_g2d0_list[] = {
694 [0] = &clk_mout_mpll.clk,
695 [1] = &clk_sclk_apll.clk,
698 static struct clksrc_sources clkset_mout_g2d0 = {
699 .sources = clkset_mout_g2d0_list,
700 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
703 static struct clksrc_clk clk_mout_g2d0 = {
707 .sources = &clkset_mout_g2d0,
708 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
711 static struct clk *clkset_mout_g2d1_list[] = {
712 [0] = &clk_mout_epll.clk,
713 [1] = &clk_sclk_vpll.clk,
716 static struct clksrc_sources clkset_mout_g2d1 = {
717 .sources = clkset_mout_g2d1_list,
718 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
721 static struct clksrc_clk clk_mout_g2d1 = {
725 .sources = &clkset_mout_g2d1,
726 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
729 static struct clk *clkset_mout_g2d_list[] = {
730 [0] = &clk_mout_g2d0.clk,
731 [1] = &clk_mout_g2d1.clk,
734 static struct clksrc_sources clkset_mout_g2d = {
735 .sources = clkset_mout_g2d_list,
736 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
739 static struct clk *clkset_mout_mfc0_list[] = {
740 [0] = &clk_mout_mpll.clk,
741 [1] = &clk_sclk_apll.clk,
744 static struct clksrc_sources clkset_mout_mfc0 = {
745 .sources = clkset_mout_mfc0_list,
746 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
749 static struct clksrc_clk clk_mout_mfc0 = {
753 .sources = &clkset_mout_mfc0,
754 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
757 static struct clk *clkset_mout_mfc1_list[] = {
758 [0] = &clk_mout_epll.clk,
759 [1] = &clk_sclk_vpll.clk,
762 static struct clksrc_sources clkset_mout_mfc1 = {
763 .sources = clkset_mout_mfc1_list,
764 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
767 static struct clksrc_clk clk_mout_mfc1 = {
771 .sources = &clkset_mout_mfc1,
772 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
775 static struct clk *clkset_mout_mfc_list[] = {
776 [0] = &clk_mout_mfc0.clk,
777 [1] = &clk_mout_mfc1.clk,
780 static struct clksrc_sources clkset_mout_mfc = {
781 .sources = clkset_mout_mfc_list,
782 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
785 static struct clksrc_clk clk_dout_mmc0 = {
789 .sources = &clkset_group,
790 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
791 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
794 static struct clksrc_clk clk_dout_mmc1 = {
798 .sources = &clkset_group,
799 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
800 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
803 static struct clksrc_clk clk_dout_mmc2 = {
807 .sources = &clkset_group,
808 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
809 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
812 static struct clksrc_clk clk_dout_mmc3 = {
816 .sources = &clkset_group,
817 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
818 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
821 static struct clksrc_clk clk_dout_mmc4 = {
825 .sources = &clkset_group,
826 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
827 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
830 static struct clksrc_clk clksrcs[] = {
834 .devname = "s5pv210-uart.0",
835 .enable = exynos4_clksrc_mask_peril0_ctrl,
838 .sources = &clkset_group,
839 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
840 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
844 .devname = "s5pv210-uart.1",
845 .enable = exynos4_clksrc_mask_peril0_ctrl,
848 .sources = &clkset_group,
849 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
850 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
854 .devname = "s5pv210-uart.2",
855 .enable = exynos4_clksrc_mask_peril0_ctrl,
858 .sources = &clkset_group,
859 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
860 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
864 .devname = "s5pv210-uart.3",
865 .enable = exynos4_clksrc_mask_peril0_ctrl,
866 .ctrlbit = (1 << 12),
868 .sources = &clkset_group,
869 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
870 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
874 .enable = exynos4_clksrc_mask_peril0_ctrl,
875 .ctrlbit = (1 << 24),
877 .sources = &clkset_group,
878 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
879 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
883 .devname = "s5p-mipi-csis.0",
884 .enable = exynos4_clksrc_mask_cam_ctrl,
885 .ctrlbit = (1 << 24),
887 .sources = &clkset_group,
888 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
889 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
893 .devname = "s5p-mipi-csis.1",
894 .enable = exynos4_clksrc_mask_cam_ctrl,
895 .ctrlbit = (1 << 28),
897 .sources = &clkset_group,
898 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
899 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
903 .devname = "exynos4-fimc.0",
904 .enable = exynos4_clksrc_mask_cam_ctrl,
905 .ctrlbit = (1 << 16),
907 .sources = &clkset_group,
908 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
909 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
913 .devname = "exynos4-fimc.1",
914 .enable = exynos4_clksrc_mask_cam_ctrl,
915 .ctrlbit = (1 << 20),
917 .sources = &clkset_group,
918 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
919 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
923 .devname = "exynos4-fimc.0",
924 .enable = exynos4_clksrc_mask_cam_ctrl,
927 .sources = &clkset_group,
928 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
929 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
933 .devname = "exynos4-fimc.1",
934 .enable = exynos4_clksrc_mask_cam_ctrl,
937 .sources = &clkset_group,
938 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
939 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
943 .devname = "exynos4-fimc.2",
944 .enable = exynos4_clksrc_mask_cam_ctrl,
947 .sources = &clkset_group,
948 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
949 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
953 .devname = "exynos4-fimc.3",
954 .enable = exynos4_clksrc_mask_cam_ctrl,
955 .ctrlbit = (1 << 12),
957 .sources = &clkset_group,
958 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
959 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
963 .devname = "exynos4-fb.0",
964 .enable = exynos4_clksrc_mask_lcd0_ctrl,
967 .sources = &clkset_group,
968 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
969 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
973 .devname = "exynos4-fb.1",
974 .enable = exynos4_clksrc_mask_lcd1_ctrl,
977 .sources = &clkset_group,
978 .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 },
979 .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 },
983 .enable = exynos4_clksrc_mask_fsys_ctrl,
984 .ctrlbit = (1 << 24),
986 .sources = &clkset_mout_corebus,
987 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 },
988 .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 },
992 .devname = "s3c64xx-spi.0",
993 .enable = exynos4_clksrc_mask_peril1_ctrl,
994 .ctrlbit = (1 << 16),
996 .sources = &clkset_group,
997 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
998 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1002 .devname = "s3c64xx-spi.1",
1003 .enable = exynos4_clksrc_mask_peril1_ctrl,
1004 .ctrlbit = (1 << 20),
1006 .sources = &clkset_group,
1007 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1008 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1012 .devname = "s3c64xx-spi.2",
1013 .enable = exynos4_clksrc_mask_peril1_ctrl,
1014 .ctrlbit = (1 << 24),
1016 .sources = &clkset_group,
1017 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1018 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1021 .name = "sclk_fimg2d",
1023 .sources = &clkset_mout_g2d,
1024 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1025 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1029 .devname = "s5p-mfc",
1031 .sources = &clkset_mout_mfc,
1032 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1033 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1037 .devname = "s3c-sdhci.0",
1038 .parent = &clk_dout_mmc0.clk,
1039 .enable = exynos4_clksrc_mask_fsys_ctrl,
1040 .ctrlbit = (1 << 0),
1042 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1046 .devname = "s3c-sdhci.1",
1047 .parent = &clk_dout_mmc1.clk,
1048 .enable = exynos4_clksrc_mask_fsys_ctrl,
1049 .ctrlbit = (1 << 4),
1051 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1055 .devname = "s3c-sdhci.2",
1056 .parent = &clk_dout_mmc2.clk,
1057 .enable = exynos4_clksrc_mask_fsys_ctrl,
1058 .ctrlbit = (1 << 8),
1060 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1064 .devname = "s3c-sdhci.3",
1065 .parent = &clk_dout_mmc3.clk,
1066 .enable = exynos4_clksrc_mask_fsys_ctrl,
1067 .ctrlbit = (1 << 12),
1069 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1072 .name = "sclk_dwmmc",
1073 .parent = &clk_dout_mmc4.clk,
1074 .enable = exynos4_clksrc_mask_fsys_ctrl,
1075 .ctrlbit = (1 << 16),
1077 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1081 /* Clock initialization code */
1082 static struct clksrc_clk *sysclks[] = {
1115 static int xtal_rate;
1117 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1119 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1122 static struct clk_ops exynos4_fout_apll_ops = {
1123 .get_rate = exynos4_fout_apll_get_rate,
1126 void __init_or_cpufreq exynos4_setup_clocks(void)
1128 struct clk *xtal_clk;
1133 unsigned long vpllsrc;
1135 unsigned long armclk;
1136 unsigned long sclk_dmc;
1137 unsigned long aclk_200;
1138 unsigned long aclk_100;
1139 unsigned long aclk_160;
1140 unsigned long aclk_133;
1143 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1145 xtal_clk = clk_get(NULL, "xtal");
1146 BUG_ON(IS_ERR(xtal_clk));
1148 xtal = clk_get_rate(xtal_clk);
1154 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1156 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
1157 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
1158 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1159 __raw_readl(S5P_EPLL_CON1), pll_4600);
1161 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1162 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1163 __raw_readl(S5P_VPLL_CON1), pll_4650);
1165 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1166 clk_fout_mpll.rate = mpll;
1167 clk_fout_epll.rate = epll;
1168 clk_fout_vpll.rate = vpll;
1170 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1171 apll, mpll, epll, vpll);
1173 armclk = clk_get_rate(&clk_armclk.clk);
1174 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1176 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1177 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1178 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1179 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1181 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1182 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1183 armclk, sclk_dmc, aclk_200,
1184 aclk_100, aclk_160, aclk_133);
1186 clk_f.rate = armclk;
1187 clk_h.rate = sclk_dmc;
1188 clk_p.rate = aclk_100;
1190 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1191 s3c_set_clksrc(&clksrcs[ptr], true);
1194 static struct clk *clks[] __initdata = {
1195 /* Nothing here yet */
1198 void __init exynos4_register_clocks(void)
1202 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1204 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1205 s3c_register_clksrc(sysclks[ptr], 1);
1207 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1208 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1210 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1211 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));