2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * arch/arm/mach-exynos/mcpm-exynos.c
7 * Based on arch/arm/mach-vexpress/dcscb.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/arm-cci.h>
15 #include <linux/delay.h>
17 #include <linux/of_address.h>
19 #include <asm/cputype.h>
26 #define EXYNOS5420_CPUS_PER_CLUSTER 4
27 #define EXYNOS5420_NR_CLUSTERS 2
29 #define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9)
30 #define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
31 #define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
34 * The common v7_exit_coherency_flush API could not be used because of the
35 * Erratum 799270 workaround. This macro is the same as the common one (in
36 * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
38 #define exynos_v7_exit_coherency_flush(level) \
40 "stmfd sp!, {fp, ip}\n\t"\
41 "mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" \
42 "bic r0, r0, #"__stringify(CR_C)"\n\t" \
43 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \
45 "bl v7_flush_dcache_"__stringify(level)"\n\t" \
47 "mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \
48 "bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \
49 /* Dummy Load of a device register to avoid Erratum 799270 */ \
51 "and r4, r4, #0\n\t" \
52 "orr r0, r0, r4\n\t" \
53 "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" \
56 "ldmfd sp!, {fp, ip}" \
58 : "Ir" (pmu_base_addr + S5P_INFORM0) \
59 : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
60 "r9", "r10", "lr", "memory")
63 * We can't use regular spinlocks. In the switcher case, it is possible
64 * for an outbound CPU to call power_down() after its inbound counterpart
65 * is already live using the same logical CPU number which trips lockdep
68 static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
70 cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
72 #define exynos_cluster_usecnt(cluster) \
73 (cpu_use_count[0][cluster] + \
74 cpu_use_count[1][cluster] + \
75 cpu_use_count[2][cluster] + \
76 cpu_use_count[3][cluster])
78 #define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
80 static int exynos_power_up(unsigned int cpu, unsigned int cluster)
82 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
84 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
85 if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
86 cluster >= EXYNOS5420_NR_CLUSTERS)
90 * Since this is called with IRQs enabled, and no arch_spin_lock_irq
91 * variant exists, we need to disable IRQs manually here.
94 arch_spin_lock(&exynos_mcpm_lock);
96 cpu_use_count[cpu][cluster]++;
97 if (cpu_use_count[cpu][cluster] == 1) {
98 bool was_cluster_down =
99 (exynos_cluster_usecnt(cluster) == 1);
102 * Turn on the cluster (L2/COMMON) and then power on the
105 if (was_cluster_down)
106 exynos_cluster_power_up(cluster);
108 exynos_cpu_power_up(cpunr);
109 } else if (cpu_use_count[cpu][cluster] != 2) {
111 * The only possible values are:
114 * 2 = CPU requested to be up before it had a chance
115 * to actually make itself down.
116 * Any other value is a bug.
121 arch_spin_unlock(&exynos_mcpm_lock);
128 * NOTE: This function requires the stack data to be visible through power down
129 * and can only be executed on processors like A15 and A7 that hit the cache
130 * with the C bit clear in the SCTLR register.
132 static void exynos_power_down(void)
134 unsigned int mpidr, cpu, cluster;
135 bool last_man = false, skip_wfi = false;
138 mpidr = read_cpuid_mpidr();
139 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
140 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
141 cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
143 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
144 BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
145 cluster >= EXYNOS5420_NR_CLUSTERS);
147 __mcpm_cpu_going_down(cpu, cluster);
149 arch_spin_lock(&exynos_mcpm_lock);
150 BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
151 cpu_use_count[cpu][cluster]--;
152 if (cpu_use_count[cpu][cluster] == 0) {
153 exynos_cpu_power_down(cpunr);
155 if (exynos_cluster_unused(cluster)) {
156 exynos_cluster_power_down(cluster);
159 } else if (cpu_use_count[cpu][cluster] == 1) {
161 * A power_up request went ahead of us.
162 * Even if we do not want to shut this CPU down,
163 * the caller expects a certain state as if the WFI
164 * was aborted. So let's continue with cache cleaning.
171 if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
172 arch_spin_unlock(&exynos_mcpm_lock);
174 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
176 * On the Cortex-A15 we need to disable
177 * L2 prefetching before flushing the cache.
180 "mcr p15, 1, %0, c15, c0, 3\n\t"
186 /* Flush all cache levels for this cluster. */
187 exynos_v7_exit_coherency_flush(all);
190 * Disable cluster-level coherency by masking
191 * incoming snoops and DVM messages:
193 cci_disable_port_by_cpu(mpidr);
195 __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
197 arch_spin_unlock(&exynos_mcpm_lock);
199 /* Disable and flush the local CPU cache. */
200 exynos_v7_exit_coherency_flush(louis);
203 __mcpm_cpu_down(cpu, cluster);
205 /* Now we are prepared for power-down, do it: */
209 /* Not dead at this point? Let our caller cope. */
212 static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
214 unsigned int tries = 100;
215 unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
217 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
218 BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
219 cluster >= EXYNOS5420_NR_CLUSTERS);
221 /* Wait for the core state to be OFF */
223 if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
224 if ((exynos_cpu_power_state(cpunr) == 0))
225 return 0; /* success: the CPU is halted */
228 /* Otherwise, wait and retry: */
232 return -ETIMEDOUT; /* timeout */
235 static void exynos_powered_up(void)
237 unsigned int mpidr, cpu, cluster;
239 mpidr = read_cpuid_mpidr();
240 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
241 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
243 arch_spin_lock(&exynos_mcpm_lock);
244 if (cpu_use_count[cpu][cluster] == 0)
245 cpu_use_count[cpu][cluster] = 1;
246 arch_spin_unlock(&exynos_mcpm_lock);
249 static void exynos_suspend(u64 residency)
251 unsigned int mpidr, cpunr;
256 * Execution reaches here only if cpu did not power down.
257 * Hence roll back the changes done in exynos_power_down function.
259 * CAUTION: "This function requires the stack data to be visible through
260 * power down and can only be executed on processors like A15 and A7
261 * that hit the cache with the C bit clear in the SCTLR register."
263 mpidr = read_cpuid_mpidr();
264 cpunr = exynos_pmu_cpunr(mpidr);
266 exynos_cpu_power_up(cpunr);
269 static const struct mcpm_platform_ops exynos_power_ops = {
270 .power_up = exynos_power_up,
271 .power_down = exynos_power_down,
272 .wait_for_powerdown = exynos_wait_for_powerdown,
273 .suspend = exynos_suspend,
274 .powered_up = exynos_powered_up,
277 static void __init exynos_mcpm_usage_count_init(void)
279 unsigned int mpidr, cpu, cluster;
281 mpidr = read_cpuid_mpidr();
282 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
283 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
285 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
286 BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
287 cluster >= EXYNOS5420_NR_CLUSTERS);
289 cpu_use_count[cpu][cluster] = 1;
293 * Enable cluster-level coherency, in preparation for turning on the MMU.
295 static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
300 "b cci_enable_port_for_self");
303 static void __init exynos_cache_off(void)
305 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
306 /* disable L2 prefetching on the Cortex-A15 */
308 "mcr p15, 1, %0, c15, c0, 3\n\t"
313 exynos_v7_exit_coherency_flush(all);
316 static const struct of_device_id exynos_dt_mcpm_match[] = {
317 { .compatible = "samsung,exynos5420" },
318 { .compatible = "samsung,exynos5800" },
322 static int __init exynos_mcpm_init(void)
324 struct device_node *node;
325 void __iomem *ns_sram_base_addr;
326 unsigned int value, i;
329 node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
337 node = of_find_compatible_node(NULL, NULL,
338 "samsung,exynos4210-sysram-ns");
342 ns_sram_base_addr = of_iomap(node, 0);
344 if (!ns_sram_base_addr) {
345 pr_err("failed to map non-secure iRAM base address\n");
350 * To increase the stability of KFC reset we need to program
351 * the PMU SPARE3 register
353 pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
355 exynos_mcpm_usage_count_init();
357 ret = mcpm_platform_register(&exynos_power_ops);
359 ret = mcpm_sync_init(exynos_pm_power_up_setup);
361 ret = mcpm_loopback(exynos_cache_off); /* turn on the CCI */
363 iounmap(ns_sram_base_addr);
369 pr_info("Exynos MCPM support installed\n");
372 * On Exynos5420/5800 for the A15 and A7 clusters:
374 * EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores
375 * in a cluster are turned off before turning off the cluster L2.
377 * EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered
378 * off before waking it up.
380 * EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be
381 * turned on before the first man is powered up.
383 for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) {
384 value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i));
385 value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN |
386 EXYNOS5420_USE_ARM_CORE_DOWN_STATE |
387 EXYNOS5420_USE_L2_COMMON_UP_STATE;
388 pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i));
392 * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
393 * as part of secondary_cpu_start(). Let's redirect it to the
394 * mcpm_entry_point().
396 __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */
397 __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */
398 __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
400 iounmap(ns_sram_base_addr);
405 early_initcall(exynos_mcpm_init);