arch/arm/mach-exynos/exynos.c

   1 /*
   2  * SAMSUNG EXYNOS Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/serial_s3c.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_fdt.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22
  23 #include <asm/cacheflush.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/memory.h>
  28
  29 #include <plat/cpu.h>
  30
  31 #include "common.h"
  32 #include "mfc.h"
  33 #include "regs-pmu.h"
  34
  35 #define L2_AUX_VAL 0x7C470001
  36 #define L2_AUX_MASK 0xC200ffff
  37
  38 static struct map_desc exynos4_iodesc[] __initdata = {
  39         {
  40                 .virtual        = (unsigned long)S3C_VA_SYS,
  41                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  42                 .length         = SZ_64K,
  43                 .type           = MT_DEVICE,
  44         }, {
  45                 .virtual        = (unsigned long)S3C_VA_TIMER,
  46                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
  47                 .length         = SZ_16K,
  48                 .type           = MT_DEVICE,
  49         }, {
  50                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
  51                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
  52                 .length         = SZ_4K,
  53                 .type           = MT_DEVICE,
  54         }, {
  55                 .virtual        = (unsigned long)S5P_VA_SROMC,
  56                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
  57                 .length         = SZ_4K,
  58                 .type           = MT_DEVICE,
  59         }, {
  60                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
  61                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
  62                 .length         = SZ_4K,
  63                 .type           = MT_DEVICE,
  64         }, {
  65                 .virtual        = (unsigned long)S5P_VA_PMU,
  66                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
  67                 .length         = SZ_64K,
  68                 .type           = MT_DEVICE,
  69         }, {
  70                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
  71                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
  72                 .length         = SZ_4K,
  73                 .type           = MT_DEVICE,
  74         }, {
  75                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
  76                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
  77                 .length         = SZ_64K,
  78                 .type           = MT_DEVICE,
  79         }, {
  80                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
  81                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
  82                 .length         = SZ_64K,
  83                 .type           = MT_DEVICE,
  84         }, {
  85                 .virtual        = (unsigned long)S5P_VA_CMU,
  86                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  87                 .length         = SZ_128K,
  88                 .type           = MT_DEVICE,
  89         }, {
  90                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  91                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  92                 .length         = SZ_8K,
  93                 .type           = MT_DEVICE,
  94         }, {
  95                 .virtual        = (unsigned long)S5P_VA_L2CC,
  96                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
  97                 .length         = SZ_4K,
  98                 .type           = MT_DEVICE,
  99         }, {
 100                 .virtual        = (unsigned long)S5P_VA_DMC0,
 101                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 102                 .length         = SZ_64K,
 103                 .type           = MT_DEVICE,
 104         }, {
 105                 .virtual        = (unsigned long)S5P_VA_DMC1,
 106                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 107                 .length         = SZ_64K,
 108                 .type           = MT_DEVICE,
 109         }, {
 110                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 111                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 112                 .length         = SZ_4K,
 113                 .type           = MT_DEVICE,
 114         },
 115 };
 116
 117 static struct map_desc exynos5_iodesc[] __initdata = {
 118         {
 119                 .virtual        = (unsigned long)S3C_VA_SYS,
 120                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 121                 .length         = SZ_64K,
 122                 .type           = MT_DEVICE,
 123         }, {
 124                 .virtual        = (unsigned long)S3C_VA_TIMER,
 125                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 126                 .length         = SZ_16K,
 127                 .type           = MT_DEVICE,
 128         }, {
 129                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 130                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 131                 .length         = SZ_4K,
 132                 .type           = MT_DEVICE,
 133         }, {
 134                 .virtual        = (unsigned long)S5P_VA_SROMC,
 135                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE,
 138         }, {
 139                 .virtual        = (unsigned long)S5P_VA_CMU,
 140                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 141                 .length         = 144 * SZ_1K,
 142                 .type           = MT_DEVICE,
 143         }, {
 144                 .virtual        = (unsigned long)S5P_VA_PMU,
 145                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 146                 .length         = SZ_64K,
 147                 .type           = MT_DEVICE,
 148         },
 149 };
 150
 151 void exynos_restart(enum reboot_mode mode, const char *cmd)
 152 {
 153         struct device_node *np;
 154         u32 val = 0x1;
 155         void __iomem *addr = EXYNOS_SWRESET;
 156
 157         if (of_machine_is_compatible("samsung,exynos5440")) {
 158                 u32 status;
 159                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 160
 161                 addr = of_iomap(np, 0) + 0xbc;
 162                 status = __raw_readl(addr);
 163
 164                 addr = of_iomap(np, 0) + 0xcc;
 165                 val = __raw_readl(addr);
 166
 167                 val = (val & 0xffff0000) | (status & 0xffff);
 168         }
 169
 170         __raw_writel(val, addr);
 171 }
 172
 173 static struct platform_device exynos_cpuidle = {
 174         .name           = "exynos_cpuidle",
 175         .id             = -1,
 176 };
 177
 178 void __init exynos_cpuidle_init(void)
 179 {
 180         platform_device_register(&exynos_cpuidle);
 181 }
 182
 183 void __init exynos_cpufreq_init(void)
 184 {
 185         platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
 186 }
 187
 188 void __init exynos_init_late(void)
 189 {
 190         if (of_machine_is_compatible("samsung,exynos5440"))
 191                 /* to be supported later */
 192                 return;
 193
 194         pm_genpd_poweroff_unused();
 195         exynos_pm_init();
 196 }
 197
 198 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 199                                         int depth, void *data)
 200 {
 201         struct map_desc iodesc;
 202         __be32 *reg;
 203         unsigned long len;
 204
 205         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 206                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 207                 return 0;
 208
 209         reg = of_get_flat_dt_prop(node, "reg", &len);
 210         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 211                 return 0;
 212
 213         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 214         iodesc.length = be32_to_cpu(reg[1]) - 1;
 215         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 216         iodesc.type = MT_DEVICE;
 217         iotable_init(&iodesc, 1);
 218         return 1;
 219 }
 220
 221 /*
 222  * exynos_map_io
 223  *
 224  * register the standard cpu IO areas
 225  */
 226 static void __init exynos_map_io(void)
 227 {
 228         if (soc_is_exynos4())
 229                 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 230
 231         if (soc_is_exynos5())
 232                 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 233 }
 234
 235 void __init exynos_init_io(void)
 236 {
 237         debug_ll_io_init();
 238
 239         of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 240
 241         /* detect cpu id and rev. */
 242         s5p_init_cpu(S5P_VA_CHIPID);
 243
 244         exynos_map_io();
 245 }
 246
 247 struct bus_type exynos_subsys = {
 248         .name           = "exynos-core",
 249         .dev_name       = "exynos-core",
 250 };
 251
 252 static int __init exynos_core_init(void)
 253 {
 254         return subsys_system_register(&exynos_subsys, NULL);
 255 }
 256 core_initcall(exynos_core_init);
 257
 258 static int __init exynos4_l2x0_cache_init(void)
 259 {
 260         int ret;
 261
 262         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 263         if (ret)
 264                 return ret;
 265
 266         if (IS_ENABLED(CONFIG_S5P_SLEEP)) {
 267                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 268                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 269         }
 270         return 0;
 271 }
 272 early_initcall(exynos4_l2x0_cache_init);
 273
 274 static void __init exynos_dt_machine_init(void)
 275 {
 276         struct device_node *i2c_np;
 277         const char *i2c_compat = "samsung,s3c2440-i2c";
 278         unsigned int tmp;
 279         int id;
 280
 281         /*
 282          * Exynos5's legacy i2c controller and new high speed i2c
 283          * controller have muxed interrupt sources. By default the
 284          * interrupts for 4-channel HS-I2C controller are enabled.
 285          * If node for first four channels of legacy i2c controller
 286          * are available then re-configure the interrupts via the
 287          * system register.
 288          */
 289         if (soc_is_exynos5()) {
 290                 for_each_compatible_node(i2c_np, NULL, i2c_compat) {
 291                         if (of_device_is_available(i2c_np)) {
 292                                 id = of_alias_get_id(i2c_np, "i2c");
 293                                 if (id < 4) {
 294                                         tmp = readl(EXYNOS5_SYS_I2C_CFG);
 295                                         writel(tmp & ~(0x1 << id),
 296                                                         EXYNOS5_SYS_I2C_CFG);
 297                                 }
 298                         }
 299                 }
 300         }
 301
 302         exynos_cpuidle_init();
 303         exynos_cpufreq_init();
 304
 305         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 306 }
 307
 308 static char const *exynos_dt_compat[] __initconst = {
 309         "samsung,exynos4",
 310         "samsung,exynos4210",
 311         "samsung,exynos4212",
 312         "samsung,exynos4412",
 313         "samsung,exynos5",
 314         "samsung,exynos5250",
 315         "samsung,exynos5420",
 316         "samsung,exynos5440",
 317         NULL
 318 };
 319
 320 static void __init exynos_reserve(void)
 321 {
 322 #ifdef CONFIG_S5P_DEV_MFC
 323         int i;
 324         char *mfc_mem[] = {
 325                 "samsung,mfc-v5",
 326                 "samsung,mfc-v6",
 327                 "samsung,mfc-v7",
 328         };
 329
 330         for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
 331                 if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
 332                         break;
 333 #endif
 334 }
 335
 336 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
 337         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
 338         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 339         .smp            = smp_ops(exynos_smp_ops),
 340         .map_io         = exynos_init_io,
 341         .init_early     = exynos_firmware_init,
 342         .init_machine   = exynos_dt_machine_init,
 343         .init_late      = exynos_init_late,
 344         .dt_compat      = exynos_dt_compat,
 345         .restart        = exynos_restart,
 346         .reserve        = exynos_reserve,
 347 MACHINE_END