arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/sched.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22
  23 #include <asm/proc-fns.h>
  24 #include <asm/exception.h>
  25 #include <asm/hardware/cache-l2x0.h>
  26 #include <asm/hardware/gic.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/mach/irq.h>
  29 #include <asm/cacheflush.h>
  30
  31 #include <mach/regs-irq.h>
  32 #include <mach/regs-pmu.h>
  33 #include <mach/regs-gpio.h>
  34 #include <mach/pmu.h>
  35
  36 #include <plat/cpu.h>
  37 #include <plat/clock.h>
  38 #include <plat/devs.h>
  39 #include <plat/pm.h>
  40 #include <plat/sdhci.h>
  41 #include <plat/gpio-cfg.h>
  42 #include <plat/adc-core.h>
  43 #include <plat/fb-core.h>
  44 #include <plat/fimc-core.h>
  45 #include <plat/iic-core.h>
  46 #include <plat/tv-core.h>
  47 #include <plat/regs-serial.h>
  48
  49 #include "common.h"
  50 #define L2_AUX_VAL 0x7C470001
  51 #define L2_AUX_MASK 0xC200ffff
  52
  53 static const char name_exynos4210[] = "EXYNOS4210";
  54 static const char name_exynos4212[] = "EXYNOS4212";
  55 static const char name_exynos4412[] = "EXYNOS4412";
  56 static const char name_exynos5250[] = "EXYNOS5250";
  57
  58 static void exynos4_map_io(void);
  59 static void exynos5_map_io(void);
  60 static void exynos4_init_clocks(int xtal);
  61 static void exynos5_init_clocks(int xtal);
  62 static void exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  63 static int exynos_init(void);
  64
  65 static struct cpu_table cpu_ids[] __initdata = {
  66         {
  67                 .idcode         = EXYNOS4210_CPU_ID,
  68                 .idmask         = EXYNOS4_CPU_MASK,
  69                 .map_io         = exynos4_map_io,
  70                 .init_clocks    = exynos4_init_clocks,
  71                 .init_uarts     = exynos_init_uarts,
  72                 .init           = exynos_init,
  73                 .name           = name_exynos4210,
  74         }, {
  75                 .idcode         = EXYNOS4212_CPU_ID,
  76                 .idmask         = EXYNOS4_CPU_MASK,
  77                 .map_io         = exynos4_map_io,
  78                 .init_clocks    = exynos4_init_clocks,
  79                 .init_uarts     = exynos_init_uarts,
  80                 .init           = exynos_init,
  81                 .name           = name_exynos4212,
  82         }, {
  83                 .idcode         = EXYNOS4412_CPU_ID,
  84                 .idmask         = EXYNOS4_CPU_MASK,
  85                 .map_io         = exynos4_map_io,
  86                 .init_clocks    = exynos4_init_clocks,
  87                 .init_uarts     = exynos_init_uarts,
  88                 .init           = exynos_init,
  89                 .name           = name_exynos4412,
  90         }, {
  91                 .idcode         = EXYNOS5250_SOC_ID,
  92                 .idmask         = EXYNOS5_SOC_MASK,
  93                 .map_io         = exynos5_map_io,
  94                 .init_clocks    = exynos5_init_clocks,
  95                 .init_uarts     = exynos_init_uarts,
  96                 .init           = exynos_init,
  97                 .name           = name_exynos5250,
  98         },
  99 };
 100
 101 /* Initial IO mappings */
 102
 103 static struct map_desc exynos_iodesc[] __initdata = {
 104         {
 105                 .virtual        = (unsigned long)S5P_VA_CHIPID,
 106                 .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE,
 109         },
 110 };
 111
 112 static struct map_desc exynos4_iodesc[] __initdata = {
 113         {
 114                 .virtual        = (unsigned long)S3C_VA_SYS,
 115                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
 116                 .length         = SZ_64K,
 117                 .type           = MT_DEVICE,
 118         }, {
 119                 .virtual        = (unsigned long)S3C_VA_TIMER,
 120                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 121                 .length         = SZ_16K,
 122                 .type           = MT_DEVICE,
 123         }, {
 124                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 125                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 126                 .length         = SZ_4K,
 127                 .type           = MT_DEVICE,
 128         }, {
 129                 .virtual        = (unsigned long)S5P_VA_SROMC,
 130                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 131                 .length         = SZ_4K,
 132                 .type           = MT_DEVICE,
 133         }, {
 134                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 135                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE,
 138         }, {
 139                 .virtual        = (unsigned long)S5P_VA_PMU,
 140                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 141                 .length         = SZ_64K,
 142                 .type           = MT_DEVICE,
 143         }, {
 144                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 145                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 146                 .length         = SZ_4K,
 147                 .type           = MT_DEVICE,
 148         }, {
 149                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 150                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 151                 .length         = SZ_64K,
 152                 .type           = MT_DEVICE,
 153         }, {
 154                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 155                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 156                 .length         = SZ_64K,
 157                 .type           = MT_DEVICE,
 158         }, {
 159                 .virtual        = (unsigned long)S3C_VA_UART,
 160                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 161                 .length         = SZ_512K,
 162                 .type           = MT_DEVICE,
 163         }, {
 164                 .virtual        = (unsigned long)S5P_VA_CMU,
 165                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 166                 .length         = SZ_128K,
 167                 .type           = MT_DEVICE,
 168         }, {
 169                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 170                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 171                 .length         = SZ_8K,
 172                 .type           = MT_DEVICE,
 173         }, {
 174                 .virtual        = (unsigned long)S5P_VA_L2CC,
 175                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 176                 .length         = SZ_4K,
 177                 .type           = MT_DEVICE,
 178         }, {
 179                 .virtual        = (unsigned long)S5P_VA_DMC0,
 180                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 181                 .length         = SZ_64K,
 182                 .type           = MT_DEVICE,
 183         }, {
 184                 .virtual        = (unsigned long)S5P_VA_DMC1,
 185                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
 186                 .length         = SZ_64K,
 187                 .type           = MT_DEVICE,
 188         }, {
 189                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 190                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 191                 .length         = SZ_4K,
 192                 .type           = MT_DEVICE,
 193         },
 194 };
 195
 196 static struct map_desc exynos4_iodesc0[] __initdata = {
 197         {
 198                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 199                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 200                 .length         = SZ_4K,
 201                 .type           = MT_DEVICE,
 202         },
 203 };
 204
 205 static struct map_desc exynos4_iodesc1[] __initdata = {
 206         {
 207                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 208                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 209                 .length         = SZ_4K,
 210                 .type           = MT_DEVICE,
 211         },
 212 };
 213
 214 static struct map_desc exynos5_iodesc[] __initdata = {
 215         {
 216                 .virtual        = (unsigned long)S3C_VA_SYS,
 217                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
 218                 .length         = SZ_64K,
 219                 .type           = MT_DEVICE,
 220         }, {
 221                 .virtual        = (unsigned long)S3C_VA_TIMER,
 222                 .pfn            = __phys_to_pfn(EXYNOS5_PA_TIMER),
 223                 .length         = SZ_16K,
 224                 .type           = MT_DEVICE,
 225         }, {
 226                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 227                 .pfn            = __phys_to_pfn(EXYNOS5_PA_WATCHDOG),
 228                 .length         = SZ_4K,
 229                 .type           = MT_DEVICE,
 230         }, {
 231                 .virtual        = (unsigned long)S5P_VA_SROMC,
 232                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
 233                 .length         = SZ_4K,
 234                 .type           = MT_DEVICE,
 235         }, {
 236                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 237                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
 238                 .length         = SZ_4K,
 239                 .type           = MT_DEVICE,
 240         }, {
 241                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 242                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
 243                 .length         = SZ_4K,
 244                 .type           = MT_DEVICE,
 245         }, {
 246                 .virtual        = (unsigned long)S5P_VA_CMU,
 247                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
 248                 .length         = 144 * SZ_1K,
 249                 .type           = MT_DEVICE,
 250         }, {
 251                 .virtual        = (unsigned long)S5P_VA_PMU,
 252                 .pfn            = __phys_to_pfn(EXYNOS5_PA_PMU),
 253                 .length         = SZ_64K,
 254                 .type           = MT_DEVICE,
 255         }, {
 256                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 257                 .pfn            = __phys_to_pfn(EXYNOS5_PA_COMBINER),
 258                 .length         = SZ_4K,
 259                 .type           = MT_DEVICE,
 260         }, {
 261                 .virtual        = (unsigned long)S3C_VA_UART,
 262                 .pfn            = __phys_to_pfn(EXYNOS5_PA_UART),
 263                 .length         = SZ_512K,
 264                 .type           = MT_DEVICE,
 265         }, {
 266                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 267                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
 268                 .length         = SZ_64K,
 269                 .type           = MT_DEVICE,
 270         }, {
 271                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 272                 .pfn            = __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
 273                 .length         = SZ_64K,
 274                 .type           = MT_DEVICE,
 275         },
 276 };
 277
 278 void exynos4_restart(char mode, const char *cmd)
 279 {
 280         __raw_writel(0x1, S5P_SWRESET);
 281 }
 282
 283 void exynos5_restart(char mode, const char *cmd)
 284 {
 285         __raw_writel(0x1, EXYNOS_SWRESET);
 286 }
 287
 288 /*
 289  * exynos_map_io
 290  *
 291  * register the standard cpu IO areas
 292  */
 293
 294 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 295 {
 296         /* initialize the io descriptors we need for initialization */
 297         iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 298         if (mach_desc)
 299                 iotable_init(mach_desc, size);
 300
 301         /* detect cpu id and rev. */
 302         s5p_init_cpu(S5P_VA_CHIPID);
 303
 304         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 305 }
 306
 307 static void __init exynos4_map_io(void)
 308 {
 309         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 310
 311         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 312                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 313         else
 314                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 315
 316         /* initialize device information early */
 317         exynos4_default_sdhci0();
 318         exynos4_default_sdhci1();
 319         exynos4_default_sdhci2();
 320         exynos4_default_sdhci3();
 321
 322         s3c_adc_setname("samsung-adc-v3");
 323
 324         s3c_fimc_setname(0, "exynos4-fimc");
 325         s3c_fimc_setname(1, "exynos4-fimc");
 326         s3c_fimc_setname(2, "exynos4-fimc");
 327         s3c_fimc_setname(3, "exynos4-fimc");
 328
 329         /* The I2C bus controllers are directly compatible with s3c2440 */
 330         s3c_i2c0_setname("s3c2440-i2c");
 331         s3c_i2c1_setname("s3c2440-i2c");
 332         s3c_i2c2_setname("s3c2440-i2c");
 333
 334         s5p_fb_setname(0, "exynos4-fb");
 335         s5p_hdmi_setname("exynos4-hdmi");
 336 }
 337
 338 static void __init exynos5_map_io(void)
 339 {
 340         iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 341
 342         s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
 343         s3c_device_i2c0.resource[0].end   = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
 344         s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
 345         s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
 346
 347         /* The I2C bus controllers are directly compatible with s3c2440 */
 348         s3c_i2c0_setname("s3c2440-i2c");
 349         s3c_i2c1_setname("s3c2440-i2c");
 350         s3c_i2c2_setname("s3c2440-i2c");
 351 }
 352
 353 static void __init exynos4_init_clocks(int xtal)
 354 {
 355         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 356
 357         s3c24xx_register_baseclocks(xtal);
 358         s5p_register_clocks(xtal);
 359
 360         if (soc_is_exynos4210())
 361                 exynos4210_register_clocks();
 362         else if (soc_is_exynos4212() || soc_is_exynos4412())
 363                 exynos4212_register_clocks();
 364
 365         exynos4_register_clocks();
 366         exynos4_setup_clocks();
 367 }
 368
 369 static void __init exynos5_init_clocks(int xtal)
 370 {
 371         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 372
 373         s3c24xx_register_baseclocks(xtal);
 374         s5p_register_clocks(xtal);
 375
 376         exynos5_register_clocks();
 377         exynos5_setup_clocks();
 378 }
 379
 380 #define COMBINER_ENABLE_SET     0x0
 381 #define COMBINER_ENABLE_CLEAR   0x4
 382 #define COMBINER_INT_STATUS     0xC
 383
 384 static DEFINE_SPINLOCK(irq_controller_lock);
 385
 386 struct combiner_chip_data {
 387         unsigned int irq_offset;
 388         unsigned int irq_mask;
 389         void __iomem *base;
 390 };
 391
 392 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 393
 394 static inline void __iomem *combiner_base(struct irq_data *data)
 395 {
 396         struct combiner_chip_data *combiner_data =
 397                 irq_data_get_irq_chip_data(data);
 398
 399         return combiner_data->base;
 400 }
 401
 402 static void combiner_mask_irq(struct irq_data *data)
 403 {
 404         u32 mask = 1 << (data->irq % 32);
 405
 406         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 407 }
 408
 409 static void combiner_unmask_irq(struct irq_data *data)
 410 {
 411         u32 mask = 1 << (data->irq % 32);
 412
 413         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 414 }
 415
 416 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 417 {
 418         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
 419         struct irq_chip *chip = irq_get_chip(irq);
 420         unsigned int cascade_irq, combiner_irq;
 421         unsigned long status;
 422
 423         chained_irq_enter(chip, desc);
 424
 425         spin_lock(&irq_controller_lock);
 426         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
 427         spin_unlock(&irq_controller_lock);
 428         status &= chip_data->irq_mask;
 429
 430         if (status == 0)
 431                 goto out;
 432
 433         combiner_irq = __ffs(status);
 434
 435         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
 436         if (unlikely(cascade_irq >= NR_IRQS))
 437                 do_bad_IRQ(cascade_irq, desc);
 438         else
 439                 generic_handle_irq(cascade_irq);
 440
 441  out:
 442         chained_irq_exit(chip, desc);
 443 }
 444
 445 static struct irq_chip combiner_chip = {
 446         .name           = "COMBINER",
 447         .irq_mask       = combiner_mask_irq,
 448         .irq_unmask     = combiner_unmask_irq,
 449 };
 450
 451 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 452 {
 453         unsigned int max_nr;
 454
 455         if (soc_is_exynos5250())
 456                 max_nr = EXYNOS5_MAX_COMBINER_NR;
 457         else
 458                 max_nr = EXYNOS4_MAX_COMBINER_NR;
 459
 460         if (combiner_nr >= max_nr)
 461                 BUG();
 462         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 463                 BUG();
 464         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 465 }
 466
 467 static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 468                           unsigned int irq_start)
 469 {
 470         unsigned int i;
 471         unsigned int max_nr;
 472
 473         if (soc_is_exynos5250())
 474                 max_nr = EXYNOS5_MAX_COMBINER_NR;
 475         else
 476                 max_nr = EXYNOS4_MAX_COMBINER_NR;
 477
 478         if (combiner_nr >= max_nr)
 479                 BUG();
 480
 481         combiner_data[combiner_nr].base = base;
 482         combiner_data[combiner_nr].irq_offset = irq_start;
 483         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 484
 485         /* Disable all interrupts */
 486
 487         __raw_writel(combiner_data[combiner_nr].irq_mask,
 488                      base + COMBINER_ENABLE_CLEAR);
 489
 490         /* Setup the Linux IRQ subsystem */
 491
 492         for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
 493                                 + MAX_IRQ_IN_COMBINER; i++) {
 494                 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
 495                 irq_set_chip_data(i, &combiner_data[combiner_nr]);
 496                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 497         }
 498 }
 499
 500 #ifdef CONFIG_OF
 501 static const struct of_device_id exynos4_dt_irq_match[] = {
 502         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 503         {},
 504 };
 505 #endif
 506
 507 void __init exynos4_init_irq(void)
 508 {
 509         int irq;
 510         unsigned int gic_bank_offset;
 511
 512         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 513
 514         if (!of_have_populated_dt())
 515                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 516 #ifdef CONFIG_OF
 517         else
 518                 of_irq_init(exynos4_dt_irq_match);
 519 #endif
 520
 521         for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
 522
 523                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 524                                 COMBINER_IRQ(irq, 0));
 525                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 526         }
 527
 528         /*
 529          * The parameters of s5p_init_irq() are for VIC init.
 530          * Theses parameters should be NULL and 0 because EXYNOS4
 531          * uses GIC instead of VIC.
 532          */
 533         s5p_init_irq(NULL, 0);
 534 }
 535
 536 void __init exynos5_init_irq(void)
 537 {
 538         int irq;
 539
 540         gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
 541
 542         for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
 543                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 544                                 COMBINER_IRQ(irq, 0));
 545                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 546         }
 547
 548         /*
 549          * The parameters of s5p_init_irq() are for VIC init.
 550          * Theses parameters should be NULL and 0 because EXYNOS4
 551          * uses GIC instead of VIC.
 552          */
 553         s5p_init_irq(NULL, 0);
 554 }
 555
 556 struct bus_type exynos4_subsys = {
 557         .name           = "exynos4-core",
 558         .dev_name       = "exynos4-core",
 559 };
 560
 561 struct bus_type exynos5_subsys = {
 562         .name           = "exynos5-core",
 563         .dev_name       = "exynos5-core",
 564 };
 565
 566 static struct device exynos4_dev = {
 567         .bus    = &exynos4_subsys,
 568 };
 569
 570 static struct device exynos5_dev = {
 571         .bus    = &exynos5_subsys,
 572 };
 573
 574 static int __init exynos_core_init(void)
 575 {
 576         if (soc_is_exynos5250())
 577                 return subsys_system_register(&exynos5_subsys, NULL);
 578         else
 579                 return subsys_system_register(&exynos4_subsys, NULL);
 580 }
 581 core_initcall(exynos_core_init);
 582
 583 #ifdef CONFIG_CACHE_L2X0
 584 static int __init exynos4_l2x0_cache_init(void)
 585 {
 586         if (soc_is_exynos5250())
 587                 return 0;
 588
 589         int ret;
 590         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
 591         if (!ret) {
 592                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 593                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 594                 return 0;
 595         }
 596
 597         if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
 598                 l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
 599                 /* TAG, Data Latency Control: 2 cycles */
 600                 l2x0_saved_regs.tag_latency = 0x110;
 601
 602                 if (soc_is_exynos4212() || soc_is_exynos4412())
 603                         l2x0_saved_regs.data_latency = 0x120;
 604                 else
 605                         l2x0_saved_regs.data_latency = 0x110;
 606
 607                 l2x0_saved_regs.prefetch_ctrl = 0x30000007;
 608                 l2x0_saved_regs.pwr_ctrl =
 609                         (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
 610
 611                 l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
 612
 613                 __raw_writel(l2x0_saved_regs.tag_latency,
 614                                 S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 615                 __raw_writel(l2x0_saved_regs.data_latency,
 616                                 S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 617
 618                 /* L2X0 Prefetch Control */
 619                 __raw_writel(l2x0_saved_regs.prefetch_ctrl,
 620                                 S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 621
 622                 /* L2X0 Power Control */
 623                 __raw_writel(l2x0_saved_regs.pwr_ctrl,
 624                                 S5P_VA_L2CC + L2X0_POWER_CTRL);
 625
 626                 clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
 627                 clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
 628         }
 629
 630         l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
 631         return 0;
 632 }
 633 early_initcall(exynos4_l2x0_cache_init);
 634 #endif
 635
 636 static int __init exynos5_l2_cache_init(void)
 637 {
 638         unsigned int val;
 639
 640         if (!soc_is_exynos5250())
 641                 return 0;
 642
 643         asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
 644                      "bic %0, %0, #(1 << 2)\n"  /* cache disable */
 645                      "mcr p15, 0, %0, c1, c0, 0\n"
 646                      "mrc p15, 1, %0, c9, c0, 2\n"
 647                      : "=r"(val));
 648
 649         val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
 650
 651         asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
 652         asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
 653                      "orr %0, %0, #(1 << 2)\n"  /* cache enable */
 654                      "mcr p15, 0, %0, c1, c0, 0\n"
 655                      : : "r"(val));
 656
 657         return 0;
 658 }
 659 early_initcall(exynos5_l2_cache_init);
 660
 661 static int __init exynos_init(void)
 662 {
 663         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 664
 665         if (soc_is_exynos5250())
 666                 return device_register(&exynos5_dev);
 667         else
 668                 return device_register(&exynos4_dev);
 669 }
 670
 671 /* uart registration process */
 672
 673 static void __init exynos_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 674 {
 675         struct s3c2410_uartcfg *tcfg = cfg;
 676         u32 ucnt;
 677
 678         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 679                 tcfg->has_fracval = 1;
 680
 681         if (soc_is_exynos5250())
 682                 s3c24xx_init_uartdevs("exynos4210-uart", exynos5_uart_resources, cfg, no);
 683         else
 684                 s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
 685 }
 686
 687 static void __iomem *exynos_eint_base;
 688
 689 static DEFINE_SPINLOCK(eint_lock);
 690
 691 static unsigned int eint0_15_data[16];
 692
 693 static inline int exynos4_irq_to_gpio(unsigned int irq)
 694 {
 695         if (irq < IRQ_EINT(0))
 696                 return -EINVAL;
 697
 698         irq -= IRQ_EINT(0);
 699         if (irq < 8)
 700                 return EXYNOS4_GPX0(irq);
 701
 702         irq -= 8;
 703         if (irq < 8)
 704                 return EXYNOS4_GPX1(irq);
 705
 706         irq -= 8;
 707         if (irq < 8)
 708                 return EXYNOS4_GPX2(irq);
 709
 710         irq -= 8;
 711         if (irq < 8)
 712                 return EXYNOS4_GPX3(irq);
 713
 714         return -EINVAL;
 715 }
 716
 717 static inline int exynos5_irq_to_gpio(unsigned int irq)
 718 {
 719         if (irq < IRQ_EINT(0))
 720                 return -EINVAL;
 721
 722         irq -= IRQ_EINT(0);
 723         if (irq < 8)
 724                 return EXYNOS5_GPX0(irq);
 725
 726         irq -= 8;
 727         if (irq < 8)
 728                 return EXYNOS5_GPX1(irq);
 729
 730         irq -= 8;
 731         if (irq < 8)
 732                 return EXYNOS5_GPX2(irq);
 733
 734         irq -= 8;
 735         if (irq < 8)
 736                 return EXYNOS5_GPX3(irq);
 737
 738         return -EINVAL;
 739 }
 740
 741 static unsigned int exynos4_eint0_15_src_int[16] = {
 742         EXYNOS4_IRQ_EINT0,
 743         EXYNOS4_IRQ_EINT1,
 744         EXYNOS4_IRQ_EINT2,
 745         EXYNOS4_IRQ_EINT3,
 746         EXYNOS4_IRQ_EINT4,
 747         EXYNOS4_IRQ_EINT5,
 748         EXYNOS4_IRQ_EINT6,
 749         EXYNOS4_IRQ_EINT7,
 750         EXYNOS4_IRQ_EINT8,
 751         EXYNOS4_IRQ_EINT9,
 752         EXYNOS4_IRQ_EINT10,
 753         EXYNOS4_IRQ_EINT11,
 754         EXYNOS4_IRQ_EINT12,
 755         EXYNOS4_IRQ_EINT13,
 756         EXYNOS4_IRQ_EINT14,
 757         EXYNOS4_IRQ_EINT15,
 758 };
 759
 760 static unsigned int exynos5_eint0_15_src_int[16] = {
 761         EXYNOS5_IRQ_EINT0,
 762         EXYNOS5_IRQ_EINT1,
 763         EXYNOS5_IRQ_EINT2,
 764         EXYNOS5_IRQ_EINT3,
 765         EXYNOS5_IRQ_EINT4,
 766         EXYNOS5_IRQ_EINT5,
 767         EXYNOS5_IRQ_EINT6,
 768         EXYNOS5_IRQ_EINT7,
 769         EXYNOS5_IRQ_EINT8,
 770         EXYNOS5_IRQ_EINT9,
 771         EXYNOS5_IRQ_EINT10,
 772         EXYNOS5_IRQ_EINT11,
 773         EXYNOS5_IRQ_EINT12,
 774         EXYNOS5_IRQ_EINT13,
 775         EXYNOS5_IRQ_EINT14,
 776         EXYNOS5_IRQ_EINT15,
 777 };
 778 static inline void exynos_irq_eint_mask(struct irq_data *data)
 779 {
 780         u32 mask;
 781
 782         spin_lock(&eint_lock);
 783         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 784         mask |= EINT_OFFSET_BIT(data->irq);
 785         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 786         spin_unlock(&eint_lock);
 787 }
 788
 789 static void exynos_irq_eint_unmask(struct irq_data *data)
 790 {
 791         u32 mask;
 792
 793         spin_lock(&eint_lock);
 794         mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
 795         mask &= ~(EINT_OFFSET_BIT(data->irq));
 796         __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
 797         spin_unlock(&eint_lock);
 798 }
 799
 800 static inline void exynos_irq_eint_ack(struct irq_data *data)
 801 {
 802         __raw_writel(EINT_OFFSET_BIT(data->irq),
 803                      EINT_PEND(exynos_eint_base, data->irq));
 804 }
 805
 806 static void exynos_irq_eint_maskack(struct irq_data *data)
 807 {
 808         exynos_irq_eint_mask(data);
 809         exynos_irq_eint_ack(data);
 810 }
 811
 812 static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
 813 {
 814         int offs = EINT_OFFSET(data->irq);
 815         int shift;
 816         u32 ctrl, mask;
 817         u32 newvalue = 0;
 818
 819         switch (type) {
 820         case IRQ_TYPE_EDGE_RISING:
 821                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 822                 break;
 823
 824         case IRQ_TYPE_EDGE_FALLING:
 825                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 826                 break;
 827
 828         case IRQ_TYPE_EDGE_BOTH:
 829                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 830                 break;
 831
 832         case IRQ_TYPE_LEVEL_LOW:
 833                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 834                 break;
 835
 836         case IRQ_TYPE_LEVEL_HIGH:
 837                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 838                 break;
 839
 840         default:
 841                 printk(KERN_ERR "No such irq type %d", type);
 842                 return -EINVAL;
 843         }
 844
 845         shift = (offs & 0x7) * 4;
 846         mask = 0x7 << shift;
 847
 848         spin_lock(&eint_lock);
 849         ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
 850         ctrl &= ~mask;
 851         ctrl |= newvalue << shift;
 852         __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
 853         spin_unlock(&eint_lock);
 854
 855         if (soc_is_exynos5250())
 856                 s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 857         else
 858                 s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
 859
 860         return 0;
 861 }
 862
 863 static struct irq_chip exynos_irq_eint = {
 864         .name           = "exynos-eint",
 865         .irq_mask       = exynos_irq_eint_mask,
 866         .irq_unmask     = exynos_irq_eint_unmask,
 867         .irq_mask_ack   = exynos_irq_eint_maskack,
 868         .irq_ack        = exynos_irq_eint_ack,
 869         .irq_set_type   = exynos_irq_eint_set_type,
 870 #ifdef CONFIG_PM
 871         .irq_set_wake   = s3c_irqext_wake,
 872 #endif
 873 };
 874
 875 /*
 876  * exynos4_irq_demux_eint
 877  *
 878  * This function demuxes the IRQ from from EINTs 16 to 31.
 879  * It is designed to be inlined into the specific handler
 880  * s5p_irq_demux_eintX_Y.
 881  *
 882  * Each EINT pend/mask registers handle eight of them.
 883  */
 884 static inline void exynos_irq_demux_eint(unsigned int start)
 885 {
 886         unsigned int irq;
 887
 888         u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
 889         u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
 890
 891         status &= ~mask;
 892         status &= 0xff;
 893
 894         while (status) {
 895                 irq = fls(status) - 1;
 896                 generic_handle_irq(irq + start);
 897                 status &= ~(1 << irq);
 898         }
 899 }
 900
 901 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 902 {
 903         struct irq_chip *chip = irq_get_chip(irq);
 904         chained_irq_enter(chip, desc);
 905         exynos_irq_demux_eint(IRQ_EINT(16));
 906         exynos_irq_demux_eint(IRQ_EINT(24));
 907         chained_irq_exit(chip, desc);
 908 }
 909
 910 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 911 {
 912         u32 *irq_data = irq_get_handler_data(irq);
 913         struct irq_chip *chip = irq_get_chip(irq);
 914
 915         chained_irq_enter(chip, desc);
 916         chip->irq_mask(&desc->irq_data);
 917
 918         if (chip->irq_ack)
 919                 chip->irq_ack(&desc->irq_data);
 920
 921         generic_handle_irq(*irq_data);
 922
 923         chip->irq_unmask(&desc->irq_data);
 924         chained_irq_exit(chip, desc);
 925 }
 926
 927 static int __init exynos_init_irq_eint(void)
 928 {
 929         int irq;
 930
 931         if (soc_is_exynos5250())
 932                 exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
 933         else
 934                 exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
 935
 936         if (exynos_eint_base == NULL) {
 937                 pr_err("unable to ioremap for EINT base address\n");
 938                 return -ENOMEM;
 939         }
 940
 941         for (irq = 0 ; irq <= 31 ; irq++) {
 942                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
 943                                          handle_level_irq);
 944                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 945         }
 946
 947         irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
 948
 949         for (irq = 0 ; irq <= 15 ; irq++) {
 950                 eint0_15_data[irq] = IRQ_EINT(irq);
 951
 952                 if (soc_is_exynos5250()) {
 953                         irq_set_handler_data(exynos5_eint0_15_src_int[irq],
 954                                              &eint0_15_data[irq]);
 955                         irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
 956                                                 exynos_irq_eint0_15);
 957                 } else {
 958                         irq_set_handler_data(exynos4_eint0_15_src_int[irq],
 959                                              &eint0_15_data[irq]);
 960                         irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
 961                                                 exynos_irq_eint0_15);
 962                 }
 963         }
 964
 965         return 0;
 966 }
 967 arch_initcall(exynos_init_irq_eint);