arch/arm/mach-exynos/common.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for EXYNOS
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/io.h>
  16 #include <linux/device.h>
  17 #include <linux/gpio.h>
  18 #include <linux/sched.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/of.h>
  21 #include <linux/of_irq.h>
  22
  23 #include <asm/proc-fns.h>
  24 #include <asm/exception.h>
  25 #include <asm/hardware/cache-l2x0.h>
  26 #include <asm/hardware/gic.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/mach/irq.h>
  29
  30 #include <mach/regs-irq.h>
  31 #include <mach/regs-pmu.h>
  32 #include <mach/regs-gpio.h>
  33
  34 #include <plat/cpu.h>
  35 #include <plat/clock.h>
  36 #include <plat/devs.h>
  37 #include <plat/pm.h>
  38 #include <plat/sdhci.h>
  39 #include <plat/gpio-cfg.h>
  40 #include <plat/adc-core.h>
  41 #include <plat/fb-core.h>
  42 #include <plat/fimc-core.h>
  43 #include <plat/iic-core.h>
  44 #include <plat/tv-core.h>
  45 #include <plat/regs-serial.h>
  46
  47 #include "common.h"
  48
  49 static const char name_exynos4210[] = "EXYNOS4210";
  50 static const char name_exynos4212[] = "EXYNOS4212";
  51 static const char name_exynos4412[] = "EXYNOS4412";
  52
  53 static void exynos4_map_io(void);
  54 static void exynos4_init_clocks(int xtal);
  55 static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
  56 static int exynos_init(void);
  57
  58 static struct cpu_table cpu_ids[] __initdata = {
  59         {
  60                 .idcode         = EXYNOS4210_CPU_ID,
  61                 .idmask         = EXYNOS4_CPU_MASK,
  62                 .map_io         = exynos4_map_io,
  63                 .init_clocks    = exynos4_init_clocks,
  64                 .init_uarts     = exynos4_init_uarts,
  65                 .init           = exynos_init,
  66                 .name           = name_exynos4210,
  67         }, {
  68                 .idcode         = EXYNOS4212_CPU_ID,
  69                 .idmask         = EXYNOS4_CPU_MASK,
  70                 .map_io         = exynos4_map_io,
  71                 .init_clocks    = exynos4_init_clocks,
  72                 .init_uarts     = exynos4_init_uarts,
  73                 .init           = exynos_init,
  74                 .name           = name_exynos4212,
  75         }, {
  76                 .idcode         = EXYNOS4412_CPU_ID,
  77                 .idmask         = EXYNOS4_CPU_MASK,
  78                 .map_io         = exynos4_map_io,
  79                 .init_clocks    = exynos4_init_clocks,
  80                 .init_uarts     = exynos4_init_uarts,
  81                 .init           = exynos_init,
  82                 .name           = name_exynos4412,
  83         },
  84 };
  85
  86 /* Initial IO mappings */
  87
  88 static struct map_desc exynos_iodesc[] __initdata = {
  89         {
  90                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  91                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CHIPID),
  92                 .length         = SZ_4K,
  93                 .type           = MT_DEVICE,
  94         }, {
  95                 .virtual        = (unsigned long)S3C_VA_SYS,
  96                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  97                 .length         = SZ_64K,
  98                 .type           = MT_DEVICE,
  99         }, {
 100                 .virtual        = (unsigned long)S3C_VA_TIMER,
 101                 .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
 102                 .length         = SZ_16K,
 103                 .type           = MT_DEVICE,
 104         }, {
 105                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 106                 .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE,
 109         }, {
 110                 .virtual        = (unsigned long)S5P_VA_SROMC,
 111                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
 112                 .length         = SZ_4K,
 113                 .type           = MT_DEVICE,
 114         }, {
 115                 .virtual        = (unsigned long)S5P_VA_SYSTIMER,
 116                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
 117                 .length         = SZ_4K,
 118                 .type           = MT_DEVICE,
 119         }, {
 120                 .virtual        = (unsigned long)S5P_VA_PMU,
 121                 .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
 122                 .length         = SZ_64K,
 123                 .type           = MT_DEVICE,
 124         }, {
 125                 .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
 126                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE,
 129         }, {
 130                 .virtual        = (unsigned long)S5P_VA_GIC_CPU,
 131                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
 132                 .length         = SZ_64K,
 133                 .type           = MT_DEVICE,
 134         }, {
 135                 .virtual        = (unsigned long)S5P_VA_GIC_DIST,
 136                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
 137                 .length         = SZ_64K,
 138                 .type           = MT_DEVICE,
 139         }, {
 140                 .virtual        = (unsigned long)S3C_VA_UART,
 141                 .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
 142                 .length         = SZ_512K,
 143                 .type           = MT_DEVICE,
 144         },
 145 };
 146
 147 static struct map_desc exynos4_iodesc[] __initdata = {
 148         {
 149                 .virtual        = (unsigned long)S5P_VA_CMU,
 150                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
 151                 .length         = SZ_128K,
 152                 .type           = MT_DEVICE,
 153         }, {
 154                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
 155                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
 156                 .length         = SZ_8K,
 157                 .type           = MT_DEVICE,
 158         }, {
 159                 .virtual        = (unsigned long)S5P_VA_L2CC,
 160                 .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
 161                 .length         = SZ_4K,
 162                 .type           = MT_DEVICE,
 163         }, {
 164                 .virtual        = (unsigned long)S5P_VA_GPIO1,
 165                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
 166                 .length         = SZ_4K,
 167                 .type           = MT_DEVICE,
 168         }, {
 169                 .virtual        = (unsigned long)S5P_VA_GPIO2,
 170                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
 171                 .length         = SZ_4K,
 172                 .type           = MT_DEVICE,
 173         }, {
 174                 .virtual        = (unsigned long)S5P_VA_GPIO3,
 175                 .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
 176                 .length         = SZ_256,
 177                 .type           = MT_DEVICE,
 178         }, {
 179                 .virtual        = (unsigned long)S5P_VA_DMC0,
 180                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
 181                 .length         = SZ_4K,
 182                 .type           = MT_DEVICE,
 183         }, {
 184                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 185                 .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
 186                 .length         = SZ_4K,
 187                 .type           = MT_DEVICE,
 188         },
 189 };
 190
 191 static struct map_desc exynos4_iodesc0[] __initdata = {
 192         {
 193                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 194                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
 195                 .length         = SZ_4K,
 196                 .type           = MT_DEVICE,
 197         },
 198 };
 199
 200 static struct map_desc exynos4_iodesc1[] __initdata = {
 201         {
 202                 .virtual        = (unsigned long)S5P_VA_SYSRAM,
 203                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
 204                 .length         = SZ_4K,
 205                 .type           = MT_DEVICE,
 206         },
 207 };
 208
 209 void exynos4_restart(char mode, const char *cmd)
 210 {
 211         __raw_writel(0x1, S5P_SWRESET);
 212 }
 213
 214 /*
 215  * exynos_map_io
 216  *
 217  * register the standard cpu IO areas
 218  */
 219
 220 void __init exynos_init_io(struct map_desc *mach_desc, int size)
 221 {
 222         /* initialize the io descriptors we need for initialization */
 223         iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
 224         if (mach_desc)
 225                 iotable_init(mach_desc, size);
 226
 227         /* detect cpu id and rev. */
 228         s5p_init_cpu(S5P_VA_CHIPID);
 229
 230         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 231 }
 232
 233 static void __init exynos4_map_io(void)
 234 {
 235         iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 236
 237         if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
 238                 iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
 239         else
 240                 iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
 241
 242         /* initialize device information early */
 243         exynos4_default_sdhci0();
 244         exynos4_default_sdhci1();
 245         exynos4_default_sdhci2();
 246         exynos4_default_sdhci3();
 247
 248         s3c_adc_setname("samsung-adc-v3");
 249
 250         s3c_fimc_setname(0, "exynos4-fimc");
 251         s3c_fimc_setname(1, "exynos4-fimc");
 252         s3c_fimc_setname(2, "exynos4-fimc");
 253         s3c_fimc_setname(3, "exynos4-fimc");
 254
 255         /* The I2C bus controllers are directly compatible with s3c2440 */
 256         s3c_i2c0_setname("s3c2440-i2c");
 257         s3c_i2c1_setname("s3c2440-i2c");
 258         s3c_i2c2_setname("s3c2440-i2c");
 259
 260         s5p_fb_setname(0, "exynos4-fb");
 261         s5p_hdmi_setname("exynos4-hdmi");
 262 }
 263
 264 static void __init exynos4_init_clocks(int xtal)
 265 {
 266         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 267
 268         s3c24xx_register_baseclocks(xtal);
 269         s5p_register_clocks(xtal);
 270
 271         if (soc_is_exynos4210())
 272                 exynos4210_register_clocks();
 273         else if (soc_is_exynos4212() || soc_is_exynos4412())
 274                 exynos4212_register_clocks();
 275
 276         exynos4_register_clocks();
 277         exynos4_setup_clocks();
 278 }
 279
 280 #define COMBINER_ENABLE_SET     0x0
 281 #define COMBINER_ENABLE_CLEAR   0x4
 282 #define COMBINER_INT_STATUS     0xC
 283
 284 static DEFINE_SPINLOCK(irq_controller_lock);
 285
 286 struct combiner_chip_data {
 287         unsigned int irq_offset;
 288         unsigned int irq_mask;
 289         void __iomem *base;
 290 };
 291
 292 static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
 293
 294 static inline void __iomem *combiner_base(struct irq_data *data)
 295 {
 296         struct combiner_chip_data *combiner_data =
 297                 irq_data_get_irq_chip_data(data);
 298
 299         return combiner_data->base;
 300 }
 301
 302 static void combiner_mask_irq(struct irq_data *data)
 303 {
 304         u32 mask = 1 << (data->irq % 32);
 305
 306         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
 307 }
 308
 309 static void combiner_unmask_irq(struct irq_data *data)
 310 {
 311         u32 mask = 1 << (data->irq % 32);
 312
 313         __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
 314 }
 315
 316 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 317 {
 318         struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
 319         struct irq_chip *chip = irq_get_chip(irq);
 320         unsigned int cascade_irq, combiner_irq;
 321         unsigned long status;
 322
 323         chained_irq_enter(chip, desc);
 324
 325         spin_lock(&irq_controller_lock);
 326         status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
 327         spin_unlock(&irq_controller_lock);
 328         status &= chip_data->irq_mask;
 329
 330         if (status == 0)
 331                 goto out;
 332
 333         combiner_irq = __ffs(status);
 334
 335         cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
 336         if (unlikely(cascade_irq >= NR_IRQS))
 337                 do_bad_IRQ(cascade_irq, desc);
 338         else
 339                 generic_handle_irq(cascade_irq);
 340
 341  out:
 342         chained_irq_exit(chip, desc);
 343 }
 344
 345 static struct irq_chip combiner_chip = {
 346         .name           = "COMBINER",
 347         .irq_mask       = combiner_mask_irq,
 348         .irq_unmask     = combiner_unmask_irq,
 349 };
 350
 351 static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 352 {
 353         if (combiner_nr >= MAX_COMBINER_NR)
 354                 BUG();
 355         if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
 356                 BUG();
 357         irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 358 }
 359
 360 static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 361                           unsigned int irq_start)
 362 {
 363         unsigned int i;
 364
 365         if (combiner_nr >= MAX_COMBINER_NR)
 366                 BUG();
 367
 368         combiner_data[combiner_nr].base = base;
 369         combiner_data[combiner_nr].irq_offset = irq_start;
 370         combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
 371
 372         /* Disable all interrupts */
 373
 374         __raw_writel(combiner_data[combiner_nr].irq_mask,
 375                      base + COMBINER_ENABLE_CLEAR);
 376
 377         /* Setup the Linux IRQ subsystem */
 378
 379         for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
 380                                 + MAX_IRQ_IN_COMBINER; i++) {
 381                 irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
 382                 irq_set_chip_data(i, &combiner_data[combiner_nr]);
 383                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 384         }
 385 }
 386
 387 #ifdef CONFIG_OF
 388 static const struct of_device_id exynos4_dt_irq_match[] = {
 389         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 390         {},
 391 };
 392 #endif
 393
 394 void __init exynos4_init_irq(void)
 395 {
 396         int irq;
 397         unsigned int gic_bank_offset;
 398
 399         gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 400
 401         if (!of_have_populated_dt())
 402                 gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
 403 #ifdef CONFIG_OF
 404         else
 405                 of_irq_init(exynos4_dt_irq_match);
 406 #endif
 407
 408         for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
 409
 410                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
 411                                 COMBINER_IRQ(irq, 0));
 412                 combiner_cascade_irq(irq, IRQ_SPI(irq));
 413         }
 414
 415         /*
 416          * The parameters of s5p_init_irq() are for VIC init.
 417          * Theses parameters should be NULL and 0 because EXYNOS4
 418          * uses GIC instead of VIC.
 419          */
 420         s5p_init_irq(NULL, 0);
 421 }
 422
 423 struct bus_type exynos4_subsys = {
 424         .name           = "exynos4-core",
 425         .dev_name       = "exynos4-core",
 426 };
 427
 428 static struct device exynos4_dev = {
 429         .bus    = &exynos4_subsys,
 430 };
 431
 432 static int __init exynos4_core_init(void)
 433 {
 434         return subsys_system_register(&exynos4_subsys, NULL);
 435 }
 436 core_initcall(exynos4_core_init);
 437
 438 #ifdef CONFIG_CACHE_L2X0
 439 static int __init exynos4_l2x0_cache_init(void)
 440 {
 441         /* TAG, Data Latency Control: 2cycle */
 442         __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
 443
 444         if (soc_is_exynos4210())
 445                 __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 446         else if (soc_is_exynos4212() || soc_is_exynos4412())
 447                 __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
 448
 449         /* L2X0 Prefetch Control */
 450         __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
 451
 452         /* L2X0 Power Control */
 453         __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
 454                      S5P_VA_L2CC + L2X0_POWER_CTRL);
 455
 456         l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
 457
 458         return 0;
 459 }
 460
 461 early_initcall(exynos4_l2x0_cache_init);
 462 #endif
 463
 464 static int __init exynos_init(void)
 465 {
 466         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 467         return device_register(&exynos4_dev);
 468 }
 469
 470 /* uart registration process */
 471
 472 static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 473 {
 474         struct s3c2410_uartcfg *tcfg = cfg;
 475         u32 ucnt;
 476
 477         for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
 478                 tcfg->has_fracval = 1;
 479
 480         s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
 481 }
 482
 483 static DEFINE_SPINLOCK(eint_lock);
 484
 485 static unsigned int eint0_15_data[16];
 486
 487 static unsigned int exynos4_get_irq_nr(unsigned int number)
 488 {
 489         u32 ret = 0;
 490
 491         switch (number) {
 492         case 0 ... 3:
 493                 ret = (number + IRQ_EINT0);
 494                 break;
 495         case 4 ... 7:
 496                 ret = (number + (IRQ_EINT4 - 4));
 497                 break;
 498         case 8 ... 15:
 499                 ret = (number + (IRQ_EINT8 - 8));
 500                 break;
 501         default:
 502                 printk(KERN_ERR "number available : %d\n", number);
 503         }
 504
 505         return ret;
 506 }
 507
 508 static inline void exynos4_irq_eint_mask(struct irq_data *data)
 509 {
 510         u32 mask;
 511
 512         spin_lock(&eint_lock);
 513         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 514         mask |= eint_irq_to_bit(data->irq);
 515         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 516         spin_unlock(&eint_lock);
 517 }
 518
 519 static void exynos4_irq_eint_unmask(struct irq_data *data)
 520 {
 521         u32 mask;
 522
 523         spin_lock(&eint_lock);
 524         mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 525         mask &= ~(eint_irq_to_bit(data->irq));
 526         __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
 527         spin_unlock(&eint_lock);
 528 }
 529
 530 static inline void exynos4_irq_eint_ack(struct irq_data *data)
 531 {
 532         __raw_writel(eint_irq_to_bit(data->irq),
 533                      S5P_EINT_PEND(EINT_REG_NR(data->irq)));
 534 }
 535
 536 static void exynos4_irq_eint_maskack(struct irq_data *data)
 537 {
 538         exynos4_irq_eint_mask(data);
 539         exynos4_irq_eint_ack(data);
 540 }
 541
 542 static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
 543 {
 544         int offs = EINT_OFFSET(data->irq);
 545         int shift;
 546         u32 ctrl, mask;
 547         u32 newvalue = 0;
 548
 549         switch (type) {
 550         case IRQ_TYPE_EDGE_RISING:
 551                 newvalue = S5P_IRQ_TYPE_EDGE_RISING;
 552                 break;
 553
 554         case IRQ_TYPE_EDGE_FALLING:
 555                 newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
 556                 break;
 557
 558         case IRQ_TYPE_EDGE_BOTH:
 559                 newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
 560                 break;
 561
 562         case IRQ_TYPE_LEVEL_LOW:
 563                 newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
 564                 break;
 565
 566         case IRQ_TYPE_LEVEL_HIGH:
 567                 newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
 568                 break;
 569
 570         default:
 571                 printk(KERN_ERR "No such irq type %d", type);
 572                 return -EINVAL;
 573         }
 574
 575         shift = (offs & 0x7) * 4;
 576         mask = 0x7 << shift;
 577
 578         spin_lock(&eint_lock);
 579         ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
 580         ctrl &= ~mask;
 581         ctrl |= newvalue << shift;
 582         __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
 583         spin_unlock(&eint_lock);
 584
 585         switch (offs) {
 586         case 0 ... 7:
 587                 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
 588                 break;
 589         case 8 ... 15:
 590                 s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
 591                 break;
 592         case 16 ... 23:
 593                 s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
 594                 break;
 595         case 24 ... 31:
 596                 s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
 597                 break;
 598         default:
 599                 printk(KERN_ERR "No such irq number %d", offs);
 600         }
 601
 602         return 0;
 603 }
 604
 605 static struct irq_chip exynos4_irq_eint = {
 606         .name           = "exynos4-eint",
 607         .irq_mask       = exynos4_irq_eint_mask,
 608         .irq_unmask     = exynos4_irq_eint_unmask,
 609         .irq_mask_ack   = exynos4_irq_eint_maskack,
 610         .irq_ack        = exynos4_irq_eint_ack,
 611         .irq_set_type   = exynos4_irq_eint_set_type,
 612 #ifdef CONFIG_PM
 613         .irq_set_wake   = s3c_irqext_wake,
 614 #endif
 615 };
 616
 617 /*
 618  * exynos4_irq_demux_eint
 619  *
 620  * This function demuxes the IRQ from from EINTs 16 to 31.
 621  * It is designed to be inlined into the specific handler
 622  * s5p_irq_demux_eintX_Y.
 623  *
 624  * Each EINT pend/mask registers handle eight of them.
 625  */
 626 static inline void exynos4_irq_demux_eint(unsigned int start)
 627 {
 628         unsigned int irq;
 629
 630         u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
 631         u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
 632
 633         status &= ~mask;
 634         status &= 0xff;
 635
 636         while (status) {
 637                 irq = fls(status) - 1;
 638                 generic_handle_irq(irq + start);
 639                 status &= ~(1 << irq);
 640         }
 641 }
 642
 643 static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 644 {
 645         struct irq_chip *chip = irq_get_chip(irq);
 646         chained_irq_enter(chip, desc);
 647         exynos4_irq_demux_eint(IRQ_EINT(16));
 648         exynos4_irq_demux_eint(IRQ_EINT(24));
 649         chained_irq_exit(chip, desc);
 650 }
 651
 652 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 653 {
 654         u32 *irq_data = irq_get_handler_data(irq);
 655         struct irq_chip *chip = irq_get_chip(irq);
 656
 657         chained_irq_enter(chip, desc);
 658         chip->irq_mask(&desc->irq_data);
 659
 660         if (chip->irq_ack)
 661                 chip->irq_ack(&desc->irq_data);
 662
 663         generic_handle_irq(*irq_data);
 664
 665         chip->irq_unmask(&desc->irq_data);
 666         chained_irq_exit(chip, desc);
 667 }
 668
 669 static int __init exynos4_init_irq_eint(void)
 670 {
 671         int irq;
 672
 673         for (irq = 0 ; irq <= 31 ; irq++) {
 674                 irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
 675                                          handle_level_irq);
 676                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
 677         }
 678
 679         irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
 680
 681         for (irq = 0 ; irq <= 15 ; irq++) {
 682                 eint0_15_data[irq] = IRQ_EINT(irq);
 683
 684                 irq_set_handler_data(exynos4_get_irq_nr(irq),
 685                                      &eint0_15_data[irq]);
 686                 irq_set_chained_handler(exynos4_get_irq_nr(irq),
 687                                         exynos4_irq_eint0_15);
 688         }
 689
 690         return 0;
 691 }
 692 arch_initcall(exynos4_init_irq_eint);