2 * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS4210 - Clock support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/err.h>
14 #include <linux/clk.h>
16 #include <linux/syscore_ops.h>
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
26 #include <mach/hardware.h>
28 #include <mach/regs-clock.h>
29 #include <mach/sysmmu.h>
32 #include "clock-exynos4.h"
34 #ifdef CONFIG_PM_SLEEP
35 static struct sleep_save exynos4210_clock_save[] = {
36 SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
37 SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
38 SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
39 SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
40 SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
41 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
42 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
43 SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
47 static struct clksrc_clk *sysclks[] = {
48 /* nothing here yet */
51 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
53 return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
56 static struct clksrc_clk clksrcs[] = {
61 .enable = exynos4_clksrc_mask_fsys_ctrl,
64 .sources = &exynos4_clkset_mout_corebus,
65 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
66 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
70 .devname = "exynos4-fb.1",
71 .enable = exynos4_clksrc_mask_lcd1_ctrl,
74 .sources = &exynos4_clkset_group,
75 .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
76 .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
80 static struct clk init_clocks_off[] = {
84 .parent = &exynos4_clk_aclk_133.clk,
85 .enable = exynos4_clk_ip_fsys_ctrl,
90 .parent = &exynos4_clk_aclk_133.clk,
91 .enable = exynos4_clk_ip_fsys_ctrl,
95 .devname = "exynos4-fb.1",
96 .enable = exynos4_clk_ip_lcd1_ctrl,
99 .name = SYSMMU_CLOCK_NAME,
100 .devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
101 .enable = exynos4_clk_ip_image_ctrl,
104 .name = SYSMMU_CLOCK_NAME,
105 .devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
106 .enable = exynos4_clk_ip_lcd1_ctrl,
111 #ifdef CONFIG_PM_SLEEP
112 static int exynos4210_clock_suspend(void)
114 s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
119 static void exynos4210_clock_resume(void)
121 s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
125 #define exynos4210_clock_suspend NULL
126 #define exynos4210_clock_resume NULL
129 static struct syscore_ops exynos4210_clock_syscore_ops = {
130 .suspend = exynos4210_clock_suspend,
131 .resume = exynos4210_clock_resume,
134 void __init exynos4210_register_clocks(void)
138 exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
139 exynos4_clk_mout_mpll.reg_src.shift = 8;
140 exynos4_clk_mout_mpll.reg_src.size = 1;
142 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
143 s3c_register_clksrc(sysclks[ptr], 1);
145 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
147 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
148 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
150 register_syscore_ops(&exynos4210_clock_syscore_ops);