2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * EXYNOS4 - Clock support
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/err.h>
15 #include <linux/syscore_ops.h>
17 #include <plat/cpu-freq.h>
18 #include <plat/clock.h>
21 #include <plat/s5p-clock.h>
22 #include <plat/clock-clksrc.h>
26 #include <mach/regs-clock.h>
27 #include <mach/sysmmu.h>
30 #include "clock-exynos4.h"
32 #ifdef CONFIG_PM_SLEEP
33 static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
35 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
36 SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
37 SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
38 SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
39 SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
40 SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
41 SAVE_ITEM(EXYNOS4_CLKSRC_TV),
42 SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
43 SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
44 SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
45 SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
46 SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
47 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
48 SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
49 SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
50 SAVE_ITEM(EXYNOS4_CLKDIV_TV),
51 SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
52 SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
53 SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
54 SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
55 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
56 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
57 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
58 SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
59 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
60 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
61 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
62 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
63 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
64 SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
65 SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
66 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
67 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
68 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
69 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
70 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
71 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
72 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
73 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
74 SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
75 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
76 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
77 SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
78 SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
79 SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
80 SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
81 SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
82 SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
83 SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
84 SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
85 SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
86 SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
87 SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
88 SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
89 SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
90 SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
91 SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
92 SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
93 SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
94 SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
98 static struct clk exynos4_clk_sclk_hdmi27m = {
99 .name = "sclk_hdmi27m",
103 static struct clk exynos4_clk_sclk_hdmiphy = {
104 .name = "sclk_hdmiphy",
107 static struct clk exynos4_clk_sclk_usbphy0 = {
108 .name = "sclk_usbphy0",
112 static struct clk exynos4_clk_sclk_usbphy1 = {
113 .name = "sclk_usbphy1",
116 static struct clk dummy_apb_pclk = {
121 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
123 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
126 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
128 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
133 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
136 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
138 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
143 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
148 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
151 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
153 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
156 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
158 return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
161 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
163 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
166 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
168 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
171 int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
173 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
176 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
178 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
181 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
183 return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
186 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
188 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
191 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
193 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
196 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
198 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
201 int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
203 return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
206 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
208 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
211 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
213 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
216 /* Core list of CMU_CPU side */
218 static struct clksrc_clk exynos4_clk_mout_apll = {
222 .sources = &clk_src_apll,
223 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
226 static struct clksrc_clk exynos4_clk_sclk_apll = {
229 .parent = &exynos4_clk_mout_apll.clk,
231 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
234 static struct clksrc_clk exynos4_clk_mout_epll = {
238 .sources = &clk_src_epll,
239 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
242 struct clksrc_clk exynos4_clk_mout_mpll = {
246 .sources = &clk_src_mpll,
248 /* reg_src will be added in each SoCs' clock */
251 static struct clk *exynos4_clkset_moutcore_list[] = {
252 [0] = &exynos4_clk_mout_apll.clk,
253 [1] = &exynos4_clk_mout_mpll.clk,
256 static struct clksrc_sources exynos4_clkset_moutcore = {
257 .sources = exynos4_clkset_moutcore_list,
258 .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
261 static struct clksrc_clk exynos4_clk_moutcore = {
265 .sources = &exynos4_clkset_moutcore,
266 .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
269 static struct clksrc_clk exynos4_clk_coreclk = {
272 .parent = &exynos4_clk_moutcore.clk,
274 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
277 static struct clksrc_clk exynos4_clk_armclk = {
280 .parent = &exynos4_clk_coreclk.clk,
284 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
286 .name = "aclk_corem0",
287 .parent = &exynos4_clk_coreclk.clk,
289 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
292 static struct clksrc_clk exynos4_clk_aclk_cores = {
294 .name = "aclk_cores",
295 .parent = &exynos4_clk_coreclk.clk,
297 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
300 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
302 .name = "aclk_corem1",
303 .parent = &exynos4_clk_coreclk.clk,
305 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
308 static struct clksrc_clk exynos4_clk_periphclk = {
311 .parent = &exynos4_clk_coreclk.clk,
313 .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
316 /* Core list of CMU_CORE side */
318 static struct clk *exynos4_clkset_corebus_list[] = {
319 [0] = &exynos4_clk_mout_mpll.clk,
320 [1] = &exynos4_clk_sclk_apll.clk,
323 struct clksrc_sources exynos4_clkset_mout_corebus = {
324 .sources = exynos4_clkset_corebus_list,
325 .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
328 static struct clksrc_clk exynos4_clk_mout_corebus = {
330 .name = "mout_corebus",
332 .sources = &exynos4_clkset_mout_corebus,
333 .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
336 static struct clksrc_clk exynos4_clk_sclk_dmc = {
339 .parent = &exynos4_clk_mout_corebus.clk,
341 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
344 static struct clksrc_clk exynos4_clk_aclk_cored = {
346 .name = "aclk_cored",
347 .parent = &exynos4_clk_sclk_dmc.clk,
349 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
352 static struct clksrc_clk exynos4_clk_aclk_corep = {
354 .name = "aclk_corep",
355 .parent = &exynos4_clk_aclk_cored.clk,
357 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
360 static struct clksrc_clk exynos4_clk_aclk_acp = {
363 .parent = &exynos4_clk_mout_corebus.clk,
365 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
368 static struct clksrc_clk exynos4_clk_pclk_acp = {
371 .parent = &exynos4_clk_aclk_acp.clk,
373 .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
376 /* Core list of CMU_TOP side */
378 struct clk *exynos4_clkset_aclk_top_list[] = {
379 [0] = &exynos4_clk_mout_mpll.clk,
380 [1] = &exynos4_clk_sclk_apll.clk,
383 static struct clksrc_sources exynos4_clkset_aclk = {
384 .sources = exynos4_clkset_aclk_top_list,
385 .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
388 static struct clksrc_clk exynos4_clk_aclk_200 = {
392 .sources = &exynos4_clkset_aclk,
393 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
394 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
397 static struct clksrc_clk exynos4_clk_aclk_100 = {
401 .sources = &exynos4_clkset_aclk,
402 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
403 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
406 static struct clksrc_clk exynos4_clk_aclk_160 = {
410 .sources = &exynos4_clkset_aclk,
411 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
412 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
415 struct clksrc_clk exynos4_clk_aclk_133 = {
419 .sources = &exynos4_clkset_aclk,
420 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
421 .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
424 static struct clk *exynos4_clkset_vpllsrc_list[] = {
426 [1] = &exynos4_clk_sclk_hdmi27m,
429 static struct clksrc_sources exynos4_clkset_vpllsrc = {
430 .sources = exynos4_clkset_vpllsrc_list,
431 .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
434 static struct clksrc_clk exynos4_clk_vpllsrc = {
437 .enable = exynos4_clksrc_mask_top_ctrl,
440 .sources = &exynos4_clkset_vpllsrc,
441 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
444 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
445 [0] = &exynos4_clk_vpllsrc.clk,
446 [1] = &clk_fout_vpll,
449 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
450 .sources = exynos4_clkset_sclk_vpll_list,
451 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
454 static struct clksrc_clk exynos4_clk_sclk_vpll = {
458 .sources = &exynos4_clkset_sclk_vpll,
459 .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
462 static struct clk exynos4_init_clocks_off[] = {
465 .parent = &exynos4_clk_aclk_100.clk,
466 .enable = exynos4_clk_ip_peril_ctrl,
470 .devname = "s5p-mipi-csis.0",
471 .enable = exynos4_clk_ip_cam_ctrl,
475 .devname = "s5p-mipi-csis.1",
476 .enable = exynos4_clk_ip_cam_ctrl,
481 .enable = exynos4_clk_ip_cam_ctrl,
485 .devname = "exynos4-fimc.0",
486 .enable = exynos4_clk_ip_cam_ctrl,
490 .devname = "exynos4-fimc.1",
491 .enable = exynos4_clk_ip_cam_ctrl,
495 .devname = "exynos4-fimc.2",
496 .enable = exynos4_clk_ip_cam_ctrl,
500 .devname = "exynos4-fimc.3",
501 .enable = exynos4_clk_ip_cam_ctrl,
505 .devname = "exynos4-sdhci.0",
506 .parent = &exynos4_clk_aclk_133.clk,
507 .enable = exynos4_clk_ip_fsys_ctrl,
511 .devname = "exynos4-sdhci.1",
512 .parent = &exynos4_clk_aclk_133.clk,
513 .enable = exynos4_clk_ip_fsys_ctrl,
517 .devname = "exynos4-sdhci.2",
518 .parent = &exynos4_clk_aclk_133.clk,
519 .enable = exynos4_clk_ip_fsys_ctrl,
523 .devname = "exynos4-sdhci.3",
524 .parent = &exynos4_clk_aclk_133.clk,
525 .enable = exynos4_clk_ip_fsys_ctrl,
529 .parent = &exynos4_clk_aclk_133.clk,
530 .enable = exynos4_clk_ip_fsys_ctrl,
534 .devname = "s5p-sdo",
535 .enable = exynos4_clk_ip_tv_ctrl,
539 .devname = "s5p-mixer",
540 .enable = exynos4_clk_ip_tv_ctrl,
544 .devname = "s5p-mixer",
545 .enable = exynos4_clk_ip_tv_ctrl,
549 .devname = "exynos4-hdmi",
550 .enable = exynos4_clk_ip_tv_ctrl,
554 .devname = "exynos4-hdmi",
555 .enable = exynos4_clk_hdmiphy_ctrl,
559 .devname = "s5p-sdo",
560 .enable = exynos4_clk_dac_ctrl,
564 .enable = exynos4_clk_ip_peril_ctrl,
565 .ctrlbit = (1 << 15),
568 .enable = exynos4_clk_ip_perir_ctrl,
569 .ctrlbit = (1 << 16),
572 .enable = exynos4_clk_ip_perir_ctrl,
573 .ctrlbit = (1 << 15),
576 .parent = &exynos4_clk_aclk_100.clk,
577 .enable = exynos4_clk_ip_perir_ctrl,
578 .ctrlbit = (1 << 14),
581 .enable = exynos4_clk_ip_fsys_ctrl ,
582 .ctrlbit = (1 << 12),
585 .enable = exynos4_clk_ip_fsys_ctrl,
586 .ctrlbit = (1 << 13),
589 .devname = "s3c64xx-spi.0",
590 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 16),
594 .devname = "s3c64xx-spi.1",
595 .enable = exynos4_clk_ip_peril_ctrl,
596 .ctrlbit = (1 << 17),
599 .devname = "s3c64xx-spi.2",
600 .enable = exynos4_clk_ip_peril_ctrl,
601 .ctrlbit = (1 << 18),
604 .devname = "samsung-i2s.0",
605 .enable = exynos4_clk_ip_peril_ctrl,
606 .ctrlbit = (1 << 19),
609 .devname = "samsung-i2s.1",
610 .enable = exynos4_clk_ip_peril_ctrl,
611 .ctrlbit = (1 << 20),
614 .devname = "samsung-i2s.2",
615 .enable = exynos4_clk_ip_peril_ctrl,
616 .ctrlbit = (1 << 21),
619 .devname = "samsung-ac97",
620 .enable = exynos4_clk_ip_peril_ctrl,
621 .ctrlbit = (1 << 27),
624 .enable = exynos4_clk_ip_image_ctrl,
628 .devname = "s5p-mfc",
629 .enable = exynos4_clk_ip_mfc_ctrl,
633 .devname = "s3c2440-i2c.0",
634 .parent = &exynos4_clk_aclk_100.clk,
635 .enable = exynos4_clk_ip_peril_ctrl,
639 .devname = "s3c2440-i2c.1",
640 .parent = &exynos4_clk_aclk_100.clk,
641 .enable = exynos4_clk_ip_peril_ctrl,
645 .devname = "s3c2440-i2c.2",
646 .parent = &exynos4_clk_aclk_100.clk,
647 .enable = exynos4_clk_ip_peril_ctrl,
651 .devname = "s3c2440-i2c.3",
652 .parent = &exynos4_clk_aclk_100.clk,
653 .enable = exynos4_clk_ip_peril_ctrl,
657 .devname = "s3c2440-i2c.4",
658 .parent = &exynos4_clk_aclk_100.clk,
659 .enable = exynos4_clk_ip_peril_ctrl,
660 .ctrlbit = (1 << 10),
663 .devname = "s3c2440-i2c.5",
664 .parent = &exynos4_clk_aclk_100.clk,
665 .enable = exynos4_clk_ip_peril_ctrl,
666 .ctrlbit = (1 << 11),
669 .devname = "s3c2440-i2c.6",
670 .parent = &exynos4_clk_aclk_100.clk,
671 .enable = exynos4_clk_ip_peril_ctrl,
672 .ctrlbit = (1 << 12),
675 .devname = "s3c2440-i2c.7",
676 .parent = &exynos4_clk_aclk_100.clk,
677 .enable = exynos4_clk_ip_peril_ctrl,
678 .ctrlbit = (1 << 13),
681 .devname = "s3c2440-hdmiphy-i2c",
682 .parent = &exynos4_clk_aclk_100.clk,
683 .enable = exynos4_clk_ip_peril_ctrl,
684 .ctrlbit = (1 << 14),
686 .name = SYSMMU_CLOCK_NAME,
687 .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
688 .enable = exynos4_clk_ip_mfc_ctrl,
691 .name = SYSMMU_CLOCK_NAME,
692 .devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
693 .enable = exynos4_clk_ip_mfc_ctrl,
696 .name = SYSMMU_CLOCK_NAME,
697 .devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
698 .enable = exynos4_clk_ip_tv_ctrl,
701 .name = SYSMMU_CLOCK_NAME,
702 .devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
703 .enable = exynos4_clk_ip_cam_ctrl,
704 .ctrlbit = (1 << 11),
706 .name = SYSMMU_CLOCK_NAME,
707 .devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
708 .enable = exynos4_clk_ip_image_ctrl,
711 .name = SYSMMU_CLOCK_NAME,
712 .devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
713 .enable = exynos4_clk_ip_cam_ctrl,
716 .name = SYSMMU_CLOCK_NAME,
717 .devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
718 .enable = exynos4_clk_ip_cam_ctrl,
721 .name = SYSMMU_CLOCK_NAME,
722 .devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
723 .enable = exynos4_clk_ip_cam_ctrl,
726 .name = SYSMMU_CLOCK_NAME,
727 .devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
728 .enable = exynos4_clk_ip_cam_ctrl,
729 .ctrlbit = (1 << 10),
731 .name = SYSMMU_CLOCK_NAME,
732 .devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
733 .enable = exynos4_clk_ip_lcd0_ctrl,
738 static struct clk exynos4_init_clocks_on[] = {
741 .devname = "s5pv210-uart.0",
742 .enable = exynos4_clk_ip_peril_ctrl,
746 .devname = "s5pv210-uart.1",
747 .enable = exynos4_clk_ip_peril_ctrl,
751 .devname = "s5pv210-uart.2",
752 .enable = exynos4_clk_ip_peril_ctrl,
756 .devname = "s5pv210-uart.3",
757 .enable = exynos4_clk_ip_peril_ctrl,
761 .devname = "s5pv210-uart.4",
762 .enable = exynos4_clk_ip_peril_ctrl,
766 .devname = "s5pv210-uart.5",
767 .enable = exynos4_clk_ip_peril_ctrl,
772 static struct clk exynos4_clk_pdma0 = {
774 .devname = "dma-pl330.0",
775 .enable = exynos4_clk_ip_fsys_ctrl,
779 static struct clk exynos4_clk_pdma1 = {
781 .devname = "dma-pl330.1",
782 .enable = exynos4_clk_ip_fsys_ctrl,
786 static struct clk exynos4_clk_mdma1 = {
788 .devname = "dma-pl330.2",
789 .enable = exynos4_clk_ip_image_ctrl,
790 .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
793 static struct clk exynos4_clk_fimd0 = {
795 .devname = "exynos4-fb.0",
796 .enable = exynos4_clk_ip_lcd0_ctrl,
800 struct clk *exynos4_clkset_group_list[] = {
801 [0] = &clk_ext_xtal_mux,
803 [2] = &exynos4_clk_sclk_hdmi27m,
804 [3] = &exynos4_clk_sclk_usbphy0,
805 [4] = &exynos4_clk_sclk_usbphy1,
806 [5] = &exynos4_clk_sclk_hdmiphy,
807 [6] = &exynos4_clk_mout_mpll.clk,
808 [7] = &exynos4_clk_mout_epll.clk,
809 [8] = &exynos4_clk_sclk_vpll.clk,
812 struct clksrc_sources exynos4_clkset_group = {
813 .sources = exynos4_clkset_group_list,
814 .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
817 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
818 [0] = &exynos4_clk_mout_mpll.clk,
819 [1] = &exynos4_clk_sclk_apll.clk,
822 static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
823 .sources = exynos4_clkset_mout_g2d0_list,
824 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
827 static struct clksrc_clk exynos4_clk_mout_g2d0 = {
831 .sources = &exynos4_clkset_mout_g2d0,
832 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
835 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
836 [0] = &exynos4_clk_mout_epll.clk,
837 [1] = &exynos4_clk_sclk_vpll.clk,
840 static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
841 .sources = exynos4_clkset_mout_g2d1_list,
842 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
845 static struct clksrc_clk exynos4_clk_mout_g2d1 = {
849 .sources = &exynos4_clkset_mout_g2d1,
850 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
853 static struct clk *exynos4_clkset_mout_g2d_list[] = {
854 [0] = &exynos4_clk_mout_g2d0.clk,
855 [1] = &exynos4_clk_mout_g2d1.clk,
858 static struct clksrc_sources exynos4_clkset_mout_g2d = {
859 .sources = exynos4_clkset_mout_g2d_list,
860 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
863 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
864 [0] = &exynos4_clk_mout_mpll.clk,
865 [1] = &exynos4_clk_sclk_apll.clk,
868 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
869 .sources = exynos4_clkset_mout_mfc0_list,
870 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
873 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
877 .sources = &exynos4_clkset_mout_mfc0,
878 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
881 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
882 [0] = &exynos4_clk_mout_epll.clk,
883 [1] = &exynos4_clk_sclk_vpll.clk,
886 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
887 .sources = exynos4_clkset_mout_mfc1_list,
888 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
891 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
895 .sources = &exynos4_clkset_mout_mfc1,
896 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
899 static struct clk *exynos4_clkset_mout_mfc_list[] = {
900 [0] = &exynos4_clk_mout_mfc0.clk,
901 [1] = &exynos4_clk_mout_mfc1.clk,
904 static struct clksrc_sources exynos4_clkset_mout_mfc = {
905 .sources = exynos4_clkset_mout_mfc_list,
906 .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
909 static struct clk *exynos4_clkset_sclk_dac_list[] = {
910 [0] = &exynos4_clk_sclk_vpll.clk,
911 [1] = &exynos4_clk_sclk_hdmiphy,
914 static struct clksrc_sources exynos4_clkset_sclk_dac = {
915 .sources = exynos4_clkset_sclk_dac_list,
916 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
919 static struct clksrc_clk exynos4_clk_sclk_dac = {
922 .enable = exynos4_clksrc_mask_tv_ctrl,
925 .sources = &exynos4_clkset_sclk_dac,
926 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
929 static struct clksrc_clk exynos4_clk_sclk_pixel = {
931 .name = "sclk_pixel",
932 .parent = &exynos4_clk_sclk_vpll.clk,
934 .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
937 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
938 [0] = &exynos4_clk_sclk_pixel.clk,
939 [1] = &exynos4_clk_sclk_hdmiphy,
942 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
943 .sources = exynos4_clkset_sclk_hdmi_list,
944 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
947 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
950 .enable = exynos4_clksrc_mask_tv_ctrl,
953 .sources = &exynos4_clkset_sclk_hdmi,
954 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
957 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
958 [0] = &exynos4_clk_sclk_dac.clk,
959 [1] = &exynos4_clk_sclk_hdmi.clk,
962 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
963 .sources = exynos4_clkset_sclk_mixer_list,
964 .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
967 static struct clksrc_clk exynos4_clk_sclk_mixer = {
969 .name = "sclk_mixer",
970 .enable = exynos4_clksrc_mask_tv_ctrl,
973 .sources = &exynos4_clkset_sclk_mixer,
974 .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
977 static struct clksrc_clk *exynos4_sclk_tv[] = {
978 &exynos4_clk_sclk_dac,
979 &exynos4_clk_sclk_pixel,
980 &exynos4_clk_sclk_hdmi,
981 &exynos4_clk_sclk_mixer,
984 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
988 .sources = &exynos4_clkset_group,
989 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
990 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
993 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
997 .sources = &exynos4_clkset_group,
998 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
999 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1002 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
1004 .name = "dout_mmc2",
1006 .sources = &exynos4_clkset_group,
1007 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1008 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1011 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1013 .name = "dout_mmc3",
1015 .sources = &exynos4_clkset_group,
1016 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1017 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1020 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1022 .name = "dout_mmc4",
1024 .sources = &exynos4_clkset_group,
1025 .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1026 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1029 static struct clksrc_clk exynos4_clksrcs[] = {
1033 .enable = exynos4_clksrc_mask_peril0_ctrl,
1034 .ctrlbit = (1 << 24),
1036 .sources = &exynos4_clkset_group,
1037 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1038 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1041 .name = "sclk_csis",
1042 .devname = "s5p-mipi-csis.0",
1043 .enable = exynos4_clksrc_mask_cam_ctrl,
1044 .ctrlbit = (1 << 24),
1046 .sources = &exynos4_clkset_group,
1047 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1048 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1051 .name = "sclk_csis",
1052 .devname = "s5p-mipi-csis.1",
1053 .enable = exynos4_clksrc_mask_cam_ctrl,
1054 .ctrlbit = (1 << 28),
1056 .sources = &exynos4_clkset_group,
1057 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1058 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1061 .name = "sclk_cam0",
1062 .enable = exynos4_clksrc_mask_cam_ctrl,
1063 .ctrlbit = (1 << 16),
1065 .sources = &exynos4_clkset_group,
1066 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1067 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1070 .name = "sclk_cam1",
1071 .enable = exynos4_clksrc_mask_cam_ctrl,
1072 .ctrlbit = (1 << 20),
1074 .sources = &exynos4_clkset_group,
1075 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1076 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1079 .name = "sclk_fimc",
1080 .devname = "exynos4-fimc.0",
1081 .enable = exynos4_clksrc_mask_cam_ctrl,
1082 .ctrlbit = (1 << 0),
1084 .sources = &exynos4_clkset_group,
1085 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1086 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1089 .name = "sclk_fimc",
1090 .devname = "exynos4-fimc.1",
1091 .enable = exynos4_clksrc_mask_cam_ctrl,
1092 .ctrlbit = (1 << 4),
1094 .sources = &exynos4_clkset_group,
1095 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1096 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1099 .name = "sclk_fimc",
1100 .devname = "exynos4-fimc.2",
1101 .enable = exynos4_clksrc_mask_cam_ctrl,
1102 .ctrlbit = (1 << 8),
1104 .sources = &exynos4_clkset_group,
1105 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1106 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1109 .name = "sclk_fimc",
1110 .devname = "exynos4-fimc.3",
1111 .enable = exynos4_clksrc_mask_cam_ctrl,
1112 .ctrlbit = (1 << 12),
1114 .sources = &exynos4_clkset_group,
1115 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1116 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1119 .name = "sclk_fimd",
1120 .devname = "exynos4-fb.0",
1121 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1122 .ctrlbit = (1 << 0),
1124 .sources = &exynos4_clkset_group,
1125 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1126 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1129 .name = "sclk_fimg2d",
1131 .sources = &exynos4_clkset_mout_g2d,
1132 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1133 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1137 .devname = "s5p-mfc",
1139 .sources = &exynos4_clkset_mout_mfc,
1140 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1141 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1144 .name = "sclk_dwmmc",
1145 .parent = &exynos4_clk_dout_mmc4.clk,
1146 .enable = exynos4_clksrc_mask_fsys_ctrl,
1147 .ctrlbit = (1 << 16),
1149 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1153 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1156 .devname = "exynos4210-uart.0",
1157 .enable = exynos4_clksrc_mask_peril0_ctrl,
1158 .ctrlbit = (1 << 0),
1160 .sources = &exynos4_clkset_group,
1161 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1162 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1165 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1168 .devname = "exynos4210-uart.1",
1169 .enable = exynos4_clksrc_mask_peril0_ctrl,
1170 .ctrlbit = (1 << 4),
1172 .sources = &exynos4_clkset_group,
1173 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1174 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1177 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1180 .devname = "exynos4210-uart.2",
1181 .enable = exynos4_clksrc_mask_peril0_ctrl,
1182 .ctrlbit = (1 << 8),
1184 .sources = &exynos4_clkset_group,
1185 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1186 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1189 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1192 .devname = "exynos4210-uart.3",
1193 .enable = exynos4_clksrc_mask_peril0_ctrl,
1194 .ctrlbit = (1 << 12),
1196 .sources = &exynos4_clkset_group,
1197 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1198 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1201 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1204 .devname = "exynos4-sdhci.0",
1205 .parent = &exynos4_clk_dout_mmc0.clk,
1206 .enable = exynos4_clksrc_mask_fsys_ctrl,
1207 .ctrlbit = (1 << 0),
1209 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1212 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1215 .devname = "exynos4-sdhci.1",
1216 .parent = &exynos4_clk_dout_mmc1.clk,
1217 .enable = exynos4_clksrc_mask_fsys_ctrl,
1218 .ctrlbit = (1 << 4),
1220 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1223 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1226 .devname = "exynos4-sdhci.2",
1227 .parent = &exynos4_clk_dout_mmc2.clk,
1228 .enable = exynos4_clksrc_mask_fsys_ctrl,
1229 .ctrlbit = (1 << 8),
1231 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1234 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1237 .devname = "exynos4-sdhci.3",
1238 .parent = &exynos4_clk_dout_mmc3.clk,
1239 .enable = exynos4_clksrc_mask_fsys_ctrl,
1240 .ctrlbit = (1 << 12),
1242 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1245 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1248 .devname = "s3c64xx-spi.0",
1249 .enable = exynos4_clksrc_mask_peril1_ctrl,
1250 .ctrlbit = (1 << 16),
1252 .sources = &exynos4_clkset_group,
1253 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1254 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1257 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1260 .devname = "s3c64xx-spi.1",
1261 .enable = exynos4_clksrc_mask_peril1_ctrl,
1262 .ctrlbit = (1 << 20),
1264 .sources = &exynos4_clkset_group,
1265 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1266 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1269 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1272 .devname = "s3c64xx-spi.2",
1273 .enable = exynos4_clksrc_mask_peril1_ctrl,
1274 .ctrlbit = (1 << 24),
1276 .sources = &exynos4_clkset_group,
1277 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1278 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1281 /* Clock initialization code */
1282 static struct clksrc_clk *exynos4_sysclks[] = {
1283 &exynos4_clk_mout_apll,
1284 &exynos4_clk_sclk_apll,
1285 &exynos4_clk_mout_epll,
1286 &exynos4_clk_mout_mpll,
1287 &exynos4_clk_moutcore,
1288 &exynos4_clk_coreclk,
1289 &exynos4_clk_armclk,
1290 &exynos4_clk_aclk_corem0,
1291 &exynos4_clk_aclk_cores,
1292 &exynos4_clk_aclk_corem1,
1293 &exynos4_clk_periphclk,
1294 &exynos4_clk_mout_corebus,
1295 &exynos4_clk_sclk_dmc,
1296 &exynos4_clk_aclk_cored,
1297 &exynos4_clk_aclk_corep,
1298 &exynos4_clk_aclk_acp,
1299 &exynos4_clk_pclk_acp,
1300 &exynos4_clk_vpllsrc,
1301 &exynos4_clk_sclk_vpll,
1302 &exynos4_clk_aclk_200,
1303 &exynos4_clk_aclk_100,
1304 &exynos4_clk_aclk_160,
1305 &exynos4_clk_aclk_133,
1306 &exynos4_clk_dout_mmc0,
1307 &exynos4_clk_dout_mmc1,
1308 &exynos4_clk_dout_mmc2,
1309 &exynos4_clk_dout_mmc3,
1310 &exynos4_clk_dout_mmc4,
1311 &exynos4_clk_mout_mfc0,
1312 &exynos4_clk_mout_mfc1,
1315 static struct clk *exynos4_clk_cdev[] = {
1322 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1323 &exynos4_clk_sclk_uart0,
1324 &exynos4_clk_sclk_uart1,
1325 &exynos4_clk_sclk_uart2,
1326 &exynos4_clk_sclk_uart3,
1327 &exynos4_clk_sclk_mmc0,
1328 &exynos4_clk_sclk_mmc1,
1329 &exynos4_clk_sclk_mmc2,
1330 &exynos4_clk_sclk_mmc3,
1331 &exynos4_clk_sclk_spi0,
1332 &exynos4_clk_sclk_spi1,
1333 &exynos4_clk_sclk_spi2,
1337 static struct clk_lookup exynos4_clk_lookup[] = {
1338 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1339 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1340 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1341 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1342 CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1343 CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1344 CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1345 CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1346 CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1347 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1348 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1349 CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1350 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1351 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1352 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1355 static int xtal_rate;
1357 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1359 if (soc_is_exynos4210())
1360 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1362 else if (soc_is_exynos4212() || soc_is_exynos4412())
1363 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1368 static struct clk_ops exynos4_fout_apll_ops = {
1369 .get_rate = exynos4_fout_apll_get_rate,
1372 static u32 exynos4_vpll_div[][8] = {
1373 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1374 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1377 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1382 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1384 unsigned int vpll_con0, vpll_con1 = 0;
1387 /* Return if nothing changed */
1388 if (clk->rate == rate)
1391 vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1392 vpll_con0 &= ~(0x1 << 27 | \
1393 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1394 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1395 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1397 vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1398 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1399 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1400 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1402 for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1403 if (exynos4_vpll_div[i][0] == rate) {
1404 vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1405 vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1406 vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1407 vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1408 vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1409 vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1410 vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1415 if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1416 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1421 __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1422 __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1424 /* Wait for VPLL lock */
1425 while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1432 static struct clk_ops exynos4_vpll_ops = {
1433 .get_rate = exynos4_vpll_get_rate,
1434 .set_rate = exynos4_vpll_set_rate,
1437 void __init_or_cpufreq exynos4_setup_clocks(void)
1439 struct clk *xtal_clk;
1440 unsigned long apll = 0;
1441 unsigned long mpll = 0;
1442 unsigned long epll = 0;
1443 unsigned long vpll = 0;
1444 unsigned long vpllsrc;
1446 unsigned long armclk;
1447 unsigned long sclk_dmc;
1448 unsigned long aclk_200;
1449 unsigned long aclk_100;
1450 unsigned long aclk_160;
1451 unsigned long aclk_133;
1454 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1456 xtal_clk = clk_get(NULL, "xtal");
1457 BUG_ON(IS_ERR(xtal_clk));
1459 xtal = clk_get_rate(xtal_clk);
1465 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1467 if (soc_is_exynos4210()) {
1468 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1470 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1472 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1473 __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1475 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1476 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1477 __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1478 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1479 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1480 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1481 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1482 __raw_readl(EXYNOS4_EPLL_CON1));
1484 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1485 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1486 __raw_readl(EXYNOS4_VPLL_CON1));
1491 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1492 clk_fout_mpll.rate = mpll;
1493 clk_fout_epll.rate = epll;
1494 clk_fout_vpll.ops = &exynos4_vpll_ops;
1495 clk_fout_vpll.rate = vpll;
1497 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1498 apll, mpll, epll, vpll);
1500 armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1501 sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1503 aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1504 aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1505 aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1506 aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1508 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1509 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1510 armclk, sclk_dmc, aclk_200,
1511 aclk_100, aclk_160, aclk_133);
1513 clk_f.rate = armclk;
1514 clk_h.rate = sclk_dmc;
1515 clk_p.rate = aclk_100;
1517 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1518 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1521 static struct clk *exynos4_clks[] __initdata = {
1522 &exynos4_clk_sclk_hdmi27m,
1523 &exynos4_clk_sclk_hdmiphy,
1524 &exynos4_clk_sclk_usbphy0,
1525 &exynos4_clk_sclk_usbphy1,
1528 #ifdef CONFIG_PM_SLEEP
1529 static int exynos4_clock_suspend(void)
1531 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1535 static void exynos4_clock_resume(void)
1537 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1541 #define exynos4_clock_suspend NULL
1542 #define exynos4_clock_resume NULL
1545 static struct syscore_ops exynos4_clock_syscore_ops = {
1546 .suspend = exynos4_clock_suspend,
1547 .resume = exynos4_clock_resume,
1550 void __init exynos4_register_clocks(void)
1554 s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1556 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1557 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1559 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1560 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1562 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1563 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1565 s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1566 s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1568 s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1569 for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1570 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1572 s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1573 s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1574 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1576 register_syscore_ops(&exynos4_clock_syscore_ops);
1577 s3c24xx_register_clock(&dummy_apb_pclk);