arch/arm/mach-exynos/clock-exynos4.c

   1 /*
   2  * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4 - Clock support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/err.h>
  14 #include <linux/io.h>
  15 #include <linux/syscore_ops.h>
  16
  17 #include <plat/cpu-freq.h>
  18 #include <plat/clock.h>
  19 #include <plat/cpu.h>
  20 #include <plat/pll.h>
  21 #include <plat/s5p-clock.h>
  22 #include <plat/clock-clksrc.h>
  23 #include <plat/pm.h>
  24
  25 #include <mach/map.h>
  26 #include <mach/regs-clock.h>
  27 #include <mach/sysmmu.h>
  28
  29 #include "common.h"
  30 #include "clock-exynos4.h"
  31
  32 #ifdef CONFIG_PM_SLEEP
  33 static struct sleep_save exynos4_clock_save[] = {
  34         SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
  35         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
  36         SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
  37         SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
  38         SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
  39         SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
  40         SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
  41         SAVE_ITEM(EXYNOS4_CLKSRC_TV),
  42         SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
  43         SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
  44         SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
  45         SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
  46         SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
  47         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
  48         SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
  49         SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
  50         SAVE_ITEM(EXYNOS4_CLKDIV_TV),
  51         SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
  52         SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
  53         SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
  54         SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
  55         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
  56         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
  57         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
  58         SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
  59         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
  60         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
  61         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
  62         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
  63         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
  64         SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
  65         SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
  66         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
  67         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
  68         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
  69         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
  70         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
  71         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
  72         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
  73         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
  74         SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
  75         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
  76         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
  77         SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
  78         SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
  79         SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
  80         SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
  81         SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
  82         SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
  83         SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
  84         SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
  85         SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
  86         SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
  87         SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
  88         SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
  89         SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
  90         SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
  91         SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
  92         SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
  93         SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
  94         SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
  95 };
  96 #endif
  97
  98 static struct clk exynos4_clk_sclk_hdmi27m = {
  99         .name           = "sclk_hdmi27m",
 100         .rate           = 27000000,
 101 };
 102
 103 static struct clk exynos4_clk_sclk_hdmiphy = {
 104         .name           = "sclk_hdmiphy",
 105 };
 106
 107 static struct clk exynos4_clk_sclk_usbphy0 = {
 108         .name           = "sclk_usbphy0",
 109         .rate           = 27000000,
 110 };
 111
 112 static struct clk exynos4_clk_sclk_usbphy1 = {
 113         .name           = "sclk_usbphy1",
 114 };
 115
 116 static struct clk dummy_apb_pclk = {
 117         .name           = "apb_pclk",
 118         .id             = -1,
 119 };
 120
 121 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
 122 {
 123         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
 124 }
 125
 126 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
 127 {
 128         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
 129 }
 130
 131 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
 132 {
 133         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
 134 }
 135
 136 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
 137 {
 138         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
 139 }
 140
 141 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
 142 {
 143         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
 144 }
 145
 146 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
 147 {
 148         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
 149 }
 150
 151 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 152 {
 153         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
 154 }
 155
 156 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
 157 {
 158         return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
 159 }
 160
 161 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
 162 {
 163         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
 164 }
 165
 166 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
 167 {
 168         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
 169 }
 170
 171 int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
 172 {
 173         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
 174 }
 175
 176 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
 177 {
 178         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
 179 }
 180
 181 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
 182 {
 183         return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
 184 }
 185
 186 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
 187 {
 188         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
 189 }
 190
 191 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
 192 {
 193         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
 194 }
 195
 196 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
 197 {
 198         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
 199 }
 200
 201 int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
 202 {
 203         return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
 204 }
 205
 206 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
 207 {
 208         return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
 209 }
 210
 211 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
 212 {
 213         return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
 214 }
 215
 216 /* Core list of CMU_CPU side */
 217
 218 static struct clksrc_clk exynos4_clk_mout_apll = {
 219         .clk    = {
 220                 .name           = "mout_apll",
 221         },
 222         .sources = &clk_src_apll,
 223         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
 224 };
 225
 226 static struct clksrc_clk exynos4_clk_sclk_apll = {
 227         .clk    = {
 228                 .name           = "sclk_apll",
 229                 .parent         = &exynos4_clk_mout_apll.clk,
 230         },
 231         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
 232 };
 233
 234 static struct clksrc_clk exynos4_clk_mout_epll = {
 235         .clk    = {
 236                 .name           = "mout_epll",
 237         },
 238         .sources = &clk_src_epll,
 239         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
 240 };
 241
 242 struct clksrc_clk exynos4_clk_mout_mpll = {
 243         .clk    = {
 244                 .name           = "mout_mpll",
 245         },
 246         .sources = &clk_src_mpll,
 247
 248         /* reg_src will be added in each SoCs' clock */
 249 };
 250
 251 static struct clk *exynos4_clkset_moutcore_list[] = {
 252         [0] = &exynos4_clk_mout_apll.clk,
 253         [1] = &exynos4_clk_mout_mpll.clk,
 254 };
 255
 256 static struct clksrc_sources exynos4_clkset_moutcore = {
 257         .sources        = exynos4_clkset_moutcore_list,
 258         .nr_sources     = ARRAY_SIZE(exynos4_clkset_moutcore_list),
 259 };
 260
 261 static struct clksrc_clk exynos4_clk_moutcore = {
 262         .clk    = {
 263                 .name           = "moutcore",
 264         },
 265         .sources = &exynos4_clkset_moutcore,
 266         .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
 267 };
 268
 269 static struct clksrc_clk exynos4_clk_coreclk = {
 270         .clk    = {
 271                 .name           = "core_clk",
 272                 .parent         = &exynos4_clk_moutcore.clk,
 273         },
 274         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
 275 };
 276
 277 static struct clksrc_clk exynos4_clk_armclk = {
 278         .clk    = {
 279                 .name           = "armclk",
 280                 .parent         = &exynos4_clk_coreclk.clk,
 281         },
 282 };
 283
 284 static struct clksrc_clk exynos4_clk_aclk_corem0 = {
 285         .clk    = {
 286                 .name           = "aclk_corem0",
 287                 .parent         = &exynos4_clk_coreclk.clk,
 288         },
 289         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 290 };
 291
 292 static struct clksrc_clk exynos4_clk_aclk_cores = {
 293         .clk    = {
 294                 .name           = "aclk_cores",
 295                 .parent         = &exynos4_clk_coreclk.clk,
 296         },
 297         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
 298 };
 299
 300 static struct clksrc_clk exynos4_clk_aclk_corem1 = {
 301         .clk    = {
 302                 .name           = "aclk_corem1",
 303                 .parent         = &exynos4_clk_coreclk.clk,
 304         },
 305         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
 306 };
 307
 308 static struct clksrc_clk exynos4_clk_periphclk = {
 309         .clk    = {
 310                 .name           = "periphclk",
 311                 .parent         = &exynos4_clk_coreclk.clk,
 312         },
 313         .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
 314 };
 315
 316 /* Core list of CMU_CORE side */
 317
 318 static struct clk *exynos4_clkset_corebus_list[] = {
 319         [0] = &exynos4_clk_mout_mpll.clk,
 320         [1] = &exynos4_clk_sclk_apll.clk,
 321 };
 322
 323 struct clksrc_sources exynos4_clkset_mout_corebus = {
 324         .sources        = exynos4_clkset_corebus_list,
 325         .nr_sources     = ARRAY_SIZE(exynos4_clkset_corebus_list),
 326 };
 327
 328 static struct clksrc_clk exynos4_clk_mout_corebus = {
 329         .clk    = {
 330                 .name           = "mout_corebus",
 331         },
 332         .sources = &exynos4_clkset_mout_corebus,
 333         .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
 334 };
 335
 336 static struct clksrc_clk exynos4_clk_sclk_dmc = {
 337         .clk    = {
 338                 .name           = "sclk_dmc",
 339                 .parent         = &exynos4_clk_mout_corebus.clk,
 340         },
 341         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
 342 };
 343
 344 static struct clksrc_clk exynos4_clk_aclk_cored = {
 345         .clk    = {
 346                 .name           = "aclk_cored",
 347                 .parent         = &exynos4_clk_sclk_dmc.clk,
 348         },
 349         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
 350 };
 351
 352 static struct clksrc_clk exynos4_clk_aclk_corep = {
 353         .clk    = {
 354                 .name           = "aclk_corep",
 355                 .parent         = &exynos4_clk_aclk_cored.clk,
 356         },
 357         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
 358 };
 359
 360 static struct clksrc_clk exynos4_clk_aclk_acp = {
 361         .clk    = {
 362                 .name           = "aclk_acp",
 363                 .parent         = &exynos4_clk_mout_corebus.clk,
 364         },
 365         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
 366 };
 367
 368 static struct clksrc_clk exynos4_clk_pclk_acp = {
 369         .clk    = {
 370                 .name           = "pclk_acp",
 371                 .parent         = &exynos4_clk_aclk_acp.clk,
 372         },
 373         .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
 374 };
 375
 376 /* Core list of CMU_TOP side */
 377
 378 struct clk *exynos4_clkset_aclk_top_list[] = {
 379         [0] = &exynos4_clk_mout_mpll.clk,
 380         [1] = &exynos4_clk_sclk_apll.clk,
 381 };
 382
 383 static struct clksrc_sources exynos4_clkset_aclk = {
 384         .sources        = exynos4_clkset_aclk_top_list,
 385         .nr_sources     = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
 386 };
 387
 388 static struct clksrc_clk exynos4_clk_aclk_200 = {
 389         .clk    = {
 390                 .name           = "aclk_200",
 391         },
 392         .sources = &exynos4_clkset_aclk,
 393         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
 394         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
 395 };
 396
 397 static struct clksrc_clk exynos4_clk_aclk_100 = {
 398         .clk    = {
 399                 .name           = "aclk_100",
 400         },
 401         .sources = &exynos4_clkset_aclk,
 402         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
 403         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
 404 };
 405
 406 static struct clksrc_clk exynos4_clk_aclk_160 = {
 407         .clk    = {
 408                 .name           = "aclk_160",
 409         },
 410         .sources = &exynos4_clkset_aclk,
 411         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
 412         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
 413 };
 414
 415 struct clksrc_clk exynos4_clk_aclk_133 = {
 416         .clk    = {
 417                 .name           = "aclk_133",
 418         },
 419         .sources = &exynos4_clkset_aclk,
 420         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
 421         .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
 422 };
 423
 424 static struct clk *exynos4_clkset_vpllsrc_list[] = {
 425         [0] = &clk_fin_vpll,
 426         [1] = &exynos4_clk_sclk_hdmi27m,
 427 };
 428
 429 static struct clksrc_sources exynos4_clkset_vpllsrc = {
 430         .sources        = exynos4_clkset_vpllsrc_list,
 431         .nr_sources     = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
 432 };
 433
 434 static struct clksrc_clk exynos4_clk_vpllsrc = {
 435         .clk    = {
 436                 .name           = "vpll_src",
 437                 .enable         = exynos4_clksrc_mask_top_ctrl,
 438                 .ctrlbit        = (1 << 0),
 439         },
 440         .sources = &exynos4_clkset_vpllsrc,
 441         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
 442 };
 443
 444 static struct clk *exynos4_clkset_sclk_vpll_list[] = {
 445         [0] = &exynos4_clk_vpllsrc.clk,
 446         [1] = &clk_fout_vpll,
 447 };
 448
 449 static struct clksrc_sources exynos4_clkset_sclk_vpll = {
 450         .sources        = exynos4_clkset_sclk_vpll_list,
 451         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
 452 };
 453
 454 static struct clksrc_clk exynos4_clk_sclk_vpll = {
 455         .clk    = {
 456                 .name           = "sclk_vpll",
 457         },
 458         .sources = &exynos4_clkset_sclk_vpll,
 459         .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
 460 };
 461
 462 static struct clk exynos4_init_clocks_off[] = {
 463         {
 464                 .name           = "timers",
 465                 .parent         = &exynos4_clk_aclk_100.clk,
 466                 .enable         = exynos4_clk_ip_peril_ctrl,
 467                 .ctrlbit        = (1<<24),
 468         }, {
 469                 .name           = "csis",
 470                 .devname        = "s5p-mipi-csis.0",
 471                 .enable         = exynos4_clk_ip_cam_ctrl,
 472                 .ctrlbit        = (1 << 4),
 473         }, {
 474                 .name           = "csis",
 475                 .devname        = "s5p-mipi-csis.1",
 476                 .enable         = exynos4_clk_ip_cam_ctrl,
 477                 .ctrlbit        = (1 << 5),
 478         }, {
 479                 .name           = "jpeg",
 480                 .id             = 0,
 481                 .enable         = exynos4_clk_ip_cam_ctrl,
 482                 .ctrlbit        = (1 << 6),
 483         }, {
 484                 .name           = "fimc",
 485                 .devname        = "exynos4-fimc.0",
 486                 .enable         = exynos4_clk_ip_cam_ctrl,
 487                 .ctrlbit        = (1 << 0),
 488         }, {
 489                 .name           = "fimc",
 490                 .devname        = "exynos4-fimc.1",
 491                 .enable         = exynos4_clk_ip_cam_ctrl,
 492                 .ctrlbit        = (1 << 1),
 493         }, {
 494                 .name           = "fimc",
 495                 .devname        = "exynos4-fimc.2",
 496                 .enable         = exynos4_clk_ip_cam_ctrl,
 497                 .ctrlbit        = (1 << 2),
 498         }, {
 499                 .name           = "fimc",
 500                 .devname        = "exynos4-fimc.3",
 501                 .enable         = exynos4_clk_ip_cam_ctrl,
 502                 .ctrlbit        = (1 << 3),
 503         }, {
 504                 .name           = "hsmmc",
 505                 .devname        = "exynos4-sdhci.0",
 506                 .parent         = &exynos4_clk_aclk_133.clk,
 507                 .enable         = exynos4_clk_ip_fsys_ctrl,
 508                 .ctrlbit        = (1 << 5),
 509         }, {
 510                 .name           = "hsmmc",
 511                 .devname        = "exynos4-sdhci.1",
 512                 .parent         = &exynos4_clk_aclk_133.clk,
 513                 .enable         = exynos4_clk_ip_fsys_ctrl,
 514                 .ctrlbit        = (1 << 6),
 515         }, {
 516                 .name           = "hsmmc",
 517                 .devname        = "exynos4-sdhci.2",
 518                 .parent         = &exynos4_clk_aclk_133.clk,
 519                 .enable         = exynos4_clk_ip_fsys_ctrl,
 520                 .ctrlbit        = (1 << 7),
 521         }, {
 522                 .name           = "hsmmc",
 523                 .devname        = "exynos4-sdhci.3",
 524                 .parent         = &exynos4_clk_aclk_133.clk,
 525                 .enable         = exynos4_clk_ip_fsys_ctrl,
 526                 .ctrlbit        = (1 << 8),
 527         }, {
 528                 .name           = "dwmmc",
 529                 .parent         = &exynos4_clk_aclk_133.clk,
 530                 .enable         = exynos4_clk_ip_fsys_ctrl,
 531                 .ctrlbit        = (1 << 9),
 532         }, {
 533                 .name           = "dac",
 534                 .devname        = "s5p-sdo",
 535                 .enable         = exynos4_clk_ip_tv_ctrl,
 536                 .ctrlbit        = (1 << 2),
 537         }, {
 538                 .name           = "mixer",
 539                 .devname        = "s5p-mixer",
 540                 .enable         = exynos4_clk_ip_tv_ctrl,
 541                 .ctrlbit        = (1 << 1),
 542         }, {
 543                 .name           = "vp",
 544                 .devname        = "s5p-mixer",
 545                 .enable         = exynos4_clk_ip_tv_ctrl,
 546                 .ctrlbit        = (1 << 0),
 547         }, {
 548                 .name           = "hdmi",
 549                 .devname        = "exynos4-hdmi",
 550                 .enable         = exynos4_clk_ip_tv_ctrl,
 551                 .ctrlbit        = (1 << 3),
 552         }, {
 553                 .name           = "hdmiphy",
 554                 .devname        = "exynos4-hdmi",
 555                 .enable         = exynos4_clk_hdmiphy_ctrl,
 556                 .ctrlbit        = (1 << 0),
 557         }, {
 558                 .name           = "dacphy",
 559                 .devname        = "s5p-sdo",
 560                 .enable         = exynos4_clk_dac_ctrl,
 561                 .ctrlbit        = (1 << 0),
 562         }, {
 563                 .name           = "adc",
 564                 .enable         = exynos4_clk_ip_peril_ctrl,
 565                 .ctrlbit        = (1 << 15),
 566         }, {
 567                 .name           = "keypad",
 568                 .enable         = exynos4_clk_ip_perir_ctrl,
 569                 .ctrlbit        = (1 << 16),
 570         }, {
 571                 .name           = "rtc",
 572                 .enable         = exynos4_clk_ip_perir_ctrl,
 573                 .ctrlbit        = (1 << 15),
 574         }, {
 575                 .name           = "watchdog",
 576                 .parent         = &exynos4_clk_aclk_100.clk,
 577                 .enable         = exynos4_clk_ip_perir_ctrl,
 578                 .ctrlbit        = (1 << 14),
 579         }, {
 580                 .name           = "usbhost",
 581                 .enable         = exynos4_clk_ip_fsys_ctrl ,
 582                 .ctrlbit        = (1 << 12),
 583         }, {
 584                 .name           = "otg",
 585                 .enable         = exynos4_clk_ip_fsys_ctrl,
 586                 .ctrlbit        = (1 << 13),
 587         }, {
 588                 .name           = "spi",
 589                 .devname        = "s3c64xx-spi.0",
 590                 .enable         = exynos4_clk_ip_peril_ctrl,
 591                 .ctrlbit        = (1 << 16),
 592         }, {
 593                 .name           = "spi",
 594                 .devname        = "s3c64xx-spi.1",
 595                 .enable         = exynos4_clk_ip_peril_ctrl,
 596                 .ctrlbit        = (1 << 17),
 597         }, {
 598                 .name           = "spi",
 599                 .devname        = "s3c64xx-spi.2",
 600                 .enable         = exynos4_clk_ip_peril_ctrl,
 601                 .ctrlbit        = (1 << 18),
 602         }, {
 603                 .name           = "iis",
 604                 .devname        = "samsung-i2s.0",
 605                 .enable         = exynos4_clk_ip_peril_ctrl,
 606                 .ctrlbit        = (1 << 19),
 607         }, {
 608                 .name           = "iis",
 609                 .devname        = "samsung-i2s.1",
 610                 .enable         = exynos4_clk_ip_peril_ctrl,
 611                 .ctrlbit        = (1 << 20),
 612         }, {
 613                 .name           = "iis",
 614                 .devname        = "samsung-i2s.2",
 615                 .enable         = exynos4_clk_ip_peril_ctrl,
 616                 .ctrlbit        = (1 << 21),
 617         }, {
 618                 .name           = "ac97",
 619                 .devname        = "samsung-ac97",
 620                 .enable         = exynos4_clk_ip_peril_ctrl,
 621                 .ctrlbit        = (1 << 27),
 622         }, {
 623                 .name           = "fimg2d",
 624                 .enable         = exynos4_clk_ip_image_ctrl,
 625                 .ctrlbit        = (1 << 0),
 626         }, {
 627                 .name           = "mfc",
 628                 .devname        = "s5p-mfc",
 629                 .enable         = exynos4_clk_ip_mfc_ctrl,
 630                 .ctrlbit        = (1 << 0),
 631         }, {
 632                 .name           = "i2c",
 633                 .devname        = "s3c2440-i2c.0",
 634                 .parent         = &exynos4_clk_aclk_100.clk,
 635                 .enable         = exynos4_clk_ip_peril_ctrl,
 636                 .ctrlbit        = (1 << 6),
 637         }, {
 638                 .name           = "i2c",
 639                 .devname        = "s3c2440-i2c.1",
 640                 .parent         = &exynos4_clk_aclk_100.clk,
 641                 .enable         = exynos4_clk_ip_peril_ctrl,
 642                 .ctrlbit        = (1 << 7),
 643         }, {
 644                 .name           = "i2c",
 645                 .devname        = "s3c2440-i2c.2",
 646                 .parent         = &exynos4_clk_aclk_100.clk,
 647                 .enable         = exynos4_clk_ip_peril_ctrl,
 648                 .ctrlbit        = (1 << 8),
 649         }, {
 650                 .name           = "i2c",
 651                 .devname        = "s3c2440-i2c.3",
 652                 .parent         = &exynos4_clk_aclk_100.clk,
 653                 .enable         = exynos4_clk_ip_peril_ctrl,
 654                 .ctrlbit        = (1 << 9),
 655         }, {
 656                 .name           = "i2c",
 657                 .devname        = "s3c2440-i2c.4",
 658                 .parent         = &exynos4_clk_aclk_100.clk,
 659                 .enable         = exynos4_clk_ip_peril_ctrl,
 660                 .ctrlbit        = (1 << 10),
 661         }, {
 662                 .name           = "i2c",
 663                 .devname        = "s3c2440-i2c.5",
 664                 .parent         = &exynos4_clk_aclk_100.clk,
 665                 .enable         = exynos4_clk_ip_peril_ctrl,
 666                 .ctrlbit        = (1 << 11),
 667         }, {
 668                 .name           = "i2c",
 669                 .devname        = "s3c2440-i2c.6",
 670                 .parent         = &exynos4_clk_aclk_100.clk,
 671                 .enable         = exynos4_clk_ip_peril_ctrl,
 672                 .ctrlbit        = (1 << 12),
 673         }, {
 674                 .name           = "i2c",
 675                 .devname        = "s3c2440-i2c.7",
 676                 .parent         = &exynos4_clk_aclk_100.clk,
 677                 .enable         = exynos4_clk_ip_peril_ctrl,
 678                 .ctrlbit        = (1 << 13),
 679         }, {
 680                 .name           = "i2c",
 681                 .devname        = "s3c2440-hdmiphy-i2c",
 682                 .parent         = &exynos4_clk_aclk_100.clk,
 683                 .enable         = exynos4_clk_ip_peril_ctrl,
 684                 .ctrlbit        = (1 << 14),
 685         }, {
 686                 .name           = SYSMMU_CLOCK_NAME,
 687                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
 688                 .enable         = exynos4_clk_ip_mfc_ctrl,
 689                 .ctrlbit        = (1 << 1),
 690         }, {
 691                 .name           = SYSMMU_CLOCK_NAME,
 692                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
 693                 .enable         = exynos4_clk_ip_mfc_ctrl,
 694                 .ctrlbit        = (1 << 2),
 695         }, {
 696                 .name           = SYSMMU_CLOCK_NAME,
 697                 .devname        = SYSMMU_CLOCK_DEVNAME(tv, 2),
 698                 .enable         = exynos4_clk_ip_tv_ctrl,
 699                 .ctrlbit        = (1 << 4),
 700         }, {
 701                 .name           = SYSMMU_CLOCK_NAME,
 702                 .devname        = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
 703                 .enable         = exynos4_clk_ip_cam_ctrl,
 704                 .ctrlbit        = (1 << 11),
 705         }, {
 706                 .name           = SYSMMU_CLOCK_NAME,
 707                 .devname        = SYSMMU_CLOCK_DEVNAME(rot, 4),
 708                 .enable         = exynos4_clk_ip_image_ctrl,
 709                 .ctrlbit        = (1 << 4),
 710         }, {
 711                 .name           = SYSMMU_CLOCK_NAME,
 712                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
 713                 .enable         = exynos4_clk_ip_cam_ctrl,
 714                 .ctrlbit        = (1 << 7),
 715         }, {
 716                 .name           = SYSMMU_CLOCK_NAME,
 717                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
 718                 .enable         = exynos4_clk_ip_cam_ctrl,
 719                 .ctrlbit        = (1 << 8),
 720         }, {
 721                 .name           = SYSMMU_CLOCK_NAME,
 722                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
 723                 .enable         = exynos4_clk_ip_cam_ctrl,
 724                 .ctrlbit        = (1 << 9),
 725         }, {
 726                 .name           = SYSMMU_CLOCK_NAME,
 727                 .devname        = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
 728                 .enable         = exynos4_clk_ip_cam_ctrl,
 729                 .ctrlbit        = (1 << 10),
 730         }, {
 731                 .name           = SYSMMU_CLOCK_NAME,
 732                 .devname        = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
 733                 .enable         = exynos4_clk_ip_lcd0_ctrl,
 734                 .ctrlbit        = (1 << 4),
 735         }
 736 };
 737
 738 static struct clk exynos4_init_clocks_on[] = {
 739         {
 740                 .name           = "uart",
 741                 .devname        = "s5pv210-uart.0",
 742                 .enable         = exynos4_clk_ip_peril_ctrl,
 743                 .ctrlbit        = (1 << 0),
 744         }, {
 745                 .name           = "uart",
 746                 .devname        = "s5pv210-uart.1",
 747                 .enable         = exynos4_clk_ip_peril_ctrl,
 748                 .ctrlbit        = (1 << 1),
 749         }, {
 750                 .name           = "uart",
 751                 .devname        = "s5pv210-uart.2",
 752                 .enable         = exynos4_clk_ip_peril_ctrl,
 753                 .ctrlbit        = (1 << 2),
 754         }, {
 755                 .name           = "uart",
 756                 .devname        = "s5pv210-uart.3",
 757                 .enable         = exynos4_clk_ip_peril_ctrl,
 758                 .ctrlbit        = (1 << 3),
 759         }, {
 760                 .name           = "uart",
 761                 .devname        = "s5pv210-uart.4",
 762                 .enable         = exynos4_clk_ip_peril_ctrl,
 763                 .ctrlbit        = (1 << 4),
 764         }, {
 765                 .name           = "uart",
 766                 .devname        = "s5pv210-uart.5",
 767                 .enable         = exynos4_clk_ip_peril_ctrl,
 768                 .ctrlbit        = (1 << 5),
 769         }
 770 };
 771
 772 static struct clk exynos4_clk_pdma0 = {
 773         .name           = "dma",
 774         .devname        = "dma-pl330.0",
 775         .enable         = exynos4_clk_ip_fsys_ctrl,
 776         .ctrlbit        = (1 << 0),
 777 };
 778
 779 static struct clk exynos4_clk_pdma1 = {
 780         .name           = "dma",
 781         .devname        = "dma-pl330.1",
 782         .enable         = exynos4_clk_ip_fsys_ctrl,
 783         .ctrlbit        = (1 << 1),
 784 };
 785
 786 static struct clk exynos4_clk_mdma1 = {
 787         .name           = "dma",
 788         .devname        = "dma-pl330.2",
 789         .enable         = exynos4_clk_ip_image_ctrl,
 790         .ctrlbit        = ((1 << 8) | (1 << 5) | (1 << 2)),
 791 };
 792
 793 static struct clk exynos4_clk_fimd0 = {
 794         .name           = "fimd",
 795         .devname        = "exynos4-fb.0",
 796         .enable         = exynos4_clk_ip_lcd0_ctrl,
 797         .ctrlbit        = (1 << 0),
 798 };
 799
 800 struct clk *exynos4_clkset_group_list[] = {
 801         [0] = &clk_ext_xtal_mux,
 802         [1] = &clk_xusbxti,
 803         [2] = &exynos4_clk_sclk_hdmi27m,
 804         [3] = &exynos4_clk_sclk_usbphy0,
 805         [4] = &exynos4_clk_sclk_usbphy1,
 806         [5] = &exynos4_clk_sclk_hdmiphy,
 807         [6] = &exynos4_clk_mout_mpll.clk,
 808         [7] = &exynos4_clk_mout_epll.clk,
 809         [8] = &exynos4_clk_sclk_vpll.clk,
 810 };
 811
 812 struct clksrc_sources exynos4_clkset_group = {
 813         .sources        = exynos4_clkset_group_list,
 814         .nr_sources     = ARRAY_SIZE(exynos4_clkset_group_list),
 815 };
 816
 817 static struct clk *exynos4_clkset_mout_g2d0_list[] = {
 818         [0] = &exynos4_clk_mout_mpll.clk,
 819         [1] = &exynos4_clk_sclk_apll.clk,
 820 };
 821
 822 static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
 823         .sources        = exynos4_clkset_mout_g2d0_list,
 824         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
 825 };
 826
 827 static struct clksrc_clk exynos4_clk_mout_g2d0 = {
 828         .clk    = {
 829                 .name           = "mout_g2d0",
 830         },
 831         .sources = &exynos4_clkset_mout_g2d0,
 832         .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
 833 };
 834
 835 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
 836         [0] = &exynos4_clk_mout_epll.clk,
 837         [1] = &exynos4_clk_sclk_vpll.clk,
 838 };
 839
 840 static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
 841         .sources        = exynos4_clkset_mout_g2d1_list,
 842         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
 843 };
 844
 845 static struct clksrc_clk exynos4_clk_mout_g2d1 = {
 846         .clk    = {
 847                 .name           = "mout_g2d1",
 848         },
 849         .sources = &exynos4_clkset_mout_g2d1,
 850         .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
 851 };
 852
 853 static struct clk *exynos4_clkset_mout_g2d_list[] = {
 854         [0] = &exynos4_clk_mout_g2d0.clk,
 855         [1] = &exynos4_clk_mout_g2d1.clk,
 856 };
 857
 858 static struct clksrc_sources exynos4_clkset_mout_g2d = {
 859         .sources        = exynos4_clkset_mout_g2d_list,
 860         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
 861 };
 862
 863 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
 864         [0] = &exynos4_clk_mout_mpll.clk,
 865         [1] = &exynos4_clk_sclk_apll.clk,
 866 };
 867
 868 static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
 869         .sources        = exynos4_clkset_mout_mfc0_list,
 870         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
 871 };
 872
 873 static struct clksrc_clk exynos4_clk_mout_mfc0 = {
 874         .clk    = {
 875                 .name           = "mout_mfc0",
 876         },
 877         .sources = &exynos4_clkset_mout_mfc0,
 878         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
 879 };
 880
 881 static struct clk *exynos4_clkset_mout_mfc1_list[] = {
 882         [0] = &exynos4_clk_mout_epll.clk,
 883         [1] = &exynos4_clk_sclk_vpll.clk,
 884 };
 885
 886 static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
 887         .sources        = exynos4_clkset_mout_mfc1_list,
 888         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
 889 };
 890
 891 static struct clksrc_clk exynos4_clk_mout_mfc1 = {
 892         .clk    = {
 893                 .name           = "mout_mfc1",
 894         },
 895         .sources = &exynos4_clkset_mout_mfc1,
 896         .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
 897 };
 898
 899 static struct clk *exynos4_clkset_mout_mfc_list[] = {
 900         [0] = &exynos4_clk_mout_mfc0.clk,
 901         [1] = &exynos4_clk_mout_mfc1.clk,
 902 };
 903
 904 static struct clksrc_sources exynos4_clkset_mout_mfc = {
 905         .sources        = exynos4_clkset_mout_mfc_list,
 906         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
 907 };
 908
 909 static struct clk *exynos4_clkset_sclk_dac_list[] = {
 910         [0] = &exynos4_clk_sclk_vpll.clk,
 911         [1] = &exynos4_clk_sclk_hdmiphy,
 912 };
 913
 914 static struct clksrc_sources exynos4_clkset_sclk_dac = {
 915         .sources        = exynos4_clkset_sclk_dac_list,
 916         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
 917 };
 918
 919 static struct clksrc_clk exynos4_clk_sclk_dac = {
 920         .clk            = {
 921                 .name           = "sclk_dac",
 922                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 923                 .ctrlbit        = (1 << 8),
 924         },
 925         .sources = &exynos4_clkset_sclk_dac,
 926         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
 927 };
 928
 929 static struct clksrc_clk exynos4_clk_sclk_pixel = {
 930         .clk            = {
 931                 .name           = "sclk_pixel",
 932                 .parent         = &exynos4_clk_sclk_vpll.clk,
 933         },
 934         .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
 935 };
 936
 937 static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
 938         [0] = &exynos4_clk_sclk_pixel.clk,
 939         [1] = &exynos4_clk_sclk_hdmiphy,
 940 };
 941
 942 static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
 943         .sources        = exynos4_clkset_sclk_hdmi_list,
 944         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
 945 };
 946
 947 static struct clksrc_clk exynos4_clk_sclk_hdmi = {
 948         .clk            = {
 949                 .name           = "sclk_hdmi",
 950                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 951                 .ctrlbit        = (1 << 0),
 952         },
 953         .sources = &exynos4_clkset_sclk_hdmi,
 954         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
 955 };
 956
 957 static struct clk *exynos4_clkset_sclk_mixer_list[] = {
 958         [0] = &exynos4_clk_sclk_dac.clk,
 959         [1] = &exynos4_clk_sclk_hdmi.clk,
 960 };
 961
 962 static struct clksrc_sources exynos4_clkset_sclk_mixer = {
 963         .sources        = exynos4_clkset_sclk_mixer_list,
 964         .nr_sources     = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
 965 };
 966
 967 static struct clksrc_clk exynos4_clk_sclk_mixer = {
 968         .clk    = {
 969                 .name           = "sclk_mixer",
 970                 .enable         = exynos4_clksrc_mask_tv_ctrl,
 971                 .ctrlbit        = (1 << 4),
 972         },
 973         .sources = &exynos4_clkset_sclk_mixer,
 974         .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
 975 };
 976
 977 static struct clksrc_clk *exynos4_sclk_tv[] = {
 978         &exynos4_clk_sclk_dac,
 979         &exynos4_clk_sclk_pixel,
 980         &exynos4_clk_sclk_hdmi,
 981         &exynos4_clk_sclk_mixer,
 982 };
 983
 984 static struct clksrc_clk exynos4_clk_dout_mmc0 = {
 985         .clk    = {
 986                 .name           = "dout_mmc0",
 987         },
 988         .sources = &exynos4_clkset_group,
 989         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
 990         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
 991 };
 992
 993 static struct clksrc_clk exynos4_clk_dout_mmc1 = {
 994         .clk    = {
 995                 .name           = "dout_mmc1",
 996         },
 997         .sources = &exynos4_clkset_group,
 998         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
 999         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
1000 };
1001
1002 static struct clksrc_clk exynos4_clk_dout_mmc2 = {
1003         .clk    = {
1004                 .name           = "dout_mmc2",
1005         },
1006         .sources = &exynos4_clkset_group,
1007         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
1008         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
1009 };
1010
1011 static struct clksrc_clk exynos4_clk_dout_mmc3 = {
1012         .clk    = {
1013                 .name           = "dout_mmc3",
1014         },
1015         .sources = &exynos4_clkset_group,
1016         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
1017         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1018 };
1019
1020 static struct clksrc_clk exynos4_clk_dout_mmc4 = {
1021         .clk            = {
1022                 .name           = "dout_mmc4",
1023         },
1024         .sources = &exynos4_clkset_group,
1025         .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
1026         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1027 };
1028
1029 static struct clksrc_clk exynos4_clksrcs[] = {
1030         {
1031                 .clk    = {
1032                         .name           = "sclk_pwm",
1033                         .enable         = exynos4_clksrc_mask_peril0_ctrl,
1034                         .ctrlbit        = (1 << 24),
1035                 },
1036                 .sources = &exynos4_clkset_group,
1037                 .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1038                 .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1039         }, {
1040                 .clk    = {
1041                         .name           = "sclk_csis",
1042                         .devname        = "s5p-mipi-csis.0",
1043                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1044                         .ctrlbit        = (1 << 24),
1045                 },
1046                 .sources = &exynos4_clkset_group,
1047                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
1048                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
1049         }, {
1050                 .clk    = {
1051                         .name           = "sclk_csis",
1052                         .devname        = "s5p-mipi-csis.1",
1053                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1054                         .ctrlbit        = (1 << 28),
1055                 },
1056                 .sources = &exynos4_clkset_group,
1057                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
1058                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
1059         }, {
1060                 .clk    = {
1061                         .name           = "sclk_cam0",
1062                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1063                         .ctrlbit        = (1 << 16),
1064                 },
1065                 .sources = &exynos4_clkset_group,
1066                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
1067                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
1068         }, {
1069                 .clk    = {
1070                         .name           = "sclk_cam1",
1071                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1072                         .ctrlbit        = (1 << 20),
1073                 },
1074                 .sources = &exynos4_clkset_group,
1075                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
1076                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
1077         }, {
1078                 .clk    = {
1079                         .name           = "sclk_fimc",
1080                         .devname        = "exynos4-fimc.0",
1081                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1082                         .ctrlbit        = (1 << 0),
1083                 },
1084                 .sources = &exynos4_clkset_group,
1085                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
1086                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
1087         }, {
1088                 .clk    = {
1089                         .name           = "sclk_fimc",
1090                         .devname        = "exynos4-fimc.1",
1091                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1092                         .ctrlbit        = (1 << 4),
1093                 },
1094                 .sources = &exynos4_clkset_group,
1095                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
1096                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
1097         }, {
1098                 .clk    = {
1099                         .name           = "sclk_fimc",
1100                         .devname        = "exynos4-fimc.2",
1101                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1102                         .ctrlbit        = (1 << 8),
1103                 },
1104                 .sources = &exynos4_clkset_group,
1105                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
1106                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
1107         }, {
1108                 .clk    = {
1109                         .name           = "sclk_fimc",
1110                         .devname        = "exynos4-fimc.3",
1111                         .enable         = exynos4_clksrc_mask_cam_ctrl,
1112                         .ctrlbit        = (1 << 12),
1113                 },
1114                 .sources = &exynos4_clkset_group,
1115                 .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
1116                 .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
1117         }, {
1118                 .clk    = {
1119                         .name           = "sclk_fimd",
1120                         .devname        = "exynos4-fb.0",
1121                         .enable         = exynos4_clksrc_mask_lcd0_ctrl,
1122                         .ctrlbit        = (1 << 0),
1123                 },
1124                 .sources = &exynos4_clkset_group,
1125                 .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
1126                 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
1127         }, {
1128                 .clk    = {
1129                         .name           = "sclk_fimg2d",
1130                 },
1131                 .sources = &exynos4_clkset_mout_g2d,
1132                 .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1133                 .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1134         }, {
1135                 .clk    = {
1136                         .name           = "sclk_mfc",
1137                         .devname        = "s5p-mfc",
1138                 },
1139                 .sources = &exynos4_clkset_mout_mfc,
1140                 .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
1141                 .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
1142         }, {
1143                 .clk    = {
1144                         .name           = "sclk_dwmmc",
1145                         .parent         = &exynos4_clk_dout_mmc4.clk,
1146                         .enable         = exynos4_clksrc_mask_fsys_ctrl,
1147                         .ctrlbit        = (1 << 16),
1148                 },
1149                 .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1150         }
1151 };
1152
1153 static struct clksrc_clk exynos4_clk_sclk_uart0 = {
1154         .clk    = {
1155                 .name           = "uclk1",
1156                 .devname        = "exynos4210-uart.0",
1157                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1158                 .ctrlbit        = (1 << 0),
1159         },
1160         .sources = &exynos4_clkset_group,
1161         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1162         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1163 };
1164
1165 static struct clksrc_clk exynos4_clk_sclk_uart1 = {
1166         .clk    = {
1167                 .name           = "uclk1",
1168                 .devname        = "exynos4210-uart.1",
1169                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1170                 .ctrlbit        = (1 << 4),
1171         },
1172         .sources = &exynos4_clkset_group,
1173         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1174         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1175 };
1176
1177 static struct clksrc_clk exynos4_clk_sclk_uart2 = {
1178         .clk    = {
1179                 .name           = "uclk1",
1180                 .devname        = "exynos4210-uart.2",
1181                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1182                 .ctrlbit        = (1 << 8),
1183         },
1184         .sources = &exynos4_clkset_group,
1185         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1186         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1187 };
1188
1189 static struct clksrc_clk exynos4_clk_sclk_uart3 = {
1190         .clk    = {
1191                 .name           = "uclk1",
1192                 .devname        = "exynos4210-uart.3",
1193                 .enable         = exynos4_clksrc_mask_peril0_ctrl,
1194                 .ctrlbit        = (1 << 12),
1195         },
1196         .sources = &exynos4_clkset_group,
1197         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1198         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1199 };
1200
1201 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
1202         .clk    = {
1203                 .name           = "sclk_mmc",
1204                 .devname        = "exynos4-sdhci.0",
1205                 .parent         = &exynos4_clk_dout_mmc0.clk,
1206                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1207                 .ctrlbit        = (1 << 0),
1208         },
1209         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1210 };
1211
1212 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
1213         .clk    = {
1214                 .name           = "sclk_mmc",
1215                 .devname        = "exynos4-sdhci.1",
1216                 .parent         = &exynos4_clk_dout_mmc1.clk,
1217                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1218                 .ctrlbit        = (1 << 4),
1219         },
1220         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1221 };
1222
1223 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
1224         .clk    = {
1225                 .name           = "sclk_mmc",
1226                 .devname        = "exynos4-sdhci.2",
1227                 .parent         = &exynos4_clk_dout_mmc2.clk,
1228                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1229                 .ctrlbit        = (1 << 8),
1230         },
1231         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1232 };
1233
1234 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
1235         .clk    = {
1236                 .name           = "sclk_mmc",
1237                 .devname        = "exynos4-sdhci.3",
1238                 .parent         = &exynos4_clk_dout_mmc3.clk,
1239                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
1240                 .ctrlbit        = (1 << 12),
1241         },
1242         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1243 };
1244
1245 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
1246         .clk    = {
1247                 .name           = "sclk_spi",
1248                 .devname        = "s3c64xx-spi.0",
1249                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1250                 .ctrlbit        = (1 << 16),
1251         },
1252         .sources = &exynos4_clkset_group,
1253         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1254         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1255 };
1256
1257 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
1258         .clk    = {
1259                 .name           = "sclk_spi",
1260                 .devname        = "s3c64xx-spi.1",
1261                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1262                 .ctrlbit        = (1 << 20),
1263         },
1264         .sources = &exynos4_clkset_group,
1265         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1266         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1267 };
1268
1269 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
1270         .clk    = {
1271                 .name           = "sclk_spi",
1272                 .devname        = "s3c64xx-spi.2",
1273                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
1274                 .ctrlbit        = (1 << 24),
1275         },
1276         .sources = &exynos4_clkset_group,
1277         .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1278         .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1279 };
1280
1281 /* Clock initialization code */
1282 static struct clksrc_clk *exynos4_sysclks[] = {
1283         &exynos4_clk_mout_apll,
1284         &exynos4_clk_sclk_apll,
1285         &exynos4_clk_mout_epll,
1286         &exynos4_clk_mout_mpll,
1287         &exynos4_clk_moutcore,
1288         &exynos4_clk_coreclk,
1289         &exynos4_clk_armclk,
1290         &exynos4_clk_aclk_corem0,
1291         &exynos4_clk_aclk_cores,
1292         &exynos4_clk_aclk_corem1,
1293         &exynos4_clk_periphclk,
1294         &exynos4_clk_mout_corebus,
1295         &exynos4_clk_sclk_dmc,
1296         &exynos4_clk_aclk_cored,
1297         &exynos4_clk_aclk_corep,
1298         &exynos4_clk_aclk_acp,
1299         &exynos4_clk_pclk_acp,
1300         &exynos4_clk_vpllsrc,
1301         &exynos4_clk_sclk_vpll,
1302         &exynos4_clk_aclk_200,
1303         &exynos4_clk_aclk_100,
1304         &exynos4_clk_aclk_160,
1305         &exynos4_clk_aclk_133,
1306         &exynos4_clk_dout_mmc0,
1307         &exynos4_clk_dout_mmc1,
1308         &exynos4_clk_dout_mmc2,
1309         &exynos4_clk_dout_mmc3,
1310         &exynos4_clk_dout_mmc4,
1311         &exynos4_clk_mout_mfc0,
1312         &exynos4_clk_mout_mfc1,
1313 };
1314
1315 static struct clk *exynos4_clk_cdev[] = {
1316         &exynos4_clk_pdma0,
1317         &exynos4_clk_pdma1,
1318         &exynos4_clk_mdma1,
1319         &exynos4_clk_fimd0,
1320 };
1321
1322 static struct clksrc_clk *exynos4_clksrc_cdev[] = {
1323         &exynos4_clk_sclk_uart0,
1324         &exynos4_clk_sclk_uart1,
1325         &exynos4_clk_sclk_uart2,
1326         &exynos4_clk_sclk_uart3,
1327         &exynos4_clk_sclk_mmc0,
1328         &exynos4_clk_sclk_mmc1,
1329         &exynos4_clk_sclk_mmc2,
1330         &exynos4_clk_sclk_mmc3,
1331         &exynos4_clk_sclk_spi0,
1332         &exynos4_clk_sclk_spi1,
1333         &exynos4_clk_sclk_spi2,
1334
1335 };
1336
1337 static struct clk_lookup exynos4_clk_lookup[] = {
1338         CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
1339         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
1340         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
1341         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
1342         CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
1343         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
1344         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
1345         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
1346         CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
1347         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
1348         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
1349         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
1350         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
1351         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
1352         CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
1353 };
1354
1355 static int xtal_rate;
1356
1357 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1358 {
1359         if (soc_is_exynos4210())
1360                 return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
1361                                         pll_4508);
1362         else if (soc_is_exynos4212() || soc_is_exynos4412())
1363                 return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
1364         else
1365                 return 0;
1366 }
1367
1368 static struct clk_ops exynos4_fout_apll_ops = {
1369         .get_rate = exynos4_fout_apll_get_rate,
1370 };
1371
1372 static u32 exynos4_vpll_div[][8] = {
1373         {  54000000, 3, 53, 3, 1024, 0, 17, 0 },
1374         { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1375 };
1376
1377 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1378 {
1379         return clk->rate;
1380 }
1381
1382 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1383 {
1384         unsigned int vpll_con0, vpll_con1 = 0;
1385         unsigned int i;
1386
1387         /* Return if nothing changed */
1388         if (clk->rate == rate)
1389                 return 0;
1390
1391         vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
1392         vpll_con0 &= ~(0x1 << 27 |                                      \
1393                         PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |       \
1394                         PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |       \
1395                         PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1396
1397         vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
1398         vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT |  \
1399                         PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1400                         PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1401
1402         for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
1403                 if (exynos4_vpll_div[i][0] == rate) {
1404                         vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1405                         vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1406                         vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1407                         vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1408                         vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1409                         vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1410                         vpll_con0 |= exynos4_vpll_div[i][7] << 27;
1411                         break;
1412                 }
1413         }
1414
1415         if (i == ARRAY_SIZE(exynos4_vpll_div)) {
1416                 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1417                                 __func__);
1418                 return -EINVAL;
1419         }
1420
1421         __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
1422         __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
1423
1424         /* Wait for VPLL lock */
1425         while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1426                 continue;
1427
1428         clk->rate = rate;
1429         return 0;
1430 }
1431
1432 static struct clk_ops exynos4_vpll_ops = {
1433         .get_rate = exynos4_vpll_get_rate,
1434         .set_rate = exynos4_vpll_set_rate,
1435 };
1436
1437 void __init_or_cpufreq exynos4_setup_clocks(void)
1438 {
1439         struct clk *xtal_clk;
1440         unsigned long apll = 0;
1441         unsigned long mpll = 0;
1442         unsigned long epll = 0;
1443         unsigned long vpll = 0;
1444         unsigned long vpllsrc;
1445         unsigned long xtal;
1446         unsigned long armclk;
1447         unsigned long sclk_dmc;
1448         unsigned long aclk_200;
1449         unsigned long aclk_100;
1450         unsigned long aclk_160;
1451         unsigned long aclk_133;
1452         unsigned int ptr;
1453
1454         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1455
1456         xtal_clk = clk_get(NULL, "xtal");
1457         BUG_ON(IS_ERR(xtal_clk));
1458
1459         xtal = clk_get_rate(xtal_clk);
1460
1461         xtal_rate = xtal;
1462
1463         clk_put(xtal_clk);
1464
1465         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1466
1467         if (soc_is_exynos4210()) {
1468                 apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
1469                                         pll_4508);
1470                 mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
1471                                         pll_4508);
1472                 epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1473                                         __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
1474
1475                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1476                 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1477                                         __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
1478         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1479                 apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
1480                 mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
1481                 epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
1482                                         __raw_readl(EXYNOS4_EPLL_CON1));
1483
1484                 vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
1485                 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
1486                                         __raw_readl(EXYNOS4_VPLL_CON1));
1487         } else {
1488                 /* nothing */
1489         }
1490
1491         clk_fout_apll.ops = &exynos4_fout_apll_ops;
1492         clk_fout_mpll.rate = mpll;
1493         clk_fout_epll.rate = epll;
1494         clk_fout_vpll.ops = &exynos4_vpll_ops;
1495         clk_fout_vpll.rate = vpll;
1496
1497         printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1498                         apll, mpll, epll, vpll);
1499
1500         armclk = clk_get_rate(&exynos4_clk_armclk.clk);
1501         sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
1502
1503         aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
1504         aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
1505         aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
1506         aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
1507
1508         printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1509                          "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1510                         armclk, sclk_dmc, aclk_200,
1511                         aclk_100, aclk_160, aclk_133);
1512
1513         clk_f.rate = armclk;
1514         clk_h.rate = sclk_dmc;
1515         clk_p.rate = aclk_100;
1516
1517         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
1518                 s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
1519 }
1520
1521 static struct clk *exynos4_clks[] __initdata = {
1522         &exynos4_clk_sclk_hdmi27m,
1523         &exynos4_clk_sclk_hdmiphy,
1524         &exynos4_clk_sclk_usbphy0,
1525         &exynos4_clk_sclk_usbphy1,
1526 };
1527
1528 #ifdef CONFIG_PM_SLEEP
1529 static int exynos4_clock_suspend(void)
1530 {
1531         s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1532         return 0;
1533 }
1534
1535 static void exynos4_clock_resume(void)
1536 {
1537         s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1538 }
1539
1540 #else
1541 #define exynos4_clock_suspend NULL
1542 #define exynos4_clock_resume NULL
1543 #endif
1544
1545 static struct syscore_ops exynos4_clock_syscore_ops = {
1546         .suspend        = exynos4_clock_suspend,
1547         .resume         = exynos4_clock_resume,
1548 };
1549
1550 void __init exynos4_register_clocks(void)
1551 {
1552         int ptr;
1553
1554         s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
1555
1556         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
1557                 s3c_register_clksrc(exynos4_sysclks[ptr], 1);
1558
1559         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
1560                 s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
1561
1562         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
1563                 s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
1564
1565         s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
1566         s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
1567
1568         s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
1569         for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
1570                 s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
1571
1572         s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1573         s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
1574         clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1575
1576         register_syscore_ops(&exynos4_clock_syscore_ops);
1577         s3c24xx_register_clock(&dummy_apb_pclk);
1578
1579         s3c_pwmclk_init();
1580 }