2 * arch/arm/mach-dove/common.c
4 * Core functions for Marvell Dove 88AP510 System On Chip
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/clk-provider.h>
12 #include <linux/clk/mvebu.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/init.h>
16 #include <linux/of_platform.h>
17 #include <linux/platform_data/dma-mv_xor.h>
18 #include <linux/platform_data/usb-ehci-orion.h>
19 #include <linux/platform_device.h>
20 #include <asm/hardware/cache-tauros2.h>
21 #include <asm/mach/arch.h>
22 #include <asm/mach/map.h>
23 #include <asm/mach/time.h>
24 #include <mach/bridge-regs.h>
26 #include <plat/common.h>
28 #include <plat/time.h>
31 /*****************************************************************************
33 ****************************************************************************/
34 static struct map_desc dove_io_desc[] __initdata = {
36 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
37 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
38 .length = DOVE_SB_REGS_SIZE,
41 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
42 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
43 .length = DOVE_NB_REGS_SIZE,
48 void __init dove_map_io(void)
50 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
53 /*****************************************************************************
55 ****************************************************************************/
58 static DEFINE_SPINLOCK(gating_lock);
59 static struct clk *tclk;
61 static struct clk __init *dove_register_gate(const char *name,
62 const char *parent, u8 bit_idx)
64 return clk_register_gate(NULL, name, parent, 0,
65 (void __iomem *)CLOCK_GATING_CONTROL,
66 bit_idx, 0, &gating_lock);
69 static void __init dove_clk_init(void)
71 struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
72 struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
73 struct clk *xor0, *xor1, *ge, *gephy;
75 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
78 usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
79 usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
80 sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
81 pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
82 pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
83 sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
84 sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
85 nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
86 camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
87 i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
88 i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
89 crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
90 ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
91 pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
92 xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
93 xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
94 gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
95 ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
97 orion_clkdev_add(NULL, "orion_spi.0", tclk);
98 orion_clkdev_add(NULL, "orion_spi.1", tclk);
99 orion_clkdev_add(NULL, "orion_wdt", tclk);
100 orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
102 orion_clkdev_add(NULL, "orion-ehci.0", usb0);
103 orion_clkdev_add(NULL, "orion-ehci.1", usb1);
104 orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
105 orion_clkdev_add(NULL, "sata_mv.0", sata);
106 orion_clkdev_add("0", "pcie", pex0);
107 orion_clkdev_add("1", "pcie", pex1);
108 orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
109 orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
110 orion_clkdev_add(NULL, "orion_nand", nand);
111 orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
112 orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
113 orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
114 orion_clkdev_add(NULL, "mv_crypto", crypto);
115 orion_clkdev_add(NULL, "dove-ac97", ac97);
116 orion_clkdev_add(NULL, "dove-pdma", pdma);
117 orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
118 orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
121 /*****************************************************************************
123 ****************************************************************************/
124 void __init dove_ehci0_init(void)
126 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
129 /*****************************************************************************
131 ****************************************************************************/
132 void __init dove_ehci1_init(void)
134 orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
137 /*****************************************************************************
139 ****************************************************************************/
140 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
142 orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
143 IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
147 /*****************************************************************************
149 ****************************************************************************/
150 void __init dove_rtc_init(void)
152 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
155 /*****************************************************************************
157 ****************************************************************************/
158 void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
160 orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
164 /*****************************************************************************
166 ****************************************************************************/
167 void __init dove_uart0_init(void)
169 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
170 IRQ_DOVE_UART_0, tclk);
173 /*****************************************************************************
175 ****************************************************************************/
176 void __init dove_uart1_init(void)
178 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
179 IRQ_DOVE_UART_1, tclk);
182 /*****************************************************************************
184 ****************************************************************************/
185 void __init dove_uart2_init(void)
187 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
188 IRQ_DOVE_UART_2, tclk);
191 /*****************************************************************************
193 ****************************************************************************/
194 void __init dove_uart3_init(void)
196 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
197 IRQ_DOVE_UART_3, tclk);
200 /*****************************************************************************
202 ****************************************************************************/
203 void __init dove_spi0_init(void)
205 orion_spi_init(DOVE_SPI0_PHYS_BASE);
208 void __init dove_spi1_init(void)
210 orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
213 /*****************************************************************************
215 ****************************************************************************/
216 void __init dove_i2c_init(void)
218 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
221 /*****************************************************************************
223 ****************************************************************************/
224 void __init dove_init_early(void)
226 orion_time_set_base(TIMER_VIRT_BASE);
229 static int __init dove_find_tclk(void)
234 static void __init dove_timer_init(void)
236 dove_tclk = dove_find_tclk();
237 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
238 IRQ_DOVE_BRIDGE, dove_tclk);
241 struct sys_timer dove_timer = {
242 .init = dove_timer_init,
245 /*****************************************************************************
246 * Cryptographic Engines and Security Accelerator (CESA)
247 ****************************************************************************/
248 void __init dove_crypto_init(void)
250 orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
251 DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
254 /*****************************************************************************
256 ****************************************************************************/
257 void __init dove_xor0_init(void)
259 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
260 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
263 /*****************************************************************************
265 ****************************************************************************/
266 void __init dove_xor1_init(void)
268 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
269 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
272 /*****************************************************************************
274 ****************************************************************************/
275 static u64 sdio_dmamask = DMA_BIT_MASK(32);
277 static struct resource dove_sdio0_resources[] = {
279 .start = DOVE_SDIO0_PHYS_BASE,
280 .end = DOVE_SDIO0_PHYS_BASE + 0xff,
281 .flags = IORESOURCE_MEM,
283 .start = IRQ_DOVE_SDIO0,
284 .end = IRQ_DOVE_SDIO0,
285 .flags = IORESOURCE_IRQ,
289 static struct platform_device dove_sdio0 = {
290 .name = "sdhci-dove",
293 .dma_mask = &sdio_dmamask,
294 .coherent_dma_mask = DMA_BIT_MASK(32),
296 .resource = dove_sdio0_resources,
297 .num_resources = ARRAY_SIZE(dove_sdio0_resources),
300 void __init dove_sdio0_init(void)
302 platform_device_register(&dove_sdio0);
305 static struct resource dove_sdio1_resources[] = {
307 .start = DOVE_SDIO1_PHYS_BASE,
308 .end = DOVE_SDIO1_PHYS_BASE + 0xff,
309 .flags = IORESOURCE_MEM,
311 .start = IRQ_DOVE_SDIO1,
312 .end = IRQ_DOVE_SDIO1,
313 .flags = IORESOURCE_IRQ,
317 static struct platform_device dove_sdio1 = {
318 .name = "sdhci-dove",
321 .dma_mask = &sdio_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32),
324 .resource = dove_sdio1_resources,
325 .num_resources = ARRAY_SIZE(dove_sdio1_resources),
328 void __init dove_sdio1_init(void)
330 platform_device_register(&dove_sdio1);
333 void __init dove_init(void)
335 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
336 (dove_tclk + 499999) / 1000000);
338 #ifdef CONFIG_CACHE_TAUROS2
341 dove_setup_cpu_mbus();
343 /* Setup root of clk tree */
346 /* internal devices that every board has */
352 void dove_restart(char mode, const char *cmd)
355 * Enable soft reset to assert RSTOUTn.
357 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
362 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
368 #if defined(CONFIG_MACH_DOVE_DT)
370 * There are still devices that doesn't even know about DT,
371 * get clock gates here and add a clock lookup.
373 static void __init dove_legacy_clk_init(void)
375 struct device_node *np = of_find_compatible_node(NULL, NULL,
376 "marvell,dove-gating-clock");
377 struct of_phandle_args clkspec;
380 clkspec.args_count = 1;
382 clkspec.args[0] = CLOCK_GATING_BIT_USB0;
383 orion_clkdev_add(NULL, "orion-ehci.0",
384 of_clk_get_from_provider(&clkspec));
386 clkspec.args[0] = CLOCK_GATING_BIT_USB1;
387 orion_clkdev_add(NULL, "orion-ehci.1",
388 of_clk_get_from_provider(&clkspec));
390 clkspec.args[0] = CLOCK_GATING_BIT_GBE;
391 orion_clkdev_add(NULL, "mv643xx_eth_port.0",
392 of_clk_get_from_provider(&clkspec));
394 clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
395 orion_clkdev_add("0", "pcie",
396 of_clk_get_from_provider(&clkspec));
398 clkspec.args[0] = CLOCK_GATING_BIT_PCIE1;
399 orion_clkdev_add("1", "pcie",
400 of_clk_get_from_provider(&clkspec));
403 static void __init dove_of_clk_init(void)
406 dove_legacy_clk_init();
409 static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
410 .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
413 static void __init dove_dt_init(void)
415 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
416 (dove_tclk + 499999) / 1000000);
418 #ifdef CONFIG_CACHE_TAUROS2
421 dove_setup_cpu_mbus();
423 /* Setup root of clk tree */
426 /* Internal devices not ported to DT yet */
429 dove_ge00_init(&dove_dt_ge00_data);
432 dove_pcie_init(1, 1);
434 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
437 static const char * const dove_dt_board_compat[] = {
442 DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
443 .map_io = dove_map_io,
444 .init_early = dove_init_early,
445 .init_irq = orion_dt_init_irq,
446 .timer = &dove_timer,
447 .init_machine = dove_dt_init,
448 .restart = dove_restart,
449 .dt_compat = dove_dt_board_compat,