arch/arm/mach-at91/setup.c

   1 /*
   2  * Copyright (C) 2007 Atmel Corporation.
   3  * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
   4  *
   5  * Under GPLv2
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/io.h>
  10 #include <linux/mm.h>
  11 #include <linux/pm.h>
  12 #include <linux/of_address.h>
  13
  14 #include <asm/system_misc.h>
  15 #include <asm/mach/map.h>
  16
  17 #include <mach/hardware.h>
  18 #include <mach/cpu.h>
  19 #include <mach/at91_dbgu.h>
  20 #include <mach/at91_pmc.h>
  21 #include <mach/at91_shdwc.h>
  22
  23 #include "soc.h"
  24 #include "generic.h"
  25
  26 struct at91_init_soc __initdata at91_boot_soc;
  27
  28 struct at91_socinfo at91_soc_initdata;
  29 EXPORT_SYMBOL(at91_soc_initdata);
  30
  31 void __init at91rm9200_set_type(int type)
  32 {
  33         if (type == ARCH_REVISON_9200_PQFP)
  34                 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
  35         else
  36                 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
  37
  38         pr_info("AT91: filled in soc subtype: %s\n",
  39                 at91_get_soc_subtype(&at91_soc_initdata));
  40 }
  41
  42 void __init at91_init_irq_default(void)
  43 {
  44         at91_init_interrupts(at91_boot_soc.default_irq_priority);
  45 }
  46
  47 void __init at91_init_interrupts(unsigned int *priority)
  48 {
  49         /* Initialize the AIC interrupt controller */
  50         at91_aic_init(priority);
  51
  52         /* Enable GPIO interrupts */
  53         at91_gpio_irq_setup();
  54 }
  55
  56 void __iomem *at91_ramc_base[2];
  57
  58 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
  59 {
  60         if (id < 0 || id > 1) {
  61                 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
  62                 BUG();
  63         }
  64         at91_ramc_base[id] = ioremap(addr, size);
  65         if (!at91_ramc_base[id])
  66                 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
  67 }
  68
  69 static struct map_desc sram_desc[2] __initdata;
  70
  71 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
  72 {
  73         struct map_desc *desc = &sram_desc[bank];
  74
  75         desc->virtual = AT91_IO_VIRT_BASE - length;
  76         if (bank > 0)
  77                 desc->virtual -= sram_desc[bank - 1].length;
  78
  79         desc->pfn = __phys_to_pfn(base);
  80         desc->length = length;
  81         desc->type = MT_DEVICE;
  82
  83         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
  84                 base, length, desc->virtual);
  85
  86         iotable_init(desc, 1);
  87 }
  88
  89 static struct map_desc at91_io_desc __initdata = {
  90         .virtual        = AT91_VA_BASE_SYS,
  91         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  92         .length         = SZ_16K,
  93         .type           = MT_DEVICE,
  94 };
  95
  96 static void __init soc_detect(u32 dbgu_base)
  97 {
  98         u32 cidr, socid;
  99
 100         cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
 101         socid = cidr & ~AT91_CIDR_VERSION;
 102
 103         switch (socid) {
 104         case ARCH_ID_AT91RM9200:
 105                 at91_soc_initdata.type = AT91_SOC_RM9200;
 106                 at91_boot_soc = at91rm9200_soc;
 107                 break;
 108
 109         case ARCH_ID_AT91SAM9260:
 110                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 111                 at91_boot_soc = at91sam9260_soc;
 112                 break;
 113
 114         case ARCH_ID_AT91SAM9261:
 115                 at91_soc_initdata.type = AT91_SOC_SAM9261;
 116                 at91_boot_soc = at91sam9261_soc;
 117                 break;
 118
 119         case ARCH_ID_AT91SAM9263:
 120                 at91_soc_initdata.type = AT91_SOC_SAM9263;
 121                 at91_boot_soc = at91sam9263_soc;
 122                 break;
 123
 124         case ARCH_ID_AT91SAM9G20:
 125                 at91_soc_initdata.type = AT91_SOC_SAM9G20;
 126                 at91_boot_soc = at91sam9260_soc;
 127                 break;
 128
 129         case ARCH_ID_AT91SAM9G45:
 130                 at91_soc_initdata.type = AT91_SOC_SAM9G45;
 131                 if (cidr == ARCH_ID_AT91SAM9G45ES)
 132                         at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
 133                 at91_boot_soc = at91sam9g45_soc;
 134                 break;
 135
 136         case ARCH_ID_AT91SAM9RL64:
 137                 at91_soc_initdata.type = AT91_SOC_SAM9RL;
 138                 at91_boot_soc = at91sam9rl_soc;
 139                 break;
 140
 141         case ARCH_ID_AT91SAM9X5:
 142                 at91_soc_initdata.type = AT91_SOC_SAM9X5;
 143                 at91_boot_soc = at91sam9x5_soc;
 144                 break;
 145         }
 146
 147         /* at91sam9g10 */
 148         if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
 149                 at91_soc_initdata.type = AT91_SOC_SAM9G10;
 150                 at91_boot_soc = at91sam9261_soc;
 151         }
 152         /* at91sam9xe */
 153         else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
 154                 at91_soc_initdata.type = AT91_SOC_SAM9260;
 155                 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
 156                 at91_boot_soc = at91sam9260_soc;
 157         }
 158
 159         if (!at91_soc_is_detected())
 160                 return;
 161
 162         at91_soc_initdata.cidr = cidr;
 163
 164         /* sub version of soc */
 165         at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
 166
 167         if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
 168                 switch (at91_soc_initdata.exid) {
 169                 case ARCH_EXID_AT91SAM9M10:
 170                         at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
 171                         break;
 172                 case ARCH_EXID_AT91SAM9G46:
 173                         at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
 174                         break;
 175                 case ARCH_EXID_AT91SAM9M11:
 176                         at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
 177                         break;
 178                 }
 179         }
 180
 181         if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
 182                 switch (at91_soc_initdata.exid) {
 183                 case ARCH_EXID_AT91SAM9G15:
 184                         at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
 185                         break;
 186                 case ARCH_EXID_AT91SAM9G35:
 187                         at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
 188                         break;
 189                 case ARCH_EXID_AT91SAM9X35:
 190                         at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
 191                         break;
 192                 case ARCH_EXID_AT91SAM9G25:
 193                         at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
 194                         break;
 195                 case ARCH_EXID_AT91SAM9X25:
 196                         at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
 197                         break;
 198                 }
 199         }
 200 }
 201
 202 static const char *soc_name[] = {
 203         [AT91_SOC_RM9200]       = "at91rm9200",
 204         [AT91_SOC_SAM9260]      = "at91sam9260",
 205         [AT91_SOC_SAM9261]      = "at91sam9261",
 206         [AT91_SOC_SAM9263]      = "at91sam9263",
 207         [AT91_SOC_SAM9G10]      = "at91sam9g10",
 208         [AT91_SOC_SAM9G20]      = "at91sam9g20",
 209         [AT91_SOC_SAM9G45]      = "at91sam9g45",
 210         [AT91_SOC_SAM9RL]       = "at91sam9rl",
 211         [AT91_SOC_SAM9X5]       = "at91sam9x5",
 212         [AT91_SOC_NONE]         = "Unknown"
 213 };
 214
 215 const char *at91_get_soc_type(struct at91_socinfo *c)
 216 {
 217         return soc_name[c->type];
 218 }
 219 EXPORT_SYMBOL(at91_get_soc_type);
 220
 221 static const char *soc_subtype_name[] = {
 222         [AT91_SOC_RM9200_BGA]   = "at91rm9200 BGA",
 223         [AT91_SOC_RM9200_PQFP]  = "at91rm9200 PQFP",
 224         [AT91_SOC_SAM9XE]       = "at91sam9xe",
 225         [AT91_SOC_SAM9G45ES]    = "at91sam9g45es",
 226         [AT91_SOC_SAM9M10]      = "at91sam9m10",
 227         [AT91_SOC_SAM9G46]      = "at91sam9g46",
 228         [AT91_SOC_SAM9M11]      = "at91sam9m11",
 229         [AT91_SOC_SAM9G15]      = "at91sam9g15",
 230         [AT91_SOC_SAM9G35]      = "at91sam9g35",
 231         [AT91_SOC_SAM9X35]      = "at91sam9x35",
 232         [AT91_SOC_SAM9G25]      = "at91sam9g25",
 233         [AT91_SOC_SAM9X25]      = "at91sam9x25",
 234         [AT91_SOC_SUBTYPE_NONE] = "Unknown"
 235 };
 236
 237 const char *at91_get_soc_subtype(struct at91_socinfo *c)
 238 {
 239         return soc_subtype_name[c->subtype];
 240 }
 241 EXPORT_SYMBOL(at91_get_soc_subtype);
 242
 243 void __init at91_map_io(void)
 244 {
 245         /* Map peripherals */
 246         iotable_init(&at91_io_desc, 1);
 247
 248         at91_soc_initdata.type = AT91_SOC_NONE;
 249         at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
 250
 251         soc_detect(AT91_BASE_DBGU0);
 252         if (!at91_soc_is_detected())
 253                 soc_detect(AT91_BASE_DBGU1);
 254
 255         if (!at91_soc_is_detected())
 256                 panic("AT91: Impossible to detect the SOC type");
 257
 258         pr_info("AT91: Detected soc type: %s\n",
 259                 at91_get_soc_type(&at91_soc_initdata));
 260         pr_info("AT91: Detected soc subtype: %s\n",
 261                 at91_get_soc_subtype(&at91_soc_initdata));
 262
 263         if (!at91_soc_is_enabled())
 264                 panic("AT91: Soc not enabled");
 265
 266         if (at91_boot_soc.map_io)
 267                 at91_boot_soc.map_io();
 268 }
 269
 270 void __iomem *at91_shdwc_base = NULL;
 271
 272 static void at91sam9_poweroff(void)
 273 {
 274         at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 275 }
 276
 277 void __init at91_ioremap_shdwc(u32 base_addr)
 278 {
 279         at91_shdwc_base = ioremap(base_addr, 16);
 280         if (!at91_shdwc_base)
 281                 panic("Impossible to ioremap at91_shdwc_base\n");
 282         pm_power_off = at91sam9_poweroff;
 283 }
 284
 285 void __iomem *at91_rstc_base;
 286
 287 void __init at91_ioremap_rstc(u32 base_addr)
 288 {
 289         at91_rstc_base = ioremap(base_addr, 16);
 290         if (!at91_rstc_base)
 291                 panic("Impossible to ioremap at91_rstc_base\n");
 292 }
 293
 294 void __iomem *at91_matrix_base;
 295
 296 void __init at91_ioremap_matrix(u32 base_addr)
 297 {
 298         at91_matrix_base = ioremap(base_addr, 512);
 299         if (!at91_matrix_base)
 300                 panic("Impossible to ioremap at91_matrix_base\n");
 301 }
 302
 303 #if defined(CONFIG_OF)
 304 static struct of_device_id rstc_ids[] = {
 305         { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
 306         { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
 307         { /*sentinel*/ }
 308 };
 309
 310 static void at91_dt_rstc(void)
 311 {
 312         struct device_node *np;
 313         const struct of_device_id *of_id;
 314
 315         np = of_find_matching_node(NULL, rstc_ids);
 316         if (!np)
 317                 panic("unable to find compatible rstc node in dtb\n");
 318
 319         at91_rstc_base = of_iomap(np, 0);
 320         if (!at91_rstc_base)
 321                 panic("unable to map rstc cpu registers\n");
 322
 323         of_id = of_match_node(rstc_ids, np);
 324         if (!of_id)
 325                 panic("AT91: rtsc no restart function availlable\n");
 326
 327         arm_pm_restart = of_id->data;
 328
 329         of_node_put(np);
 330 }
 331
 332 static struct of_device_id ramc_ids[] = {
 333         { .compatible = "atmel,at91sam9260-sdramc" },
 334         { .compatible = "atmel,at91sam9g45-ddramc" },
 335         { /*sentinel*/ }
 336 };
 337
 338 static void at91_dt_ramc(void)
 339 {
 340         struct device_node *np;
 341
 342         np = of_find_matching_node(NULL, ramc_ids);
 343         if (!np)
 344                 panic("unable to find compatible ram conroller node in dtb\n");
 345
 346         at91_ramc_base[0] = of_iomap(np, 0);
 347         if (!at91_ramc_base[0])
 348                 panic("unable to map ramc[0] cpu registers\n");
 349         /* the controller may have 2 banks */
 350         at91_ramc_base[1] = of_iomap(np, 1);
 351
 352         of_node_put(np);
 353 }
 354
 355 static struct of_device_id shdwc_ids[] = {
 356         { .compatible = "atmel,at91sam9260-shdwc", },
 357         { .compatible = "atmel,at91sam9rl-shdwc", },
 358         { .compatible = "atmel,at91sam9x5-shdwc", },
 359         { /*sentinel*/ }
 360 };
 361
 362 static const char *shdwc_wakeup_modes[] = {
 363         [AT91_SHDW_WKMODE0_NONE]        = "none",
 364         [AT91_SHDW_WKMODE0_HIGH]        = "high",
 365         [AT91_SHDW_WKMODE0_LOW]         = "low",
 366         [AT91_SHDW_WKMODE0_ANYLEVEL]    = "any",
 367 };
 368
 369 const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
 370 {
 371         const char *pm;
 372         int err, i;
 373
 374         err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
 375         if (err < 0)
 376                 return AT91_SHDW_WKMODE0_ANYLEVEL;
 377
 378         for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
 379                 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
 380                         return i;
 381
 382         return -ENODEV;
 383 }
 384
 385 static void at91_dt_shdwc(void)
 386 {
 387         struct device_node *np;
 388         int wakeup_mode;
 389         u32 reg;
 390         u32 mode = 0;
 391
 392         np = of_find_matching_node(NULL, shdwc_ids);
 393         if (!np) {
 394                 pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
 395                 return;
 396         }
 397
 398         at91_shdwc_base = of_iomap(np, 0);
 399         if (!at91_shdwc_base)
 400                 panic("AT91: unable to map shdwc cpu registers\n");
 401
 402         wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
 403         if (wakeup_mode < 0) {
 404                 pr_warn("AT91: shdwc unknown wakeup mode\n");
 405                 goto end;
 406         }
 407
 408         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
 409                 if (reg > AT91_SHDW_CPTWK0_MAX) {
 410                         pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
 411                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
 412                         reg = AT91_SHDW_CPTWK0_MAX;
 413                 }
 414                 mode |= AT91_SHDW_CPTWK0_(reg);
 415         }
 416
 417         if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
 418                         mode |= AT91_SHDW_RTCWKEN;
 419
 420         if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
 421                         mode |= AT91_SHDW_RTTWKEN;
 422
 423         at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
 424
 425 end:
 426         pm_power_off = at91sam9_poweroff;
 427
 428         of_node_put(np);
 429 }
 430
 431 void __init at91_dt_initialize(void)
 432 {
 433         at91_dt_rstc();
 434         at91_dt_ramc();
 435         at91_dt_shdwc();
 436
 437         /* Init clock subsystem */
 438         at91_dt_clock_init();
 439
 440         /* Register the processor-specific clocks */
 441         at91_boot_soc.register_clocks();
 442
 443         at91_boot_soc.init();
 444 }
 445 #endif
 446
 447 void __init at91_initialize(unsigned long main_clock)
 448 {
 449         at91_boot_soc.ioremap_registers();
 450
 451         /* Init clock subsystem */
 452         at91_clock_init(main_clock);
 453
 454         /* Register the processor-specific clocks */
 455         at91_boot_soc.register_clocks();
 456
 457         at91_boot_soc.init();
 458 }