2 * Copyright (C) 2007 Atmel Corporation.
3 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 #include <linux/module.h>
12 #include <linux/of_address.h>
14 #include <asm/system_misc.h>
15 #include <asm/mach/map.h>
17 #include <mach/hardware.h>
19 #include <mach/at91_dbgu.h>
20 #include <mach/at91_pmc.h>
21 #include <mach/at91_shdwc.h>
26 struct at91_init_soc __initdata at91_boot_soc;
28 struct at91_socinfo at91_soc_initdata;
29 EXPORT_SYMBOL(at91_soc_initdata);
31 void __init at91rm9200_set_type(int type)
33 if (type == ARCH_REVISON_9200_PQFP)
34 at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
36 at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
38 pr_info("AT91: filled in soc subtype: %s\n",
39 at91_get_soc_subtype(&at91_soc_initdata));
42 void __init at91_init_irq_default(void)
44 at91_init_interrupts(at91_boot_soc.default_irq_priority);
47 void __init at91_init_interrupts(unsigned int *priority)
49 /* Initialize the AIC interrupt controller */
50 at91_aic_init(priority);
52 /* Enable GPIO interrupts */
53 at91_gpio_irq_setup();
56 void __iomem *at91_ramc_base[2];
58 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
60 if (id < 0 || id > 1) {
61 pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
64 at91_ramc_base[id] = ioremap(addr, size);
65 if (!at91_ramc_base[id])
66 panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
69 static struct map_desc sram_desc[2] __initdata;
71 void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
73 struct map_desc *desc = &sram_desc[bank];
75 desc->virtual = AT91_IO_VIRT_BASE - length;
77 desc->virtual -= sram_desc[bank - 1].length;
79 desc->pfn = __phys_to_pfn(base);
80 desc->length = length;
81 desc->type = MT_DEVICE;
83 pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
84 base, length, desc->virtual);
86 iotable_init(desc, 1);
89 static struct map_desc at91_io_desc __initdata = {
90 .virtual = AT91_VA_BASE_SYS,
91 .pfn = __phys_to_pfn(AT91_BASE_SYS),
96 static void __init soc_detect(u32 dbgu_base)
100 cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
101 socid = cidr & ~AT91_CIDR_VERSION;
104 case ARCH_ID_AT91RM9200:
105 at91_soc_initdata.type = AT91_SOC_RM9200;
106 at91_boot_soc = at91rm9200_soc;
109 case ARCH_ID_AT91SAM9260:
110 at91_soc_initdata.type = AT91_SOC_SAM9260;
111 at91_boot_soc = at91sam9260_soc;
114 case ARCH_ID_AT91SAM9261:
115 at91_soc_initdata.type = AT91_SOC_SAM9261;
116 at91_boot_soc = at91sam9261_soc;
119 case ARCH_ID_AT91SAM9263:
120 at91_soc_initdata.type = AT91_SOC_SAM9263;
121 at91_boot_soc = at91sam9263_soc;
124 case ARCH_ID_AT91SAM9G20:
125 at91_soc_initdata.type = AT91_SOC_SAM9G20;
126 at91_boot_soc = at91sam9260_soc;
129 case ARCH_ID_AT91SAM9G45:
130 at91_soc_initdata.type = AT91_SOC_SAM9G45;
131 if (cidr == ARCH_ID_AT91SAM9G45ES)
132 at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
133 at91_boot_soc = at91sam9g45_soc;
136 case ARCH_ID_AT91SAM9RL64:
137 at91_soc_initdata.type = AT91_SOC_SAM9RL;
138 at91_boot_soc = at91sam9rl_soc;
141 case ARCH_ID_AT91SAM9X5:
142 at91_soc_initdata.type = AT91_SOC_SAM9X5;
143 at91_boot_soc = at91sam9x5_soc;
148 if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
149 at91_soc_initdata.type = AT91_SOC_SAM9G10;
150 at91_boot_soc = at91sam9261_soc;
153 else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
154 at91_soc_initdata.type = AT91_SOC_SAM9260;
155 at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
156 at91_boot_soc = at91sam9260_soc;
159 if (!at91_soc_is_detected())
162 at91_soc_initdata.cidr = cidr;
164 /* sub version of soc */
165 at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
167 if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
168 switch (at91_soc_initdata.exid) {
169 case ARCH_EXID_AT91SAM9M10:
170 at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
172 case ARCH_EXID_AT91SAM9G46:
173 at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
175 case ARCH_EXID_AT91SAM9M11:
176 at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
181 if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
182 switch (at91_soc_initdata.exid) {
183 case ARCH_EXID_AT91SAM9G15:
184 at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
186 case ARCH_EXID_AT91SAM9G35:
187 at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
189 case ARCH_EXID_AT91SAM9X35:
190 at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
192 case ARCH_EXID_AT91SAM9G25:
193 at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
195 case ARCH_EXID_AT91SAM9X25:
196 at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
202 static const char *soc_name[] = {
203 [AT91_SOC_RM9200] = "at91rm9200",
204 [AT91_SOC_SAM9260] = "at91sam9260",
205 [AT91_SOC_SAM9261] = "at91sam9261",
206 [AT91_SOC_SAM9263] = "at91sam9263",
207 [AT91_SOC_SAM9G10] = "at91sam9g10",
208 [AT91_SOC_SAM9G20] = "at91sam9g20",
209 [AT91_SOC_SAM9G45] = "at91sam9g45",
210 [AT91_SOC_SAM9RL] = "at91sam9rl",
211 [AT91_SOC_SAM9X5] = "at91sam9x5",
212 [AT91_SOC_NONE] = "Unknown"
215 const char *at91_get_soc_type(struct at91_socinfo *c)
217 return soc_name[c->type];
219 EXPORT_SYMBOL(at91_get_soc_type);
221 static const char *soc_subtype_name[] = {
222 [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
223 [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
224 [AT91_SOC_SAM9XE] = "at91sam9xe",
225 [AT91_SOC_SAM9G45ES] = "at91sam9g45es",
226 [AT91_SOC_SAM9M10] = "at91sam9m10",
227 [AT91_SOC_SAM9G46] = "at91sam9g46",
228 [AT91_SOC_SAM9M11] = "at91sam9m11",
229 [AT91_SOC_SAM9G15] = "at91sam9g15",
230 [AT91_SOC_SAM9G35] = "at91sam9g35",
231 [AT91_SOC_SAM9X35] = "at91sam9x35",
232 [AT91_SOC_SAM9G25] = "at91sam9g25",
233 [AT91_SOC_SAM9X25] = "at91sam9x25",
234 [AT91_SOC_SUBTYPE_NONE] = "Unknown"
237 const char *at91_get_soc_subtype(struct at91_socinfo *c)
239 return soc_subtype_name[c->subtype];
241 EXPORT_SYMBOL(at91_get_soc_subtype);
243 void __init at91_map_io(void)
245 /* Map peripherals */
246 iotable_init(&at91_io_desc, 1);
248 at91_soc_initdata.type = AT91_SOC_NONE;
249 at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
251 soc_detect(AT91_BASE_DBGU0);
252 if (!at91_soc_is_detected())
253 soc_detect(AT91_BASE_DBGU1);
255 if (!at91_soc_is_detected())
256 panic("AT91: Impossible to detect the SOC type");
258 pr_info("AT91: Detected soc type: %s\n",
259 at91_get_soc_type(&at91_soc_initdata));
260 pr_info("AT91: Detected soc subtype: %s\n",
261 at91_get_soc_subtype(&at91_soc_initdata));
263 if (!at91_soc_is_enabled())
264 panic("AT91: Soc not enabled");
266 if (at91_boot_soc.map_io)
267 at91_boot_soc.map_io();
270 void __iomem *at91_shdwc_base = NULL;
272 static void at91sam9_poweroff(void)
274 at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
277 void __init at91_ioremap_shdwc(u32 base_addr)
279 at91_shdwc_base = ioremap(base_addr, 16);
280 if (!at91_shdwc_base)
281 panic("Impossible to ioremap at91_shdwc_base\n");
282 pm_power_off = at91sam9_poweroff;
285 void __iomem *at91_rstc_base;
287 void __init at91_ioremap_rstc(u32 base_addr)
289 at91_rstc_base = ioremap(base_addr, 16);
291 panic("Impossible to ioremap at91_rstc_base\n");
294 void __iomem *at91_matrix_base;
296 void __init at91_ioremap_matrix(u32 base_addr)
298 at91_matrix_base = ioremap(base_addr, 512);
299 if (!at91_matrix_base)
300 panic("Impossible to ioremap at91_matrix_base\n");
303 #if defined(CONFIG_OF)
304 static struct of_device_id rstc_ids[] = {
305 { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
306 { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
310 static void at91_dt_rstc(void)
312 struct device_node *np;
313 const struct of_device_id *of_id;
315 np = of_find_matching_node(NULL, rstc_ids);
317 panic("unable to find compatible rstc node in dtb\n");
319 at91_rstc_base = of_iomap(np, 0);
321 panic("unable to map rstc cpu registers\n");
323 of_id = of_match_node(rstc_ids, np);
325 panic("AT91: rtsc no restart function availlable\n");
327 arm_pm_restart = of_id->data;
332 static struct of_device_id ramc_ids[] = {
333 { .compatible = "atmel,at91sam9260-sdramc" },
334 { .compatible = "atmel,at91sam9g45-ddramc" },
338 static void at91_dt_ramc(void)
340 struct device_node *np;
342 np = of_find_matching_node(NULL, ramc_ids);
344 panic("unable to find compatible ram conroller node in dtb\n");
346 at91_ramc_base[0] = of_iomap(np, 0);
347 if (!at91_ramc_base[0])
348 panic("unable to map ramc[0] cpu registers\n");
349 /* the controller may have 2 banks */
350 at91_ramc_base[1] = of_iomap(np, 1);
355 static struct of_device_id shdwc_ids[] = {
356 { .compatible = "atmel,at91sam9260-shdwc", },
357 { .compatible = "atmel,at91sam9rl-shdwc", },
358 { .compatible = "atmel,at91sam9x5-shdwc", },
362 static const char *shdwc_wakeup_modes[] = {
363 [AT91_SHDW_WKMODE0_NONE] = "none",
364 [AT91_SHDW_WKMODE0_HIGH] = "high",
365 [AT91_SHDW_WKMODE0_LOW] = "low",
366 [AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
369 const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
374 err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
376 return AT91_SHDW_WKMODE0_ANYLEVEL;
378 for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
379 if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
385 static void at91_dt_shdwc(void)
387 struct device_node *np;
392 np = of_find_matching_node(NULL, shdwc_ids);
394 pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
398 at91_shdwc_base = of_iomap(np, 0);
399 if (!at91_shdwc_base)
400 panic("AT91: unable to map shdwc cpu registers\n");
402 wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
403 if (wakeup_mode < 0) {
404 pr_warn("AT91: shdwc unknown wakeup mode\n");
408 if (!of_property_read_u32(np, "atmel,wakeup-counter", ®)) {
409 if (reg > AT91_SHDW_CPTWK0_MAX) {
410 pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
411 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
412 reg = AT91_SHDW_CPTWK0_MAX;
414 mode |= AT91_SHDW_CPTWK0_(reg);
417 if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
418 mode |= AT91_SHDW_RTCWKEN;
420 if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
421 mode |= AT91_SHDW_RTTWKEN;
423 at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);
426 pm_power_off = at91sam9_poweroff;
431 void __init at91_dt_initialize(void)
437 /* Init clock subsystem */
438 at91_dt_clock_init();
440 /* Register the processor-specific clocks */
441 at91_boot_soc.register_clocks();
443 at91_boot_soc.init();
447 void __init at91_initialize(unsigned long main_clock)
449 at91_boot_soc.ioremap_registers();
451 /* Init clock subsystem */
452 at91_clock_init(main_clock);
454 /* Register the processor-specific clocks */
455 at91_boot_soc.register_clocks();
457 at91_boot_soc.init();