2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
5 * Copyright (C) 2005 David Brownell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/gpio.h>
14 #include <linux/suspend.h>
15 #include <linux/sched.h>
16 #include <linux/proc_fs.h>
17 #include <linux/genalloc.h>
18 #include <linux/interrupt.h>
19 #include <linux/sysfs.h>
20 #include <linux/module.h>
22 #include <linux/of_platform.h>
23 #include <linux/of_address.h>
24 #include <linux/platform_device.h>
26 #include <linux/clk/at91_pmc.h>
29 #include <linux/atomic.h>
30 #include <asm/mach/time.h>
31 #include <asm/mach/irq.h>
32 #include <asm/fncpy.h>
33 #include <asm/cacheflush.h>
39 * FIXME: this is needed to communicate between the pinctrl driver and
40 * the PM implementation in the machine. Possibly part of the PM
41 * implementation should be moved down into the pinctrl driver and get
42 * called as part of the generic suspend/resume path.
44 extern void at91_pinctrl_gpio_suspend(void);
45 extern void at91_pinctrl_gpio_resume(void);
48 unsigned long uhp_udp_mask;
52 void __iomem *at91_ramc_base[2];
54 static int at91_pm_valid_state(suspend_state_t state)
58 case PM_SUSPEND_STANDBY:
68 static suspend_state_t target_state;
71 * Called after processes are frozen, but before we shutdown devices.
73 static int at91_pm_begin(suspend_state_t state)
80 * Verify that all the clocks are correct before entering
83 static int at91_pm_verify_clocks(void)
88 scsr = at91_pmc_read(AT91_PMC_SCSR);
90 /* USB must not be using PLLB */
91 if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
92 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
96 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
97 for (i = 0; i < 4; i++) {
100 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
103 css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
104 if (css != AT91_PMC_CSS_SLOW) {
105 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
114 * Call this from platform driver suspend() to see how deeply to suspend.
115 * For example, some controllers (like OHCI) need one of the PLL clocks
116 * in order to act as a wakeup source, and those are not available when
117 * going into slow clock mode.
119 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
120 * the very same problem (but not using at91 main_clk), and it'd be better
121 * to add one generic API rather than lots of platform-specific ones.
123 int at91_suspend_entering_slow_clock(void)
125 return (target_state == PM_SUSPEND_MEM);
127 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
129 static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
130 void __iomem *ramc1, int memctrl);
132 extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
133 void __iomem *ramc1, int memctrl);
134 extern u32 at91_pm_suspend_in_sram_sz;
136 static void at91_pm_suspend(suspend_state_t state)
138 unsigned int pm_data = at91_pm_data.memctrl;
140 pm_data |= (state == PM_SUSPEND_MEM) ?
141 AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
146 at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
147 at91_ramc_base[1], pm_data);
152 static int at91_pm_enter(suspend_state_t state)
154 at91_pinctrl_gpio_suspend();
158 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
159 * drivers must suspend more deeply, the master clock switches
160 * to the clk32k and turns off the main oscillator
164 * Ensure that clocks are in a valid state.
166 if (!at91_pm_verify_clocks())
169 at91_pm_suspend(state);
174 * STANDBY mode has *all* drivers suspended; ignores irqs not
175 * marked as 'wakeup' event sources; and reduces DRAM power.
176 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
177 * nothing fancy done with main or cpu clocks.
179 case PM_SUSPEND_STANDBY:
180 at91_pm_suspend(state);
188 pr_debug("AT91: PM - bogus suspend state %d\n", state);
193 target_state = PM_SUSPEND_ON;
195 at91_pinctrl_gpio_resume();
200 * Called right prior to thawing processes.
202 static void at91_pm_end(void)
204 target_state = PM_SUSPEND_ON;
208 static const struct platform_suspend_ops at91_pm_ops = {
209 .valid = at91_pm_valid_state,
210 .begin = at91_pm_begin,
211 .enter = at91_pm_enter,
215 static struct platform_device at91_cpuidle_device = {
216 .name = "cpuidle-at91",
219 static void at91_pm_set_standby(void (*at91_standby)(void))
222 at91_cpuidle_device.dev.platform_data = at91_standby;
226 * The AT91RM9200 goes into self-refresh mode with this command, and will
227 * terminate self-refresh automatically on the next SDRAM access.
229 * Self-refresh mode is exited as soon as a memory access is made, but we don't
230 * know for sure when that happens. However, we need to restore the low-power
231 * mode if it was enabled before going idle. Restoring low-power mode while
232 * still in self-refresh is "not recommended", but seems to work.
234 static void at91rm9200_standby(void)
236 u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
241 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
242 " str %0, [%1, %2]\n\t"
243 " str %3, [%1, %4]\n\t"
244 " mcr p15, 0, %0, c7, c0, 4\n\t"
247 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
248 "r" (1), "r" (AT91_MC_SDRAMC_SRR),
252 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
255 static void at91_ddr_standby(void)
257 /* Those two values allow us to delay self-refresh activation
260 u32 saved_lpr0, saved_lpr1 = 0;
262 if (at91_ramc_base[1]) {
263 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
264 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
265 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
268 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
269 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
270 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
272 /* self-refresh mode now */
273 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
274 if (at91_ramc_base[1])
275 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
279 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
280 if (at91_ramc_base[1])
281 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
284 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
287 static void at91sam9_sdram_standby(void)
290 u32 saved_lpr0, saved_lpr1 = 0;
292 if (at91_ramc_base[1]) {
293 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
294 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
295 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
298 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
299 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
300 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
302 /* self-refresh mode now */
303 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
304 if (at91_ramc_base[1])
305 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
309 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
310 if (at91_ramc_base[1])
311 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
314 static const struct of_device_id const ramc_ids[] __initconst = {
315 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
316 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
317 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
318 { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
322 static __init void at91_dt_ramc(void)
324 struct device_node *np;
325 const struct of_device_id *of_id;
327 const void *standby = NULL;
329 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
330 at91_ramc_base[idx] = of_iomap(np, 0);
331 if (!at91_ramc_base[idx])
332 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
335 standby = of_id->data;
341 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
344 pr_warn("ramc no standby function available\n");
348 at91_pm_set_standby(standby);
351 static void __init at91_pm_sram_init(void)
353 struct gen_pool *sram_pool;
354 phys_addr_t sram_pbase;
355 unsigned long sram_base;
356 struct device_node *node;
357 struct platform_device *pdev = NULL;
359 for_each_compatible_node(node, NULL, "mmio-sram") {
360 pdev = of_find_device_by_node(node);
368 pr_warn("%s: failed to find sram device!\n", __func__);
372 sram_pool = gen_pool_get(&pdev->dev, NULL);
374 pr_warn("%s: sram pool unavailable!\n", __func__);
378 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
380 pr_warn("%s: unable to alloc sram!\n", __func__);
384 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
385 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
386 at91_pm_suspend_in_sram_sz, false);
387 if (!at91_suspend_sram_fn) {
388 pr_warn("SRAM: Could not map\n");
392 /* Copy the pm suspend handler to SRAM */
393 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
394 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
397 static void __init at91_pm_init(void)
401 if (at91_cpuidle_device.dev.platform_data)
402 platform_device_register(&at91_cpuidle_device);
404 if (at91_suspend_sram_fn)
405 suspend_set_ops(&at91_pm_ops);
407 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
410 void __init at91rm9200_pm_init(void)
415 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
417 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
419 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
420 at91_pm_data.memctrl = AT91_MEMCTRL_MC;
425 void __init at91sam9260_pm_init(void)
428 at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
429 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
430 return at91_pm_init();
433 void __init at91sam9g45_pm_init(void)
436 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
437 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
438 return at91_pm_init();
441 void __init at91sam9x5_pm_init(void)
444 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
445 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
446 return at91_pm_init();