2 * On-Chip devices setup code for the AT91SAM9G45 family
4 * Copyright (C) 2009 Atmel Corporation.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/gpio.h>
17 #include <linux/clk.h>
18 #include <linux/platform_device.h>
19 #include <linux/i2c-gpio.h>
20 #include <linux/atmel-mci.h>
21 #include <linux/platform_data/atmel-aes.h>
23 #include <linux/platform_data/at91_adc.h>
26 #include <video/atmel_lcdc.h>
28 #include <mach/at91_adc.h>
29 #include <mach/board.h>
30 #include <mach/at91sam9g45.h>
31 #include <mach/at91sam9g45_matrix.h>
32 #include <mach/at91_matrix.h>
33 #include <mach/at91sam9_smc.h>
34 #include <mach/at_hdmac.h>
35 #include <mach/atmel-mci.h>
37 #include <media/atmel-isi.h>
43 /* --------------------------------------------------------------------
44 * HDMAC - AHB DMA Controller
45 * -------------------------------------------------------------------- */
47 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
48 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
50 static struct resource hdmac_resources[] = {
52 .start = AT91SAM9G45_BASE_DMA,
53 .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
54 .flags = IORESOURCE_MEM,
57 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
58 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
59 .flags = IORESOURCE_IRQ,
63 static struct platform_device at_hdmac_device = {
64 .name = "at91sam9g45_dma",
67 .dma_mask = &hdmac_dmamask,
68 .coherent_dma_mask = DMA_BIT_MASK(32),
70 .resource = hdmac_resources,
71 .num_resources = ARRAY_SIZE(hdmac_resources),
74 void __init at91_add_device_hdmac(void)
76 platform_device_register(&at_hdmac_device);
79 void __init at91_add_device_hdmac(void) {}
83 /* --------------------------------------------------------------------
85 * -------------------------------------------------------------------- */
87 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
88 static u64 ohci_dmamask = DMA_BIT_MASK(32);
89 static struct at91_usbh_data usbh_ohci_data;
91 static struct resource usbh_ohci_resources[] = {
93 .start = AT91SAM9G45_OHCI_BASE,
94 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
95 .flags = IORESOURCE_MEM,
98 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
99 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
100 .flags = IORESOURCE_IRQ,
104 static struct platform_device at91_usbh_ohci_device = {
108 .dma_mask = &ohci_dmamask,
109 .coherent_dma_mask = DMA_BIT_MASK(32),
110 .platform_data = &usbh_ohci_data,
112 .resource = usbh_ohci_resources,
113 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
116 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
123 /* Enable VBus control for UHP ports */
124 for (i = 0; i < data->ports; i++) {
125 if (gpio_is_valid(data->vbus_pin[i]))
126 at91_set_gpio_output(data->vbus_pin[i],
127 data->vbus_pin_active_low[i]);
130 /* Enable overcurrent notification */
131 for (i = 0; i < data->ports; i++) {
132 if (gpio_is_valid(data->overcurrent_pin[i]))
133 at91_set_gpio_input(data->overcurrent_pin[i], 1);
136 usbh_ohci_data = *data;
137 platform_device_register(&at91_usbh_ohci_device);
140 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
144 /* --------------------------------------------------------------------
146 * Needs an OHCI host for low and full speed management
147 * -------------------------------------------------------------------- */
149 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
150 static u64 ehci_dmamask = DMA_BIT_MASK(32);
151 static struct at91_usbh_data usbh_ehci_data;
153 static struct resource usbh_ehci_resources[] = {
155 .start = AT91SAM9G45_EHCI_BASE,
156 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
157 .flags = IORESOURCE_MEM,
160 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
161 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
162 .flags = IORESOURCE_IRQ,
166 static struct platform_device at91_usbh_ehci_device = {
167 .name = "atmel-ehci",
170 .dma_mask = &ehci_dmamask,
171 .coherent_dma_mask = DMA_BIT_MASK(32),
172 .platform_data = &usbh_ehci_data,
174 .resource = usbh_ehci_resources,
175 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
178 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
185 /* Enable VBus control for UHP ports */
186 for (i = 0; i < data->ports; i++) {
187 if (gpio_is_valid(data->vbus_pin[i]))
188 at91_set_gpio_output(data->vbus_pin[i],
189 data->vbus_pin_active_low[i]);
192 usbh_ehci_data = *data;
193 platform_device_register(&at91_usbh_ehci_device);
196 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
200 /* --------------------------------------------------------------------
201 * USB HS Device (Gadget)
202 * -------------------------------------------------------------------- */
204 #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE)
205 static struct resource usba_udc_resources[] = {
207 .start = AT91SAM9G45_UDPHS_FIFO,
208 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
209 .flags = IORESOURCE_MEM,
212 .start = AT91SAM9G45_BASE_UDPHS,
213 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
214 .flags = IORESOURCE_MEM,
217 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
218 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
219 .flags = IORESOURCE_IRQ,
223 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
227 .fifo_size = maxpkt, \
233 static struct usba_ep_data usba_udc_ep[] __initdata = {
234 EP("ep0", 0, 64, 1, 0, 0),
235 EP("ep1", 1, 1024, 2, 1, 1),
236 EP("ep2", 2, 1024, 2, 1, 1),
237 EP("ep3", 3, 1024, 3, 1, 0),
238 EP("ep4", 4, 1024, 3, 1, 0),
239 EP("ep5", 5, 1024, 3, 1, 1),
240 EP("ep6", 6, 1024, 3, 1, 1),
246 * pdata doesn't have room for any endpoints, so we need to
247 * append room for the ones we need right after it.
250 struct usba_platform_data pdata;
251 struct usba_ep_data ep[7];
254 static struct platform_device at91_usba_udc_device = {
255 .name = "atmel_usba_udc",
258 .platform_data = &usba_udc_data.pdata,
260 .resource = usba_udc_resources,
261 .num_resources = ARRAY_SIZE(usba_udc_resources),
264 void __init at91_add_device_usba(struct usba_platform_data *data)
266 usba_udc_data.pdata.vbus_pin = -EINVAL;
267 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
268 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
270 if (data && gpio_is_valid(data->vbus_pin)) {
271 at91_set_gpio_input(data->vbus_pin, 0);
272 at91_set_deglitch(data->vbus_pin, 1);
273 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
276 /* Pullup pin is handled internally by USB device peripheral */
278 platform_device_register(&at91_usba_udc_device);
281 void __init at91_add_device_usba(struct usba_platform_data *data) {}
285 /* --------------------------------------------------------------------
287 * -------------------------------------------------------------------- */
289 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
290 static u64 eth_dmamask = DMA_BIT_MASK(32);
291 static struct macb_platform_data eth_data;
293 static struct resource eth_resources[] = {
295 .start = AT91SAM9G45_BASE_EMAC,
296 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
297 .flags = IORESOURCE_MEM,
300 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
301 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
302 .flags = IORESOURCE_IRQ,
306 static struct platform_device at91sam9g45_eth_device = {
310 .dma_mask = ð_dmamask,
311 .coherent_dma_mask = DMA_BIT_MASK(32),
312 .platform_data = ð_data,
314 .resource = eth_resources,
315 .num_resources = ARRAY_SIZE(eth_resources),
318 void __init at91_add_device_eth(struct macb_platform_data *data)
323 if (gpio_is_valid(data->phy_irq_pin)) {
324 at91_set_gpio_input(data->phy_irq_pin, 0);
325 at91_set_deglitch(data->phy_irq_pin, 1);
328 /* Pins used for MII and RMII */
329 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
330 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
331 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
332 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
333 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
334 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
335 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
336 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
337 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
338 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
340 if (!data->is_rmii) {
341 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
342 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
343 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
344 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
345 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
346 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
347 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
348 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
352 platform_device_register(&at91sam9g45_eth_device);
355 void __init at91_add_device_eth(struct macb_platform_data *data) {}
359 /* --------------------------------------------------------------------
361 * -------------------------------------------------------------------- */
363 #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
364 static u64 mmc_dmamask = DMA_BIT_MASK(32);
365 static struct mci_platform_data mmc0_data, mmc1_data;
367 static struct resource mmc0_resources[] = {
369 .start = AT91SAM9G45_BASE_MCI0,
370 .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1,
371 .flags = IORESOURCE_MEM,
374 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
375 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
376 .flags = IORESOURCE_IRQ,
380 static struct platform_device at91sam9g45_mmc0_device = {
384 .dma_mask = &mmc_dmamask,
385 .coherent_dma_mask = DMA_BIT_MASK(32),
386 .platform_data = &mmc0_data,
388 .resource = mmc0_resources,
389 .num_resources = ARRAY_SIZE(mmc0_resources),
392 static struct resource mmc1_resources[] = {
394 .start = AT91SAM9G45_BASE_MCI1,
395 .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1,
396 .flags = IORESOURCE_MEM,
399 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
400 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
401 .flags = IORESOURCE_IRQ,
405 static struct platform_device at91sam9g45_mmc1_device = {
409 .dma_mask = &mmc_dmamask,
410 .coherent_dma_mask = DMA_BIT_MASK(32),
411 .platform_data = &mmc1_data,
413 .resource = mmc1_resources,
414 .num_resources = ARRAY_SIZE(mmc1_resources),
417 /* Consider only one slot : slot 0 */
418 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
424 /* Must have at least one usable slot */
425 if (!data->slot[0].bus_width)
428 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
430 struct at_dma_slave *atslave;
431 struct mci_dma_data *alt_atslave;
433 alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
434 atslave = &alt_atslave->sdata;
436 /* DMA slave channel configuration */
437 atslave->dma_dev = &at_hdmac_device.dev;
438 atslave->cfg = ATC_FIFOCFG_HALFFIFO
439 | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
440 if (mmc_id == 0) /* MCI0 */
441 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
442 | ATC_DST_PER(AT_DMA_ID_MCI0);
445 atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
446 | ATC_DST_PER(AT_DMA_ID_MCI1);
448 data->dma_slave = alt_atslave;
454 if (gpio_is_valid(data->slot[0].detect_pin)) {
455 at91_set_gpio_input(data->slot[0].detect_pin, 1);
456 at91_set_deglitch(data->slot[0].detect_pin, 1);
458 if (gpio_is_valid(data->slot[0].wp_pin))
459 at91_set_gpio_input(data->slot[0].wp_pin, 1);
461 if (mmc_id == 0) { /* MCI0 */
464 at91_set_A_periph(AT91_PIN_PA0, 0);
467 at91_set_A_periph(AT91_PIN_PA1, 1);
469 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
470 at91_set_A_periph(AT91_PIN_PA2, 1);
471 if (data->slot[0].bus_width == 4) {
472 at91_set_A_periph(AT91_PIN_PA3, 1);
473 at91_set_A_periph(AT91_PIN_PA4, 1);
474 at91_set_A_periph(AT91_PIN_PA5, 1);
475 if (data->slot[0].bus_width == 8) {
476 at91_set_A_periph(AT91_PIN_PA6, 1);
477 at91_set_A_periph(AT91_PIN_PA7, 1);
478 at91_set_A_periph(AT91_PIN_PA8, 1);
479 at91_set_A_periph(AT91_PIN_PA9, 1);
484 platform_device_register(&at91sam9g45_mmc0_device);
489 at91_set_A_periph(AT91_PIN_PA31, 0);
492 at91_set_A_periph(AT91_PIN_PA22, 1);
494 /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
495 at91_set_A_periph(AT91_PIN_PA23, 1);
496 if (data->slot[0].bus_width == 4) {
497 at91_set_A_periph(AT91_PIN_PA24, 1);
498 at91_set_A_periph(AT91_PIN_PA25, 1);
499 at91_set_A_periph(AT91_PIN_PA26, 1);
500 if (data->slot[0].bus_width == 8) {
501 at91_set_A_periph(AT91_PIN_PA27, 1);
502 at91_set_A_periph(AT91_PIN_PA28, 1);
503 at91_set_A_periph(AT91_PIN_PA29, 1);
504 at91_set_A_periph(AT91_PIN_PA30, 1);
509 platform_device_register(&at91sam9g45_mmc1_device);
514 void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
518 /* --------------------------------------------------------------------
520 * -------------------------------------------------------------------- */
522 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
523 static struct atmel_nand_data nand_data;
525 #define NAND_BASE AT91_CHIPSELECT_3
527 static struct resource nand_resources[] = {
530 .end = NAND_BASE + SZ_256M - 1,
531 .flags = IORESOURCE_MEM,
534 .start = AT91SAM9G45_BASE_ECC,
535 .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
536 .flags = IORESOURCE_MEM,
540 static struct platform_device at91sam9g45_nand_device = {
541 .name = "atmel_nand",
544 .platform_data = &nand_data,
546 .resource = nand_resources,
547 .num_resources = ARRAY_SIZE(nand_resources),
550 void __init at91_add_device_nand(struct atmel_nand_data *data)
557 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
558 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
561 if (gpio_is_valid(data->enable_pin))
562 at91_set_gpio_output(data->enable_pin, 1);
565 if (gpio_is_valid(data->rdy_pin))
566 at91_set_gpio_input(data->rdy_pin, 1);
568 /* card detect pin */
569 if (gpio_is_valid(data->det_pin))
570 at91_set_gpio_input(data->det_pin, 1);
573 platform_device_register(&at91sam9g45_nand_device);
576 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
580 /* --------------------------------------------------------------------
582 * -------------------------------------------------------------------- */
585 * Prefer the GPIO code since the TWI controller isn't robust
586 * (gets overruns and underruns under load) and can only issue
587 * repeated STARTs in one scenario (the driver doesn't yet handle them).
589 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
590 static struct i2c_gpio_platform_data pdata_i2c0 = {
591 .sda_pin = AT91_PIN_PA20,
592 .sda_is_open_drain = 1,
593 .scl_pin = AT91_PIN_PA21,
594 .scl_is_open_drain = 1,
595 .udelay = 5, /* ~100 kHz */
598 static struct platform_device at91sam9g45_twi0_device = {
601 .dev.platform_data = &pdata_i2c0,
604 static struct i2c_gpio_platform_data pdata_i2c1 = {
605 .sda_pin = AT91_PIN_PB10,
606 .sda_is_open_drain = 1,
607 .scl_pin = AT91_PIN_PB11,
608 .scl_is_open_drain = 1,
609 .udelay = 5, /* ~100 kHz */
612 static struct platform_device at91sam9g45_twi1_device = {
615 .dev.platform_data = &pdata_i2c1,
618 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
620 i2c_register_board_info(i2c_id, devices, nr_devices);
623 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
624 at91_set_multi_drive(AT91_PIN_PA20, 1);
626 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
627 at91_set_multi_drive(AT91_PIN_PA21, 1);
629 platform_device_register(&at91sam9g45_twi0_device);
631 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
632 at91_set_multi_drive(AT91_PIN_PB10, 1);
634 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
635 at91_set_multi_drive(AT91_PIN_PB11, 1);
637 platform_device_register(&at91sam9g45_twi1_device);
641 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
642 static struct resource twi0_resources[] = {
644 .start = AT91SAM9G45_BASE_TWI0,
645 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
646 .flags = IORESOURCE_MEM,
649 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
650 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
651 .flags = IORESOURCE_IRQ,
655 static struct platform_device at91sam9g45_twi0_device = {
658 .resource = twi0_resources,
659 .num_resources = ARRAY_SIZE(twi0_resources),
662 static struct resource twi1_resources[] = {
664 .start = AT91SAM9G45_BASE_TWI1,
665 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
666 .flags = IORESOURCE_MEM,
669 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
670 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
671 .flags = IORESOURCE_IRQ,
675 static struct platform_device at91sam9g45_twi1_device = {
678 .resource = twi1_resources,
679 .num_resources = ARRAY_SIZE(twi1_resources),
682 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
684 i2c_register_board_info(i2c_id, devices, nr_devices);
686 /* pins used for TWI interface */
688 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
689 at91_set_multi_drive(AT91_PIN_PA20, 1);
691 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
692 at91_set_multi_drive(AT91_PIN_PA21, 1);
694 platform_device_register(&at91sam9g45_twi0_device);
696 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
697 at91_set_multi_drive(AT91_PIN_PB10, 1);
699 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
700 at91_set_multi_drive(AT91_PIN_PB11, 1);
702 platform_device_register(&at91sam9g45_twi1_device);
706 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
710 /* --------------------------------------------------------------------
712 * -------------------------------------------------------------------- */
714 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
715 static u64 spi_dmamask = DMA_BIT_MASK(32);
717 static struct resource spi0_resources[] = {
719 .start = AT91SAM9G45_BASE_SPI0,
720 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
721 .flags = IORESOURCE_MEM,
724 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
725 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
726 .flags = IORESOURCE_IRQ,
730 static struct platform_device at91sam9g45_spi0_device = {
734 .dma_mask = &spi_dmamask,
735 .coherent_dma_mask = DMA_BIT_MASK(32),
737 .resource = spi0_resources,
738 .num_resources = ARRAY_SIZE(spi0_resources),
741 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
743 static struct resource spi1_resources[] = {
745 .start = AT91SAM9G45_BASE_SPI1,
746 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
747 .flags = IORESOURCE_MEM,
750 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
751 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
752 .flags = IORESOURCE_IRQ,
756 static struct platform_device at91sam9g45_spi1_device = {
760 .dma_mask = &spi_dmamask,
761 .coherent_dma_mask = DMA_BIT_MASK(32),
763 .resource = spi1_resources,
764 .num_resources = ARRAY_SIZE(spi1_resources),
767 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
769 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
772 unsigned long cs_pin;
773 short enable_spi0 = 0;
774 short enable_spi1 = 0;
776 /* Choose SPI chip-selects */
777 for (i = 0; i < nr_devices; i++) {
778 if (devices[i].controller_data)
779 cs_pin = (unsigned long) devices[i].controller_data;
780 else if (devices[i].bus_num == 0)
781 cs_pin = spi0_standard_cs[devices[i].chip_select];
783 cs_pin = spi1_standard_cs[devices[i].chip_select];
785 if (!gpio_is_valid(cs_pin))
788 if (devices[i].bus_num == 0)
793 /* enable chip-select pin */
794 at91_set_gpio_output(cs_pin, 1);
796 /* pass chip-select pin to driver */
797 devices[i].controller_data = (void *) cs_pin;
800 spi_register_board_info(devices, nr_devices);
802 /* Configure SPI bus(es) */
804 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
805 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
806 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
808 platform_device_register(&at91sam9g45_spi0_device);
811 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
812 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
813 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
815 platform_device_register(&at91sam9g45_spi1_device);
819 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
823 /* --------------------------------------------------------------------
825 * -------------------------------------------------------------------- */
827 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
828 static u64 ac97_dmamask = DMA_BIT_MASK(32);
829 static struct ac97c_platform_data ac97_data;
831 static struct resource ac97_resources[] = {
833 .start = AT91SAM9G45_BASE_AC97C,
834 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
835 .flags = IORESOURCE_MEM,
838 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
839 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
840 .flags = IORESOURCE_IRQ,
844 static struct platform_device at91sam9g45_ac97_device = {
845 .name = "atmel_ac97c",
848 .dma_mask = &ac97_dmamask,
849 .coherent_dma_mask = DMA_BIT_MASK(32),
850 .platform_data = &ac97_data,
852 .resource = ac97_resources,
853 .num_resources = ARRAY_SIZE(ac97_resources),
856 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
861 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
862 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
863 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
864 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
867 if (gpio_is_valid(data->reset_pin))
868 at91_set_gpio_output(data->reset_pin, 0);
871 platform_device_register(&at91sam9g45_ac97_device);
874 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
877 /* --------------------------------------------------------------------
878 * Image Sensor Interface
879 * -------------------------------------------------------------------- */
880 #if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE)
881 static u64 isi_dmamask = DMA_BIT_MASK(32);
882 static struct isi_platform_data isi_data;
884 struct resource isi_resources[] = {
886 .start = AT91SAM9G45_BASE_ISI,
887 .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1,
888 .flags = IORESOURCE_MEM,
891 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
892 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
893 .flags = IORESOURCE_IRQ,
897 static struct platform_device at91sam9g45_isi_device = {
901 .dma_mask = &isi_dmamask,
902 .coherent_dma_mask = DMA_BIT_MASK(32),
903 .platform_data = &isi_data,
905 .resource = isi_resources,
906 .num_resources = ARRAY_SIZE(isi_resources),
909 static struct clk_lookup isi_mck_lookups[] = {
910 CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL),
913 void __init at91_add_device_isi(struct isi_platform_data *data,
923 at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */
924 at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */
925 at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
926 at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */
927 at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */
928 at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */
929 at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */
930 at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */
931 at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */
932 at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */
933 at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */
934 at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */
935 at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */
936 at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */
937 at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */
939 platform_device_register(&at91sam9g45_isi_device);
941 if (use_pck_as_mck) {
942 at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */
944 pck = clk_get(NULL, "pck1");
945 parent = clk_get(NULL, "plla");
947 BUG_ON(IS_ERR(pck) || IS_ERR(parent));
949 if (clk_set_parent(pck, parent)) {
950 pr_err("Failed to set PCK's parent\n");
952 /* Register PCK as ISI_MCK */
953 isi_mck_lookups[0].clk = pck;
954 clkdev_add_table(isi_mck_lookups,
955 ARRAY_SIZE(isi_mck_lookups));
963 void __init at91_add_device_isi(struct isi_platform_data *data,
964 bool use_pck_as_mck) {}
968 /* --------------------------------------------------------------------
970 * -------------------------------------------------------------------- */
972 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
973 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
974 static struct atmel_lcdfb_info lcdc_data;
976 static struct resource lcdc_resources[] = {
978 .start = AT91SAM9G45_LCDC_BASE,
979 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
980 .flags = IORESOURCE_MEM,
983 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
984 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
985 .flags = IORESOURCE_IRQ,
989 static struct platform_device at91_lcdc_device = {
990 .name = "atmel_lcdfb",
993 .dma_mask = &lcdc_dmamask,
994 .coherent_dma_mask = DMA_BIT_MASK(32),
995 .platform_data = &lcdc_data,
997 .resource = lcdc_resources,
998 .num_resources = ARRAY_SIZE(lcdc_resources),
1001 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
1006 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
1008 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
1009 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
1010 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
1011 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
1012 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
1013 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
1014 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
1015 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
1016 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
1017 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
1018 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
1019 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
1020 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
1021 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
1022 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
1023 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
1024 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
1025 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
1026 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
1027 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
1028 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
1029 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
1030 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
1031 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
1032 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
1033 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
1034 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
1035 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
1036 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
1039 platform_device_register(&at91_lcdc_device);
1042 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
1046 /* --------------------------------------------------------------------
1047 * Timer/Counter block
1048 * -------------------------------------------------------------------- */
1050 #ifdef CONFIG_ATMEL_TCLIB
1051 static struct resource tcb0_resources[] = {
1053 .start = AT91SAM9G45_BASE_TCB0,
1054 .end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1,
1055 .flags = IORESOURCE_MEM,
1058 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1059 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1060 .flags = IORESOURCE_IRQ,
1064 static struct platform_device at91sam9g45_tcb0_device = {
1065 .name = "atmel_tcb",
1067 .resource = tcb0_resources,
1068 .num_resources = ARRAY_SIZE(tcb0_resources),
1071 /* TCB1 begins with TC3 */
1072 static struct resource tcb1_resources[] = {
1074 .start = AT91SAM9G45_BASE_TCB1,
1075 .end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1,
1076 .flags = IORESOURCE_MEM,
1079 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1080 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
1081 .flags = IORESOURCE_IRQ,
1085 static struct platform_device at91sam9g45_tcb1_device = {
1086 .name = "atmel_tcb",
1088 .resource = tcb1_resources,
1089 .num_resources = ARRAY_SIZE(tcb1_resources),
1092 static void __init at91_add_device_tc(void)
1094 platform_device_register(&at91sam9g45_tcb0_device);
1095 platform_device_register(&at91sam9g45_tcb1_device);
1098 static void __init at91_add_device_tc(void) { }
1102 /* --------------------------------------------------------------------
1104 * -------------------------------------------------------------------- */
1106 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
1107 static struct resource rtc_resources[] = {
1109 .start = AT91SAM9G45_BASE_RTC,
1110 .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
1111 .flags = IORESOURCE_MEM,
1114 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1115 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1116 .flags = IORESOURCE_IRQ,
1120 static struct platform_device at91sam9g45_rtc_device = {
1123 .resource = rtc_resources,
1124 .num_resources = ARRAY_SIZE(rtc_resources),
1127 static void __init at91_add_device_rtc(void)
1129 platform_device_register(&at91sam9g45_rtc_device);
1132 static void __init at91_add_device_rtc(void) {}
1136 /* --------------------------------------------------------------------
1138 * -------------------------------------------------------------------- */
1140 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
1141 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
1142 static struct at91_tsadcc_data tsadcc_data;
1144 static struct resource tsadcc_resources[] = {
1146 .start = AT91SAM9G45_BASE_TSC,
1147 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1148 .flags = IORESOURCE_MEM,
1151 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1152 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1153 .flags = IORESOURCE_IRQ,
1157 static struct platform_device at91sam9g45_tsadcc_device = {
1158 .name = "atmel_tsadcc",
1161 .dma_mask = &tsadcc_dmamask,
1162 .coherent_dma_mask = DMA_BIT_MASK(32),
1163 .platform_data = &tsadcc_data,
1165 .resource = tsadcc_resources,
1166 .num_resources = ARRAY_SIZE(tsadcc_resources),
1169 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
1174 at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
1175 at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
1176 at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
1177 at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
1179 tsadcc_data = *data;
1180 platform_device_register(&at91sam9g45_tsadcc_device);
1183 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
1187 /* --------------------------------------------------------------------
1189 * -------------------------------------------------------------------- */
1191 #if IS_ENABLED(CONFIG_AT91_ADC)
1192 static struct at91_adc_data adc_data;
1194 static struct resource adc_resources[] = {
1196 .start = AT91SAM9G45_BASE_TSC,
1197 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
1198 .flags = IORESOURCE_MEM,
1201 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1202 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
1203 .flags = IORESOURCE_IRQ,
1207 static struct platform_device at91_adc_device = {
1211 .platform_data = &adc_data,
1213 .resource = adc_resources,
1214 .num_resources = ARRAY_SIZE(adc_resources),
1217 static struct at91_adc_trigger at91_adc_triggers[] = {
1219 .name = "external-rising",
1221 .is_external = true,
1224 .name = "external-falling",
1226 .is_external = true,
1229 .name = "external-any",
1231 .is_external = true,
1234 .name = "continuous",
1236 .is_external = false,
1240 static struct at91_adc_reg_desc at91_adc_register_g45 = {
1241 .channel_base = AT91_ADC_CHR(0),
1242 .drdy_mask = AT91_ADC_DRDY,
1243 .status_register = AT91_ADC_SR,
1244 .trigger_register = 0x08,
1247 void __init at91_add_device_adc(struct at91_adc_data *data)
1252 if (test_bit(0, &data->channels_used))
1253 at91_set_gpio_input(AT91_PIN_PD20, 0);
1254 if (test_bit(1, &data->channels_used))
1255 at91_set_gpio_input(AT91_PIN_PD21, 0);
1256 if (test_bit(2, &data->channels_used))
1257 at91_set_gpio_input(AT91_PIN_PD22, 0);
1258 if (test_bit(3, &data->channels_used))
1259 at91_set_gpio_input(AT91_PIN_PD23, 0);
1260 if (test_bit(4, &data->channels_used))
1261 at91_set_gpio_input(AT91_PIN_PD24, 0);
1262 if (test_bit(5, &data->channels_used))
1263 at91_set_gpio_input(AT91_PIN_PD25, 0);
1264 if (test_bit(6, &data->channels_used))
1265 at91_set_gpio_input(AT91_PIN_PD26, 0);
1266 if (test_bit(7, &data->channels_used))
1267 at91_set_gpio_input(AT91_PIN_PD27, 0);
1269 if (data->use_external_triggers)
1270 at91_set_A_periph(AT91_PIN_PD28, 0);
1272 data->num_channels = 8;
1273 data->startup_time = 40;
1274 data->registers = &at91_adc_register_g45;
1275 data->trigger_number = 4;
1276 data->trigger_list = at91_adc_triggers;
1279 platform_device_register(&at91_adc_device);
1282 void __init at91_add_device_adc(struct at91_adc_data *data) {}
1285 /* --------------------------------------------------------------------
1287 * -------------------------------------------------------------------- */
1289 static struct resource rtt_resources[] = {
1291 .start = AT91SAM9G45_BASE_RTT,
1292 .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
1293 .flags = IORESOURCE_MEM,
1295 .flags = IORESOURCE_MEM,
1299 static struct platform_device at91sam9g45_rtt_device = {
1302 .resource = rtt_resources,
1305 #if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
1306 static void __init at91_add_device_rtt_rtc(void)
1308 at91sam9g45_rtt_device.name = "rtc-at91sam9";
1310 * The second resource is needed:
1311 * GPBR will serve as the storage for RTC time offset
1313 at91sam9g45_rtt_device.num_resources = 2;
1314 rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
1315 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1316 rtt_resources[1].end = rtt_resources[1].start + 3;
1319 static void __init at91_add_device_rtt_rtc(void)
1321 /* Only one resource is needed: RTT not used as RTC */
1322 at91sam9g45_rtt_device.num_resources = 1;
1326 static void __init at91_add_device_rtt(void)
1328 at91_add_device_rtt_rtc();
1329 platform_device_register(&at91sam9g45_rtt_device);
1333 /* --------------------------------------------------------------------
1335 * -------------------------------------------------------------------- */
1337 #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE)
1338 static struct resource trng_resources[] = {
1340 .start = AT91SAM9G45_BASE_TRNG,
1341 .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1,
1342 .flags = IORESOURCE_MEM,
1346 static struct platform_device at91sam9g45_trng_device = {
1347 .name = "atmel-trng",
1349 .resource = trng_resources,
1350 .num_resources = ARRAY_SIZE(trng_resources),
1353 static void __init at91_add_device_trng(void)
1355 platform_device_register(&at91sam9g45_trng_device);
1358 static void __init at91_add_device_trng(void) {}
1361 /* --------------------------------------------------------------------
1363 * -------------------------------------------------------------------- */
1365 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
1366 static struct resource wdt_resources[] = {
1368 .start = AT91SAM9G45_BASE_WDT,
1369 .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
1370 .flags = IORESOURCE_MEM,
1374 static struct platform_device at91sam9g45_wdt_device = {
1377 .resource = wdt_resources,
1378 .num_resources = ARRAY_SIZE(wdt_resources),
1381 static void __init at91_add_device_watchdog(void)
1383 platform_device_register(&at91sam9g45_wdt_device);
1386 static void __init at91_add_device_watchdog(void) {}
1390 /* --------------------------------------------------------------------
1392 * --------------------------------------------------------------------*/
1394 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
1395 static u32 pwm_mask;
1397 static struct resource pwm_resources[] = {
1399 .start = AT91SAM9G45_BASE_PWMC,
1400 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
1401 .flags = IORESOURCE_MEM,
1404 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1405 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
1406 .flags = IORESOURCE_IRQ,
1410 static struct platform_device at91sam9g45_pwm0_device = {
1411 .name = "atmel_pwm",
1414 .platform_data = &pwm_mask,
1416 .resource = pwm_resources,
1417 .num_resources = ARRAY_SIZE(pwm_resources),
1420 void __init at91_add_device_pwm(u32 mask)
1422 if (mask & (1 << AT91_PWM0))
1423 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1425 if (mask & (1 << AT91_PWM1))
1426 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1428 if (mask & (1 << AT91_PWM2))
1429 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1431 if (mask & (1 << AT91_PWM3))
1432 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1436 platform_device_register(&at91sam9g45_pwm0_device);
1439 void __init at91_add_device_pwm(u32 mask) {}
1443 /* --------------------------------------------------------------------
1444 * SSC -- Synchronous Serial Controller
1445 * -------------------------------------------------------------------- */
1447 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1448 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1450 static struct resource ssc0_resources[] = {
1452 .start = AT91SAM9G45_BASE_SSC0,
1453 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1454 .flags = IORESOURCE_MEM,
1457 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1458 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
1459 .flags = IORESOURCE_IRQ,
1463 static struct platform_device at91sam9g45_ssc0_device = {
1467 .dma_mask = &ssc0_dmamask,
1468 .coherent_dma_mask = DMA_BIT_MASK(32),
1470 .resource = ssc0_resources,
1471 .num_resources = ARRAY_SIZE(ssc0_resources),
1474 static inline void configure_ssc0_pins(unsigned pins)
1476 if (pins & ATMEL_SSC_TF)
1477 at91_set_A_periph(AT91_PIN_PD1, 1);
1478 if (pins & ATMEL_SSC_TK)
1479 at91_set_A_periph(AT91_PIN_PD0, 1);
1480 if (pins & ATMEL_SSC_TD)
1481 at91_set_A_periph(AT91_PIN_PD2, 1);
1482 if (pins & ATMEL_SSC_RD)
1483 at91_set_A_periph(AT91_PIN_PD3, 1);
1484 if (pins & ATMEL_SSC_RK)
1485 at91_set_A_periph(AT91_PIN_PD4, 1);
1486 if (pins & ATMEL_SSC_RF)
1487 at91_set_A_periph(AT91_PIN_PD5, 1);
1490 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1492 static struct resource ssc1_resources[] = {
1494 .start = AT91SAM9G45_BASE_SSC1,
1495 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1496 .flags = IORESOURCE_MEM,
1499 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1500 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
1501 .flags = IORESOURCE_IRQ,
1505 static struct platform_device at91sam9g45_ssc1_device = {
1509 .dma_mask = &ssc1_dmamask,
1510 .coherent_dma_mask = DMA_BIT_MASK(32),
1512 .resource = ssc1_resources,
1513 .num_resources = ARRAY_SIZE(ssc1_resources),
1516 static inline void configure_ssc1_pins(unsigned pins)
1518 if (pins & ATMEL_SSC_TF)
1519 at91_set_A_periph(AT91_PIN_PD14, 1);
1520 if (pins & ATMEL_SSC_TK)
1521 at91_set_A_periph(AT91_PIN_PD12, 1);
1522 if (pins & ATMEL_SSC_TD)
1523 at91_set_A_periph(AT91_PIN_PD10, 1);
1524 if (pins & ATMEL_SSC_RD)
1525 at91_set_A_periph(AT91_PIN_PD11, 1);
1526 if (pins & ATMEL_SSC_RK)
1527 at91_set_A_periph(AT91_PIN_PD13, 1);
1528 if (pins & ATMEL_SSC_RF)
1529 at91_set_A_periph(AT91_PIN_PD15, 1);
1533 * SSC controllers are accessed through library code, instead of any
1534 * kind of all-singing/all-dancing driver. For example one could be
1535 * used by a particular I2S audio codec's driver, while another one
1536 * on the same system might be used by a custom data capture driver.
1538 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1540 struct platform_device *pdev;
1543 * NOTE: caller is responsible for passing information matching
1544 * "pins" to whatever will be using each particular controller.
1547 case AT91SAM9G45_ID_SSC0:
1548 pdev = &at91sam9g45_ssc0_device;
1549 configure_ssc0_pins(pins);
1551 case AT91SAM9G45_ID_SSC1:
1552 pdev = &at91sam9g45_ssc1_device;
1553 configure_ssc1_pins(pins);
1559 platform_device_register(pdev);
1563 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1567 /* --------------------------------------------------------------------
1569 * -------------------------------------------------------------------- */
1571 #if defined(CONFIG_SERIAL_ATMEL)
1572 static struct resource dbgu_resources[] = {
1574 .start = AT91SAM9G45_BASE_DBGU,
1575 .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
1576 .flags = IORESOURCE_MEM,
1579 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
1580 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
1581 .flags = IORESOURCE_IRQ,
1585 static struct atmel_uart_data dbgu_data = {
1590 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1592 static struct platform_device at91sam9g45_dbgu_device = {
1593 .name = "atmel_usart",
1596 .dma_mask = &dbgu_dmamask,
1597 .coherent_dma_mask = DMA_BIT_MASK(32),
1598 .platform_data = &dbgu_data,
1600 .resource = dbgu_resources,
1601 .num_resources = ARRAY_SIZE(dbgu_resources),
1604 static inline void configure_dbgu_pins(void)
1606 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1607 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1610 static struct resource uart0_resources[] = {
1612 .start = AT91SAM9G45_BASE_US0,
1613 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1614 .flags = IORESOURCE_MEM,
1617 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1618 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
1619 .flags = IORESOURCE_IRQ,
1623 static struct atmel_uart_data uart0_data = {
1628 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1630 static struct platform_device at91sam9g45_uart0_device = {
1631 .name = "atmel_usart",
1634 .dma_mask = &uart0_dmamask,
1635 .coherent_dma_mask = DMA_BIT_MASK(32),
1636 .platform_data = &uart0_data,
1638 .resource = uart0_resources,
1639 .num_resources = ARRAY_SIZE(uart0_resources),
1642 static inline void configure_usart0_pins(unsigned pins)
1644 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1645 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1647 if (pins & ATMEL_UART_RTS)
1648 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1649 if (pins & ATMEL_UART_CTS)
1650 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1653 static struct resource uart1_resources[] = {
1655 .start = AT91SAM9G45_BASE_US1,
1656 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1657 .flags = IORESOURCE_MEM,
1660 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1661 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
1662 .flags = IORESOURCE_IRQ,
1666 static struct atmel_uart_data uart1_data = {
1671 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1673 static struct platform_device at91sam9g45_uart1_device = {
1674 .name = "atmel_usart",
1677 .dma_mask = &uart1_dmamask,
1678 .coherent_dma_mask = DMA_BIT_MASK(32),
1679 .platform_data = &uart1_data,
1681 .resource = uart1_resources,
1682 .num_resources = ARRAY_SIZE(uart1_resources),
1685 static inline void configure_usart1_pins(unsigned pins)
1687 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1688 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1690 if (pins & ATMEL_UART_RTS)
1691 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1692 if (pins & ATMEL_UART_CTS)
1693 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1696 static struct resource uart2_resources[] = {
1698 .start = AT91SAM9G45_BASE_US2,
1699 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1700 .flags = IORESOURCE_MEM,
1703 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1704 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
1705 .flags = IORESOURCE_IRQ,
1709 static struct atmel_uart_data uart2_data = {
1714 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1716 static struct platform_device at91sam9g45_uart2_device = {
1717 .name = "atmel_usart",
1720 .dma_mask = &uart2_dmamask,
1721 .coherent_dma_mask = DMA_BIT_MASK(32),
1722 .platform_data = &uart2_data,
1724 .resource = uart2_resources,
1725 .num_resources = ARRAY_SIZE(uart2_resources),
1728 static inline void configure_usart2_pins(unsigned pins)
1730 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1731 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1733 if (pins & ATMEL_UART_RTS)
1734 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1735 if (pins & ATMEL_UART_CTS)
1736 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1739 static struct resource uart3_resources[] = {
1741 .start = AT91SAM9G45_BASE_US3,
1742 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1743 .flags = IORESOURCE_MEM,
1746 .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1747 .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
1748 .flags = IORESOURCE_IRQ,
1752 static struct atmel_uart_data uart3_data = {
1757 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1759 static struct platform_device at91sam9g45_uart3_device = {
1760 .name = "atmel_usart",
1763 .dma_mask = &uart3_dmamask,
1764 .coherent_dma_mask = DMA_BIT_MASK(32),
1765 .platform_data = &uart3_data,
1767 .resource = uart3_resources,
1768 .num_resources = ARRAY_SIZE(uart3_resources),
1771 static inline void configure_usart3_pins(unsigned pins)
1773 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1774 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1776 if (pins & ATMEL_UART_RTS)
1777 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1778 if (pins & ATMEL_UART_CTS)
1779 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1782 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1784 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1786 struct platform_device *pdev;
1787 struct atmel_uart_data *pdata;
1791 pdev = &at91sam9g45_dbgu_device;
1792 configure_dbgu_pins();
1794 case AT91SAM9G45_ID_US0:
1795 pdev = &at91sam9g45_uart0_device;
1796 configure_usart0_pins(pins);
1798 case AT91SAM9G45_ID_US1:
1799 pdev = &at91sam9g45_uart1_device;
1800 configure_usart1_pins(pins);
1802 case AT91SAM9G45_ID_US2:
1803 pdev = &at91sam9g45_uart2_device;
1804 configure_usart2_pins(pins);
1806 case AT91SAM9G45_ID_US3:
1807 pdev = &at91sam9g45_uart3_device;
1808 configure_usart3_pins(pins);
1813 pdata = pdev->dev.platform_data;
1814 pdata->num = portnr; /* update to mapped ID */
1816 if (portnr < ATMEL_MAX_UART)
1817 at91_uarts[portnr] = pdev;
1820 void __init at91_add_device_serial(void)
1824 for (i = 0; i < ATMEL_MAX_UART; i++) {
1826 platform_device_register(at91_uarts[i]);
1830 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1831 void __init at91_add_device_serial(void) {}
1834 /* --------------------------------------------------------------------
1836 * -------------------------------------------------------------------- */
1838 #if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
1839 static struct resource sha_resources[] = {
1841 .start = AT91SAM9G45_BASE_SHA,
1842 .end = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
1843 .flags = IORESOURCE_MEM,
1846 .start = AT91SAM9G45_ID_AESTDESSHA,
1847 .end = AT91SAM9G45_ID_AESTDESSHA,
1848 .flags = IORESOURCE_IRQ,
1852 static struct platform_device at91sam9g45_sha_device = {
1853 .name = "atmel_sha",
1855 .resource = sha_resources,
1856 .num_resources = ARRAY_SIZE(sha_resources),
1859 static void __init at91_add_device_sha(void)
1861 platform_device_register(&at91sam9g45_sha_device);
1864 static void __init at91_add_device_sha(void) {}
1867 /* --------------------------------------------------------------------
1869 * -------------------------------------------------------------------- */
1871 #if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
1872 static struct resource tdes_resources[] = {
1874 .start = AT91SAM9G45_BASE_TDES,
1875 .end = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
1876 .flags = IORESOURCE_MEM,
1879 .start = AT91SAM9G45_ID_AESTDESSHA,
1880 .end = AT91SAM9G45_ID_AESTDESSHA,
1881 .flags = IORESOURCE_IRQ,
1885 static struct platform_device at91sam9g45_tdes_device = {
1886 .name = "atmel_tdes",
1888 .resource = tdes_resources,
1889 .num_resources = ARRAY_SIZE(tdes_resources),
1892 static void __init at91_add_device_tdes(void)
1894 platform_device_register(&at91sam9g45_tdes_device);
1897 static void __init at91_add_device_tdes(void) {}
1900 /* --------------------------------------------------------------------
1902 * -------------------------------------------------------------------- */
1904 #if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
1905 static struct aes_platform_data aes_data;
1906 static u64 aes_dmamask = DMA_BIT_MASK(32);
1908 static struct resource aes_resources[] = {
1910 .start = AT91SAM9G45_BASE_AES,
1911 .end = AT91SAM9G45_BASE_AES + SZ_16K - 1,
1912 .flags = IORESOURCE_MEM,
1915 .start = AT91SAM9G45_ID_AESTDESSHA,
1916 .end = AT91SAM9G45_ID_AESTDESSHA,
1917 .flags = IORESOURCE_IRQ,
1921 static struct platform_device at91sam9g45_aes_device = {
1922 .name = "atmel_aes",
1925 .dma_mask = &aes_dmamask,
1926 .coherent_dma_mask = DMA_BIT_MASK(32),
1927 .platform_data = &aes_data,
1929 .resource = aes_resources,
1930 .num_resources = ARRAY_SIZE(aes_resources),
1933 static void __init at91_add_device_aes(void)
1935 struct at_dma_slave *atslave;
1936 struct aes_dma_data *alt_atslave;
1938 alt_atslave = kzalloc(sizeof(struct aes_dma_data), GFP_KERNEL);
1940 /* DMA TX slave channel configuration */
1941 atslave = &alt_atslave->txdata;
1942 atslave->dma_dev = &at_hdmac_device.dev;
1943 atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_SRC_H2SEL_HW |
1944 ATC_SRC_PER(AT_DMA_ID_AES_RX);
1946 /* DMA RX slave channel configuration */
1947 atslave = &alt_atslave->rxdata;
1948 atslave->dma_dev = &at_hdmac_device.dev;
1949 atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE | ATC_DST_H2SEL_HW |
1950 ATC_DST_PER(AT_DMA_ID_AES_TX);
1952 aes_data.dma_slave = alt_atslave;
1953 platform_device_register(&at91sam9g45_aes_device);
1956 static void __init at91_add_device_aes(void) {}
1959 /* -------------------------------------------------------------------- */
1961 * These devices are always present and don't need any board-specific
1964 static int __init at91_add_standard_devices(void)
1966 if (of_have_populated_dt())
1969 at91_add_device_hdmac();
1970 at91_add_device_rtc();
1971 at91_add_device_rtt();
1972 at91_add_device_trng();
1973 at91_add_device_watchdog();
1974 at91_add_device_tc();
1975 at91_add_device_sha();
1976 at91_add_device_tdes();
1977 at91_add_device_aes();
1981 arch_initcall(at91_add_standard_devices);