arch/arm/mach-at91/at91sam9260.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9260.c
   3  *
   4  *  Copyright (C) 2006 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/cpu.h>
  20 #include <mach/at91_dbgu.h>
  21 #include <mach/at91sam9260.h>
  22 #include <mach/at91_pmc.h>
  23 #include <mach/at91_rstc.h>
  24
  25 #include "soc.h"
  26 #include "generic.h"
  27 #include "clock.h"
  28 #include "sam9_smc.h"
  29
  30 /* --------------------------------------------------------------------
  31  *  Clocks
  32  * -------------------------------------------------------------------- */
  33
  34 /*
  35  * The peripheral clocks.
  36  */
  37 static struct clk pioA_clk = {
  38         .name           = "pioA_clk",
  39         .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
  40         .type           = CLK_TYPE_PERIPHERAL,
  41 };
  42 static struct clk pioB_clk = {
  43         .name           = "pioB_clk",
  44         .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
  45         .type           = CLK_TYPE_PERIPHERAL,
  46 };
  47 static struct clk pioC_clk = {
  48         .name           = "pioC_clk",
  49         .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
  50         .type           = CLK_TYPE_PERIPHERAL,
  51 };
  52 static struct clk adc_clk = {
  53         .name           = "adc_clk",
  54         .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
  55         .type           = CLK_TYPE_PERIPHERAL,
  56 };
  57 static struct clk usart0_clk = {
  58         .name           = "usart0_clk",
  59         .pmc_mask       = 1 << AT91SAM9260_ID_US0,
  60         .type           = CLK_TYPE_PERIPHERAL,
  61 };
  62 static struct clk usart1_clk = {
  63         .name           = "usart1_clk",
  64         .pmc_mask       = 1 << AT91SAM9260_ID_US1,
  65         .type           = CLK_TYPE_PERIPHERAL,
  66 };
  67 static struct clk usart2_clk = {
  68         .name           = "usart2_clk",
  69         .pmc_mask       = 1 << AT91SAM9260_ID_US2,
  70         .type           = CLK_TYPE_PERIPHERAL,
  71 };
  72 static struct clk mmc_clk = {
  73         .name           = "mci_clk",
  74         .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
  75         .type           = CLK_TYPE_PERIPHERAL,
  76 };
  77 static struct clk udc_clk = {
  78         .name           = "udc_clk",
  79         .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
  80         .type           = CLK_TYPE_PERIPHERAL,
  81 };
  82 static struct clk twi_clk = {
  83         .name           = "twi_clk",
  84         .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
  85         .type           = CLK_TYPE_PERIPHERAL,
  86 };
  87 static struct clk spi0_clk = {
  88         .name           = "spi0_clk",
  89         .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
  90         .type           = CLK_TYPE_PERIPHERAL,
  91 };
  92 static struct clk spi1_clk = {
  93         .name           = "spi1_clk",
  94         .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
  95         .type           = CLK_TYPE_PERIPHERAL,
  96 };
  97 static struct clk ssc_clk = {
  98         .name           = "ssc_clk",
  99         .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
 100         .type           = CLK_TYPE_PERIPHERAL,
 101 };
 102 static struct clk tc0_clk = {
 103         .name           = "tc0_clk",
 104         .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
 105         .type           = CLK_TYPE_PERIPHERAL,
 106 };
 107 static struct clk tc1_clk = {
 108         .name           = "tc1_clk",
 109         .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
 110         .type           = CLK_TYPE_PERIPHERAL,
 111 };
 112 static struct clk tc2_clk = {
 113         .name           = "tc2_clk",
 114         .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
 115         .type           = CLK_TYPE_PERIPHERAL,
 116 };
 117 static struct clk ohci_clk = {
 118         .name           = "ohci_clk",
 119         .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
 120         .type           = CLK_TYPE_PERIPHERAL,
 121 };
 122 static struct clk macb_clk = {
 123         .name           = "pclk",
 124         .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
 125         .type           = CLK_TYPE_PERIPHERAL,
 126 };
 127 static struct clk isi_clk = {
 128         .name           = "isi_clk",
 129         .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
 130         .type           = CLK_TYPE_PERIPHERAL,
 131 };
 132 static struct clk usart3_clk = {
 133         .name           = "usart3_clk",
 134         .pmc_mask       = 1 << AT91SAM9260_ID_US3,
 135         .type           = CLK_TYPE_PERIPHERAL,
 136 };
 137 static struct clk usart4_clk = {
 138         .name           = "usart4_clk",
 139         .pmc_mask       = 1 << AT91SAM9260_ID_US4,
 140         .type           = CLK_TYPE_PERIPHERAL,
 141 };
 142 static struct clk usart5_clk = {
 143         .name           = "usart5_clk",
 144         .pmc_mask       = 1 << AT91SAM9260_ID_US5,
 145         .type           = CLK_TYPE_PERIPHERAL,
 146 };
 147 static struct clk tc3_clk = {
 148         .name           = "tc3_clk",
 149         .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
 150         .type           = CLK_TYPE_PERIPHERAL,
 151 };
 152 static struct clk tc4_clk = {
 153         .name           = "tc4_clk",
 154         .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
 155         .type           = CLK_TYPE_PERIPHERAL,
 156 };
 157 static struct clk tc5_clk = {
 158         .name           = "tc5_clk",
 159         .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
 160         .type           = CLK_TYPE_PERIPHERAL,
 161 };
 162
 163 static struct clk *periph_clocks[] __initdata = {
 164         &pioA_clk,
 165         &pioB_clk,
 166         &pioC_clk,
 167         &adc_clk,
 168         &usart0_clk,
 169         &usart1_clk,
 170         &usart2_clk,
 171         &mmc_clk,
 172         &udc_clk,
 173         &twi_clk,
 174         &spi0_clk,
 175         &spi1_clk,
 176         &ssc_clk,
 177         &tc0_clk,
 178         &tc1_clk,
 179         &tc2_clk,
 180         &ohci_clk,
 181         &macb_clk,
 182         &isi_clk,
 183         &usart3_clk,
 184         &usart4_clk,
 185         &usart5_clk,
 186         &tc3_clk,
 187         &tc4_clk,
 188         &tc5_clk,
 189         // irq0 .. irq2
 190 };
 191
 192 static struct clk_lookup periph_clocks_lookups[] = {
 193         /* One additional fake clock for macb_hclk */
 194         CLKDEV_CON_ID("hclk", &macb_clk),
 195         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 196         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 197         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 198         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 199         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 200         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 201         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 202         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 203         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
 204         /* more usart lookup table for DT entries */
 205         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 206         CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
 207         CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
 208         CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
 209         CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
 210         CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
 211         CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
 212         /* more tc lookup table for DT entries */
 213         CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
 214         CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
 215         CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
 216         CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
 217         CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
 218         CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
 219         /* fake hclk clock */
 220         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 221         CLKDEV_CON_ID("pioA", &pioA_clk),
 222         CLKDEV_CON_ID("pioB", &pioB_clk),
 223         CLKDEV_CON_ID("pioC", &pioC_clk),
 224 };
 225
 226 static struct clk_lookup usart_clocks_lookups[] = {
 227         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 228         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 229         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 230         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 231         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 232         CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
 233         CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
 234 };
 235
 236 /*
 237  * The two programmable clocks.
 238  * You must configure pin multiplexing to bring these signals out.
 239  */
 240 static struct clk pck0 = {
 241         .name           = "pck0",
 242         .pmc_mask       = AT91_PMC_PCK0,
 243         .type           = CLK_TYPE_PROGRAMMABLE,
 244         .id             = 0,
 245 };
 246 static struct clk pck1 = {
 247         .name           = "pck1",
 248         .pmc_mask       = AT91_PMC_PCK1,
 249         .type           = CLK_TYPE_PROGRAMMABLE,
 250         .id             = 1,
 251 };
 252
 253 static void __init at91sam9260_register_clocks(void)
 254 {
 255         int i;
 256
 257         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 258                 clk_register(periph_clocks[i]);
 259
 260         clkdev_add_table(periph_clocks_lookups,
 261                          ARRAY_SIZE(periph_clocks_lookups));
 262         clkdev_add_table(usart_clocks_lookups,
 263                          ARRAY_SIZE(usart_clocks_lookups));
 264
 265         clk_register(&pck0);
 266         clk_register(&pck1);
 267 }
 268
 269 static struct clk_lookup console_clock_lookup;
 270
 271 void __init at91sam9260_set_console_clock(int id)
 272 {
 273         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 274                 return;
 275
 276         console_clock_lookup.con_id = "usart";
 277         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 278         clkdev_add(&console_clock_lookup);
 279 }
 280
 281 /* --------------------------------------------------------------------
 282  *  GPIO
 283  * -------------------------------------------------------------------- */
 284
 285 static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
 286         {
 287                 .id             = AT91SAM9260_ID_PIOA,
 288                 .regbase        = AT91SAM9260_BASE_PIOA,
 289         }, {
 290                 .id             = AT91SAM9260_ID_PIOB,
 291                 .regbase        = AT91SAM9260_BASE_PIOB,
 292         }, {
 293                 .id             = AT91SAM9260_ID_PIOC,
 294                 .regbase        = AT91SAM9260_BASE_PIOC,
 295         }
 296 };
 297
 298 /* --------------------------------------------------------------------
 299  *  AT91SAM9260 processor initialization
 300  * -------------------------------------------------------------------- */
 301
 302 static void __init at91sam9xe_map_io(void)
 303 {
 304         unsigned long sram_size;
 305
 306         switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
 307                 case AT91_CIDR_SRAMSIZ_32K:
 308                         sram_size = 2 * SZ_16K;
 309                         break;
 310                 case AT91_CIDR_SRAMSIZ_16K:
 311                 default:
 312                         sram_size = SZ_16K;
 313         }
 314
 315         at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
 316 }
 317
 318 static void __init at91sam9260_map_io(void)
 319 {
 320         if (cpu_is_at91sam9xe())
 321                 at91sam9xe_map_io();
 322         else if (cpu_is_at91sam9g20())
 323                 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
 324         else
 325                 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
 326 }
 327
 328 static void __init at91sam9260_ioremap_registers(void)
 329 {
 330         at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
 331         at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
 332         at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
 333         at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
 334         at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
 335         at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
 336 }
 337
 338 static void __init at91sam9260_initialize(void)
 339 {
 340         arm_pm_idle = at91sam9_idle;
 341         arm_pm_restart = at91sam9_alt_restart;
 342         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
 343                         | (1 << AT91SAM9260_ID_IRQ2);
 344
 345         /* Register GPIO subsystem */
 346         at91_gpio_init(at91sam9260_gpio, 3);
 347 }
 348
 349 /* --------------------------------------------------------------------
 350  *  Interrupt initialization
 351  * -------------------------------------------------------------------- */
 352
 353 /*
 354  * The default interrupt priority levels (0 = lowest, 7 = highest).
 355  */
 356 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 357         7,      /* Advanced Interrupt Controller */
 358         7,      /* System Peripherals */
 359         1,      /* Parallel IO Controller A */
 360         1,      /* Parallel IO Controller B */
 361         1,      /* Parallel IO Controller C */
 362         0,      /* Analog-to-Digital Converter */
 363         5,      /* USART 0 */
 364         5,      /* USART 1 */
 365         5,      /* USART 2 */
 366         0,      /* Multimedia Card Interface */
 367         2,      /* USB Device Port */
 368         6,      /* Two-Wire Interface */
 369         5,      /* Serial Peripheral Interface 0 */
 370         5,      /* Serial Peripheral Interface 1 */
 371         5,      /* Serial Synchronous Controller */
 372         0,
 373         0,
 374         0,      /* Timer Counter 0 */
 375         0,      /* Timer Counter 1 */
 376         0,      /* Timer Counter 2 */
 377         2,      /* USB Host port */
 378         3,      /* Ethernet */
 379         0,      /* Image Sensor Interface */
 380         5,      /* USART 3 */
 381         5,      /* USART 4 */
 382         5,      /* USART 5 */
 383         0,      /* Timer Counter 3 */
 384         0,      /* Timer Counter 4 */
 385         0,      /* Timer Counter 5 */
 386         0,      /* Advanced Interrupt Controller */
 387         0,      /* Advanced Interrupt Controller */
 388         0,      /* Advanced Interrupt Controller */
 389 };
 390
 391 struct at91_init_soc __initdata at91sam9260_soc = {
 392         .map_io = at91sam9260_map_io,
 393         .default_irq_priority = at91sam9260_default_irq_priority,
 394         .ioremap_registers = at91sam9260_ioremap_registers,
 395         .register_clocks = at91sam9260_register_clocks,
 396         .init = at91sam9260_initialize,
 397 };