2 * arch/arm/kernel/topology.c
4 * Copyright (C) 2011 Linaro Limited.
5 * Written by: Vincent Guittot
7 * based on arch/sh/kernel/topology.c
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/cpu.h>
15 #include <linux/cpumask.h>
16 #include <linux/export.h>
17 #include <linux/init.h>
18 #include <linux/percpu.h>
19 #include <linux/node.h>
20 #include <linux/nodemask.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
25 #include <asm/cputype.h>
26 #include <asm/topology.h>
29 * cpu capacity scale management
34 * This per cpu data structure describes the relative capacity of each core.
35 * On a heteregenous system, cores don't have the same computation capacity
36 * and we reflect that difference in the cpu_capacity field so the scheduler
37 * can take this difference into account during load balance. A per cpu
38 * structure is preferred because each CPU updates its own cpu_capacity field
39 * during the load balance except for idle cores. One idle core is selected
40 * to run the rebalance_domains for all idle cores and the cpu_capacity can be
41 * updated during this sequence.
43 static DEFINE_PER_CPU(unsigned long, cpu_scale);
45 unsigned long scale_cpu_capacity(struct sched_domain *sd, int cpu)
47 #ifdef CONFIG_CPU_FREQ
48 unsigned long max_freq_scale = cpufreq_scale_max_freq_capacity(cpu);
50 return per_cpu(cpu_scale, cpu) * max_freq_scale >> SCHED_CAPACITY_SHIFT;
52 return per_cpu(cpu_scale, cpu);
56 static void set_capacity_scale(unsigned int cpu, unsigned long capacity)
58 per_cpu(cpu_scale, cpu) = capacity;
62 struct cpu_efficiency {
63 const char *compatible;
64 unsigned long efficiency;
68 * Table of relative efficiency of each processors
69 * The efficiency value must fit in 20bit and the final
70 * cpu_scale value must be in the range
71 * 0 < cpu_scale < 3*SCHED_CAPACITY_SCALE/2
72 * in order to return at most 1 when DIV_ROUND_CLOSEST
73 * is used to compute the capacity of a CPU.
74 * Processors that are not defined in the table,
75 * use the default SCHED_CAPACITY_SCALE value for cpu_scale.
77 static const struct cpu_efficiency table_efficiency[] = {
78 {"arm,cortex-a15", 3891},
79 {"arm,cortex-a7", 2048},
83 static unsigned long *__cpu_capacity;
84 #define cpu_capacity(cpu) __cpu_capacity[cpu]
86 static unsigned long middle_capacity = 1;
89 * Iterate all CPUs' descriptor in DT and compute the efficiency
90 * (as per table_efficiency). Also calculate a middle efficiency
91 * as close as possible to (max{eff_i} - min{eff_i}) / 2
92 * This is later used to scale the cpu_capacity field such that an
93 * 'average' CPU is of middle capacity. Also see the comments near
94 * table_efficiency[] and update_cpu_capacity().
96 static void __init parse_dt_topology(void)
98 const struct cpu_efficiency *cpu_eff;
99 struct device_node *cn = NULL;
100 unsigned long min_capacity = ULONG_MAX;
101 unsigned long max_capacity = 0;
102 unsigned long capacity = 0;
105 __cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity),
108 for_each_possible_cpu(cpu) {
112 /* too early to use cpu->of_node */
113 cn = of_get_cpu_node(cpu, NULL);
115 pr_err("missing device node for CPU %d\n", cpu);
119 for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++)
120 if (of_device_is_compatible(cn, cpu_eff->compatible))
123 if (cpu_eff->compatible == NULL)
126 rate = of_get_property(cn, "clock-frequency", &len);
127 if (!rate || len != 4) {
128 pr_err("%s missing clock-frequency property\n",
133 capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency;
135 /* Save min capacity of the system */
136 if (capacity < min_capacity)
137 min_capacity = capacity;
139 /* Save max capacity of the system */
140 if (capacity > max_capacity)
141 max_capacity = capacity;
143 cpu_capacity(cpu) = capacity;
146 /* If min and max capacities are equals, we bypass the update of the
147 * cpu_scale because all CPUs have the same capacity. Otherwise, we
148 * compute a middle_capacity factor that will ensure that the capacity
149 * of an 'average' CPU of the system will be as close as possible to
150 * SCHED_CAPACITY_SCALE, which is the default value, but with the
151 * constraint explained near table_efficiency[].
153 if (4*max_capacity < (3*(max_capacity + min_capacity)))
154 middle_capacity = (min_capacity + max_capacity)
155 >> (SCHED_CAPACITY_SHIFT+1);
157 middle_capacity = ((max_capacity / 3)
158 >> (SCHED_CAPACITY_SHIFT-1)) + 1;
162 static const struct sched_group_energy * const cpu_core_energy(int cpu);
165 * Look for a customed capacity of a CPU in the cpu_capacity table during the
166 * boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
167 * function returns directly for SMP system.
169 static void update_cpu_capacity(unsigned int cpu)
171 unsigned long capacity = SCHED_CAPACITY_SCALE;
173 if (cpu_core_energy(cpu)) {
174 int max_cap_idx = cpu_core_energy(cpu)->nr_cap_states - 1;
175 capacity = cpu_core_energy(cpu)->cap_states[max_cap_idx].cap;
178 set_capacity_scale(cpu, capacity);
180 pr_info("CPU%u: update cpu_capacity %lu\n",
181 cpu, arch_scale_cpu_capacity(NULL, cpu));
185 static inline void parse_dt_topology(void) {}
186 static inline void update_cpu_capacity(unsigned int cpuid) {}
192 struct cputopo_arm cpu_topology[NR_CPUS];
193 EXPORT_SYMBOL_GPL(cpu_topology);
195 const struct cpumask *cpu_coregroup_mask(int cpu)
197 return &cpu_topology[cpu].core_sibling;
201 * The current assumption is that we can power gate each core independently.
202 * This will be superseded by DT binding once available.
204 const struct cpumask *cpu_corepower_mask(int cpu)
206 return &cpu_topology[cpu].thread_sibling;
209 static void update_siblings_masks(unsigned int cpuid)
211 struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
214 /* update core and thread sibling masks */
215 for_each_possible_cpu(cpu) {
216 cpu_topo = &cpu_topology[cpu];
218 if (cpuid_topo->socket_id != cpu_topo->socket_id)
221 cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
223 cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
225 if (cpuid_topo->core_id != cpu_topo->core_id)
228 cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
230 cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
236 * store_cpu_topology is called at boot when only one cpu is running
237 * and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
238 * which prevents simultaneous write access to cpu_topology array
240 void store_cpu_topology(unsigned int cpuid)
242 struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid];
245 /* If the cpu topology has been already set, just return */
246 if (cpuid_topo->core_id != -1)
249 mpidr = read_cpuid_mpidr();
251 /* create cpu topology mapping */
252 if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) {
254 * This is a multiprocessor system
255 * multiprocessor format & multiprocessor mode field are set
258 if (mpidr & MPIDR_MT_BITMASK) {
259 /* core performance interdependency */
260 cpuid_topo->thread_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
261 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
262 cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
264 /* largely independent cores */
265 cpuid_topo->thread_id = -1;
266 cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
267 cpuid_topo->socket_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
271 * This is an uniprocessor system
272 * we are in multiprocessor format but uniprocessor system
273 * or in the old uniprocessor format
275 cpuid_topo->thread_id = -1;
276 cpuid_topo->core_id = 0;
277 cpuid_topo->socket_id = -1;
280 update_siblings_masks(cpuid);
282 update_cpu_capacity(cpuid);
284 pr_info("CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",
285 cpuid, cpu_topology[cpuid].thread_id,
286 cpu_topology[cpuid].core_id,
287 cpu_topology[cpuid].socket_id, mpidr);
291 * ARM TC2 specific energy cost model data. There are no unit requirements for
292 * the data. Data can be normalized to any reference point, but the
293 * normalization must be consistent. That is, one bogo-joule/watt must be the
294 * same quantity for all data, but we don't care what it is.
296 static struct idle_state idle_states_cluster_a7[] = {
297 { .power = 25 }, /* arch_cpu_idle() (active idle) = WFI */
298 { .power = 25 }, /* WFI */
299 { .power = 10 }, /* cluster-sleep-l */
302 static struct idle_state idle_states_cluster_a15[] = {
303 { .power = 70 }, /* arch_cpu_idle() (active idle) = WFI */
304 { .power = 70 }, /* WFI */
305 { .power = 25 }, /* cluster-sleep-b */
308 static struct capacity_state cap_states_cluster_a7[] = {
309 /* Cluster only power */
310 { .cap = 150, .power = 2967, }, /* 350 MHz */
311 { .cap = 172, .power = 2792, }, /* 400 MHz */
312 { .cap = 215, .power = 2810, }, /* 500 MHz */
313 { .cap = 258, .power = 2815, }, /* 600 MHz */
314 { .cap = 301, .power = 2919, }, /* 700 MHz */
315 { .cap = 344, .power = 2847, }, /* 800 MHz */
316 { .cap = 387, .power = 3917, }, /* 900 MHz */
317 { .cap = 430, .power = 4905, }, /* 1000 MHz */
320 static struct capacity_state cap_states_cluster_a15[] = {
321 /* Cluster only power */
322 { .cap = 426, .power = 7920, }, /* 500 MHz */
323 { .cap = 512, .power = 8165, }, /* 600 MHz */
324 { .cap = 597, .power = 8172, }, /* 700 MHz */
325 { .cap = 682, .power = 8195, }, /* 800 MHz */
326 { .cap = 768, .power = 8265, }, /* 900 MHz */
327 { .cap = 853, .power = 8446, }, /* 1000 MHz */
328 { .cap = 938, .power = 11426, }, /* 1100 MHz */
329 { .cap = 1024, .power = 15200, }, /* 1200 MHz */
332 static struct sched_group_energy energy_cluster_a7 = {
333 .nr_idle_states = ARRAY_SIZE(idle_states_cluster_a7),
334 .idle_states = idle_states_cluster_a7,
335 .nr_cap_states = ARRAY_SIZE(cap_states_cluster_a7),
336 .cap_states = cap_states_cluster_a7,
339 static struct sched_group_energy energy_cluster_a15 = {
340 .nr_idle_states = ARRAY_SIZE(idle_states_cluster_a15),
341 .idle_states = idle_states_cluster_a15,
342 .nr_cap_states = ARRAY_SIZE(cap_states_cluster_a15),
343 .cap_states = cap_states_cluster_a15,
346 static struct idle_state idle_states_core_a7[] = {
347 { .power = 0 }, /* arch_cpu_idle (active idle) = WFI */
348 { .power = 0 }, /* WFI */
349 { .power = 0 }, /* cluster-sleep-l */
352 static struct idle_state idle_states_core_a15[] = {
353 { .power = 0 }, /* arch_cpu_idle (active idle) = WFI */
354 { .power = 0 }, /* WFI */
355 { .power = 0 }, /* cluster-sleep-b */
358 static struct capacity_state cap_states_core_a7[] = {
360 { .cap = 150, .power = 187, }, /* 350 MHz */
361 { .cap = 172, .power = 275, }, /* 400 MHz */
362 { .cap = 215, .power = 334, }, /* 500 MHz */
363 { .cap = 258, .power = 407, }, /* 600 MHz */
364 { .cap = 301, .power = 447, }, /* 700 MHz */
365 { .cap = 344, .power = 549, }, /* 800 MHz */
366 { .cap = 387, .power = 761, }, /* 900 MHz */
367 { .cap = 430, .power = 1024, }, /* 1000 MHz */
370 static struct capacity_state cap_states_core_a15[] = {
372 { .cap = 426, .power = 2021, }, /* 500 MHz */
373 { .cap = 512, .power = 2312, }, /* 600 MHz */
374 { .cap = 597, .power = 2756, }, /* 700 MHz */
375 { .cap = 682, .power = 3125, }, /* 800 MHz */
376 { .cap = 768, .power = 3524, }, /* 900 MHz */
377 { .cap = 853, .power = 3846, }, /* 1000 MHz */
378 { .cap = 938, .power = 5177, }, /* 1100 MHz */
379 { .cap = 1024, .power = 6997, }, /* 1200 MHz */
382 static struct sched_group_energy energy_core_a7 = {
383 .nr_idle_states = ARRAY_SIZE(idle_states_core_a7),
384 .idle_states = idle_states_core_a7,
385 .nr_cap_states = ARRAY_SIZE(cap_states_core_a7),
386 .cap_states = cap_states_core_a7,
389 static struct sched_group_energy energy_core_a15 = {
390 .nr_idle_states = ARRAY_SIZE(idle_states_core_a15),
391 .idle_states = idle_states_core_a15,
392 .nr_cap_states = ARRAY_SIZE(cap_states_core_a15),
393 .cap_states = cap_states_core_a15,
396 /* sd energy functions */
398 const struct sched_group_energy * const cpu_cluster_energy(int cpu)
400 return cpu_topology[cpu].socket_id ? &energy_cluster_a7 :
405 const struct sched_group_energy * const cpu_core_energy(int cpu)
407 return cpu_topology[cpu].socket_id ? &energy_core_a7 :
411 static inline int cpu_corepower_flags(void)
413 return SD_SHARE_PKG_RESOURCES | SD_SHARE_POWERDOMAIN | \
417 static struct sched_domain_topology_level arm_topology[] = {
418 #ifdef CONFIG_SCHED_MC
419 { cpu_coregroup_mask, cpu_corepower_flags, cpu_core_energy, SD_INIT_NAME(MC) },
421 { cpu_cpu_mask, NULL, cpu_cluster_energy, SD_INIT_NAME(DIE) },
426 * init_cpu_topology is called at boot when only one cpu is running
427 * which prevent simultaneous write access to cpu_topology array
429 void __init init_cpu_topology(void)
433 /* init core mask and capacity */
434 for_each_possible_cpu(cpu) {
435 struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);
437 cpu_topo->thread_id = -1;
438 cpu_topo->core_id = -1;
439 cpu_topo->socket_id = -1;
440 cpumask_clear(&cpu_topo->core_sibling);
441 cpumask_clear(&cpu_topo->thread_sibling);
443 set_capacity_scale(cpu, SCHED_CAPACITY_SCALE);
449 /* Set scheduler topology descriptor */
450 set_sched_topology(arm_topology);